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1/*
2 * Trantor T128/T128F/T228 defines
3 * Note : architecturally, the T100 and T128 are different and won't work
4 *
5 * Copyright 1993, Drew Eckhardt
6 * Visionary Computing
7 * (Unix and Linux consulting and custom programming)
8 * drew@colorado.edu
9 * +1 (303) 440-4894
10 *
11 * For more information, please consult
12 *
13 * Trantor Systems, Ltd.
14 * T128/T128F/T228 SCSI Host Adapter
15 * Hardware Specifications
16 *
17 * Trantor Systems, Ltd.
18 * 5415 Randall Place
19 * Fremont, CA 94538
20 * 1+ (415) 770-1400, FAX 1+ (415) 770-9910
21 */
22
23#ifndef T128_H
24#define T128_H
25
26/*
27 * The trantor boards are memory mapped. They use an NCR5380 or
28 * equivalent (my sample board had part second sourced from ZILOG).
29 * NCR's recommended "Pseudo-DMA" architecture is used, where
30 * a PAL drives the DMA signals on the 5380 allowing fast, blind
31 * transfers with proper handshaking.
32 */
33
34/*
35 * Note : a boot switch is provided for the purpose of informing the
36 * firmware to boot or not boot from attached SCSI devices. So, I imagine
37 * there are fewer people who've yanked the ROM like they do on the Seagate
38 * to make bootup faster, and I'll probably use this for autodetection.
39 */
40#define T_ROM_OFFSET 0
41
42/*
43 * Note : my sample board *WAS NOT* populated with the SRAM, so this
44 * can't be used for autodetection without a ROM present.
45 */
46#define T_RAM_OFFSET 0x1800
47
48/*
49 * All of the registers are allocated 32 bytes of address space, except
50 * for the data register (read/write to/from the 5380 in pseudo-DMA mode)
51 */
52#define T_CONTROL_REG_OFFSET 0x1c00 /* rw */
53#define T_CR_INT 0x10 /* Enable interrupts */
54#define T_CR_CT 0x02 /* Reset watchdog timer */
55
56#define T_STATUS_REG_OFFSET 0x1c20 /* ro */
57#define T_ST_BOOT 0x80 /* Boot switch */
58#define T_ST_S3 0x40 /* User settable switches, */
59#define T_ST_S2 0x20 /* read 0 when switch is on, 1 off */
60#define T_ST_S1 0x10
61#define T_ST_PS2 0x08 /* Set for Microchannel 228 */
62#define T_ST_RDY 0x04 /* 5380 DRQ */
63#define T_ST_TIM 0x02 /* indicates 40us watchdog timer fired */
64#define T_ST_ZERO 0x01 /* Always zero */
65
66#define T_5380_OFFSET 0x1d00 /* 8 registers here, see NCR5380.h */
67
68#define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */
69
70#define NCR5380_implementation_fields \
71 void __iomem *base
72
73#define T128_address(reg) \
74 (((struct NCR5380_hostdata *)shost_priv(instance))->base + T_5380_OFFSET + ((reg) * 0x20))
75
76#define NCR5380_read(reg) readb(T128_address(reg))
77#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
78
79#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
80
81#define NCR5380_intr t128_intr
82#define NCR5380_queue_command t128_queue_command
83#define NCR5380_abort t128_abort
84#define NCR5380_bus_reset t128_bus_reset
85#define NCR5380_info t128_info
86#define NCR5380_show_info t128_show_info
87#define NCR5380_write_info t128_write_info
88
89/* 15 14 12 10 7 5 3
90 1101 0100 1010 1000 */
91
92#define T128_IRQS 0xc4a8
93
94#endif /* T128_H */