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1/*
2 * NCR 5380 defines
3 *
4 * Copyright 1993, Drew Eckhardt
5 * Visionary Computing
6 * (Unix consulting and custom programming)
7 * drew@colorado.edu
8 * +1 (303) 666-5836
9 *
10 * For more information, please consult
11 *
12 * NCR 5380 Family
13 * SCSI Protocol Controller
14 * Databook
15 * NCR Microelectronics
16 * 1635 Aeroplaza Drive
17 * Colorado Springs, CO 80916
18 * 1+ (719) 578-3400
19 * 1+ (800) 334-5454
20 */
21
22#ifndef NCR5380_H
23#define NCR5380_H
24
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/list.h>
28#include <linux/workqueue.h>
29#include <scsi/scsi_dbg.h>
30#include <scsi/scsi_eh.h>
31#include <scsi/scsi_transport_spi.h>
32
33#define NDEBUG_ARBITRATION 0x1
34#define NDEBUG_AUTOSENSE 0x2
35#define NDEBUG_DMA 0x4
36#define NDEBUG_HANDSHAKE 0x8
37#define NDEBUG_INFORMATION 0x10
38#define NDEBUG_INIT 0x20
39#define NDEBUG_INTR 0x40
40#define NDEBUG_LINKED 0x80
41#define NDEBUG_MAIN 0x100
42#define NDEBUG_NO_DATAOUT 0x200
43#define NDEBUG_NO_WRITE 0x400
44#define NDEBUG_PIO 0x800
45#define NDEBUG_PSEUDO_DMA 0x1000
46#define NDEBUG_QUEUES 0x2000
47#define NDEBUG_RESELECTION 0x4000
48#define NDEBUG_SELECTION 0x8000
49#define NDEBUG_USLEEP 0x10000
50#define NDEBUG_LAST_BYTE_SENT 0x20000
51#define NDEBUG_RESTART_SELECT 0x40000
52#define NDEBUG_EXTENDED 0x80000
53#define NDEBUG_C400_PREAD 0x100000
54#define NDEBUG_C400_PWRITE 0x200000
55#define NDEBUG_LISTS 0x400000
56#define NDEBUG_ABORT 0x800000
57#define NDEBUG_TAGS 0x1000000
58#define NDEBUG_MERGING 0x2000000
59
60#define NDEBUG_ANY 0xFFFFFFFFUL
61
62/*
63 * The contents of the OUTPUT DATA register are asserted on the bus when
64 * either arbitration is occurring or the phase-indicating signals (
65 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
66 * bit in the INITIATOR COMMAND register is set.
67 */
68
69#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
70#define CURRENT_SCSI_DATA_REG 0 /* ro same */
71
72#define INITIATOR_COMMAND_REG 1 /* rw */
73#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
74#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
75#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
76#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
77#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
78#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
79#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
80#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
81#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
82#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
83
84#ifdef DIFFERENTIAL
85#define ICR_BASE ICR_DIFF_ENABLE
86#else
87#define ICR_BASE 0
88#endif
89
90#define MODE_REG 2
91/*
92 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
93 * transfer, causing the chip to hog the bus. You probably don't want
94 * this.
95 */
96#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
97#define MR_TARGET 0x40 /* rw target mode */
98#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
99#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
100#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
101#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
102#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
103#define MR_ARBITRATE 0x01 /* rw start arbitration */
104
105#ifdef PARITY
106#define MR_BASE MR_ENABLE_PAR_CHECK
107#else
108#define MR_BASE 0
109#endif
110
111#define TARGET_COMMAND_REG 3
112#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
113#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
114#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
115#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
116#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
117
118#define STATUS_REG 4 /* ro */
119/*
120 * Note : a set bit indicates an active signal, driven by us or another
121 * device.
122 */
123#define SR_RST 0x80
124#define SR_BSY 0x40
125#define SR_REQ 0x20
126#define SR_MSG 0x10
127#define SR_CD 0x08
128#define SR_IO 0x04
129#define SR_SEL 0x02
130#define SR_DBP 0x01
131
132/*
133 * Setting a bit in this register will cause an interrupt to be generated when
134 * BSY is false and SEL true and this bit is asserted on the bus.
135 */
136#define SELECT_ENABLE_REG 4 /* wo */
137
138#define BUS_AND_STATUS_REG 5 /* ro */
139#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
140#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
141#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
142#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
143#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
144#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
145#define BASR_ATN 0x02 /* ro BUS status */
146#define BASR_ACK 0x01 /* ro BUS status */
147
148/* Write any value to this register to start a DMA send */
149#define START_DMA_SEND_REG 5 /* wo */
150
151/*
152 * Used in DMA transfer mode, data is latched from the SCSI bus on
153 * the falling edge of REQ (ini) or ACK (tgt)
154 */
155#define INPUT_DATA_REG 6 /* ro */
156
157/* Write any value to this register to start a DMA receive */
158#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
159
160/* Read this register to clear interrupt conditions */
161#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
162
163/* Write any value to this register to start an ini mode DMA receive */
164#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
165
166/* NCR 53C400(A) Control Status Register bits: */
167#define CSR_RESET 0x80 /* wo Resets 53c400 */
168#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
169#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
170#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
171#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
172#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
173#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
174#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
175#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
176
177#if 0
178#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
179#else
180#define CSR_BASE CSR_53C80_INTR
181#endif
182
183/* Note : PHASE_* macros are based on the values of the STATUS register */
184#define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
185
186#define PHASE_DATAOUT 0
187#define PHASE_DATAIN SR_IO
188#define PHASE_CMDOUT SR_CD
189#define PHASE_STATIN (SR_CD | SR_IO)
190#define PHASE_MSGOUT (SR_MSG | SR_CD)
191#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
192#define PHASE_UNKNOWN 0xff
193
194/*
195 * Convert status register phase to something we can use to set phase in
196 * the target register so we can get phase mismatch interrupts on DMA
197 * transfers.
198 */
199
200#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
201
202/*
203 * "Special" value for the (unsigned char) command tag, to indicate
204 * I_T_L nexus instead of I_T_L_Q.
205 */
206
207#define TAG_NONE 0xff
208
209/*
210 * These are "special" values for the irq and dma_channel fields of the
211 * Scsi_Host structure
212 */
213
214#define DMA_NONE 255
215#define IRQ_AUTO 254
216#define DMA_AUTO 254
217#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
218
219#ifndef NO_IRQ
220#define NO_IRQ 0
221#endif
222
223#define FLAG_NO_DMA_FIXUP 1 /* No DMA errata workarounds */
224#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
225#define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */
226#define FLAG_TAGGED_QUEUING 64 /* as X3T9.2 spelled it */
227#define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */
228
229#ifdef SUPPORT_TAGS
230struct tag_alloc {
231 DECLARE_BITMAP(allocated, MAX_TAGS);
232 int nr_allocated;
233 int queue_size;
234};
235#endif
236
237struct NCR5380_hostdata {
238 NCR5380_implementation_fields; /* implementation specific */
239 struct Scsi_Host *host; /* Host backpointer */
240 unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
241 unsigned char busy[8]; /* index = target, bit = lun */
242#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
243 int dma_len; /* requested length of DMA */
244#endif
245 unsigned char last_message; /* last message OUT */
246 struct scsi_cmnd *connected; /* currently connected cmnd */
247 struct scsi_cmnd *selecting; /* cmnd to be connected */
248 struct list_head unissued; /* waiting to be issued */
249 struct list_head autosense; /* priority issue queue */
250 struct list_head disconnected; /* waiting for reconnect */
251 spinlock_t lock; /* protects this struct */
252 int flags;
253 struct scsi_eh_save ses;
254 struct scsi_cmnd *sensing;
255 char info[256];
256 int read_overruns; /* number of bytes to cut from a
257 * transfer to handle chip overruns */
258 struct work_struct main_task;
259#ifdef SUPPORT_TAGS
260 struct tag_alloc TagAlloc[8][8]; /* 8 targets and 8 LUNs */
261#endif
262#ifdef PSEUDO_DMA
263 unsigned spin_max_r;
264 unsigned spin_max_w;
265#endif
266 struct workqueue_struct *work_q;
267 unsigned long accesses_per_ms; /* chip register accesses per ms */
268};
269
270#ifdef __KERNEL__
271
272struct NCR5380_cmd {
273 struct list_head list;
274};
275
276#define NCR5380_CMD_SIZE (sizeof(struct NCR5380_cmd))
277
278static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr)
279{
280 return ((struct scsi_cmnd *)ncmd_ptr) - 1;
281}
282
283#ifndef NDEBUG
284#define NDEBUG (0)
285#endif
286
287#define dprintk(flg, fmt, ...) \
288 do { if ((NDEBUG) & (flg)) \
289 printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
290
291#define dsprintk(flg, host, fmt, ...) \
292 do { if ((NDEBUG) & (flg)) \
293 shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
294 } while (0)
295
296#if NDEBUG
297#define NCR5380_dprint(flg, arg) \
298 do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
299#define NCR5380_dprint_phase(flg, arg) \
300 do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
301static void NCR5380_print_phase(struct Scsi_Host *instance);
302static void NCR5380_print(struct Scsi_Host *instance);
303#else
304#define NCR5380_dprint(flg, arg) do {} while (0)
305#define NCR5380_dprint_phase(flg, arg) do {} while (0)
306#endif
307
308#if defined(AUTOPROBE_IRQ)
309static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
310#endif
311static int NCR5380_init(struct Scsi_Host *instance, int flags);
312static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
313static void NCR5380_exit(struct Scsi_Host *instance);
314static void NCR5380_information_transfer(struct Scsi_Host *instance);
315#ifndef DONT_USE_INTR
316static irqreturn_t NCR5380_intr(int irq, void *dev_id);
317#endif
318static void NCR5380_main(struct work_struct *work);
319static const char *NCR5380_info(struct Scsi_Host *instance);
320static void NCR5380_reselect(struct Scsi_Host *instance);
321static struct scsi_cmnd *NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *);
322#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
323static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
324#endif
325static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
326
327#if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
328
329#if defined(i386) || defined(__alpha__)
330
331/**
332 * NCR5380_pc_dma_setup - setup ISA DMA
333 * @instance: adapter to set up
334 * @ptr: block to transfer (virtual address)
335 * @count: number of bytes to transfer
336 * @mode: DMA controller mode to use
337 *
338 * Program the DMA controller ready to perform an ISA DMA transfer
339 * on this chip.
340 *
341 * Locks: takes and releases the ISA DMA lock.
342 */
343
344static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
345{
346 unsigned limit;
347 unsigned long bus_addr = virt_to_bus(ptr);
348 unsigned long flags;
349
350 if (instance->dma_channel <= 3) {
351 if (count > 65536)
352 count = 65536;
353 limit = 65536 - (bus_addr & 0xFFFF);
354 } else {
355 if (count > 65536 * 2)
356 count = 65536 * 2;
357 limit = 65536 * 2 - (bus_addr & 0x1FFFF);
358 }
359
360 if (count > limit)
361 count = limit;
362
363 if ((count & 1) || (bus_addr & 1))
364 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
365
366 flags=claim_dma_lock();
367 disable_dma(instance->dma_channel);
368 clear_dma_ff(instance->dma_channel);
369 set_dma_addr(instance->dma_channel, bus_addr);
370 set_dma_count(instance->dma_channel, count);
371 set_dma_mode(instance->dma_channel, mode);
372 enable_dma(instance->dma_channel);
373 release_dma_lock(flags);
374
375 return count;
376}
377
378/**
379 * NCR5380_pc_dma_write_setup - setup ISA DMA write
380 * @instance: adapter to set up
381 * @ptr: block to transfer (virtual address)
382 * @count: number of bytes to transfer
383 *
384 * Program the DMA controller ready to perform an ISA DMA write to the
385 * SCSI controller.
386 *
387 * Locks: called routines take and release the ISA DMA lock.
388 */
389
390static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
391{
392 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
393}
394
395/**
396 * NCR5380_pc_dma_read_setup - setup ISA DMA read
397 * @instance: adapter to set up
398 * @ptr: block to transfer (virtual address)
399 * @count: number of bytes to transfer
400 *
401 * Program the DMA controller ready to perform an ISA DMA read from the
402 * SCSI controller.
403 *
404 * Locks: called routines take and release the ISA DMA lock.
405 */
406
407static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
408{
409 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
410}
411
412/**
413 * NCR5380_pc_dma_residual - return bytes left
414 * @instance: adapter
415 *
416 * Reports the number of bytes left over after the DMA was terminated.
417 *
418 * Locks: takes and releases the ISA DMA lock.
419 */
420
421static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
422{
423 unsigned long flags;
424 int tmp;
425
426 flags = claim_dma_lock();
427 clear_dma_ff(instance->dma_channel);
428 tmp = get_dma_residue(instance->dma_channel);
429 release_dma_lock(flags);
430
431 return tmp;
432}
433#endif /* defined(i386) || defined(__alpha__) */
434#endif /* defined(REAL_DMA) */
435#endif /* __KERNEL__ */
436#endif /* NCR5380_H */