tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * r8a7791 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2014-2015 Cogent Embedded, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13
14#include "core.h"
15#include "sh_pfc.h"
16
17#define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_32(0, fn, sfx), \
19 PORT_GP_26(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_32(3, fn, sfx), \
22 PORT_GP_32(4, fn, sfx), \
23 PORT_GP_32(5, fn, sfx), \
24 PORT_GP_32(6, fn, sfx), \
25 PORT_GP_26(7, fn, sfx)
26
27enum {
28 PINMUX_RESERVED = 0,
29
30 PINMUX_DATA_BEGIN,
31 GP_ALL(DATA),
32 PINMUX_DATA_END,
33
34 PINMUX_FUNCTION_BEGIN,
35 GP_ALL(FN),
36
37 /* GPSR0 */
38 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
39 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
40 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
41 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
42 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
43 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
44
45 /* GPSR1 */
46 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
47 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
48 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
49 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
50 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
51 FN_IP3_21_20,
52
53 /* GPSR2 */
54 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
55 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
56 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
57 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
58 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
59 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
60 FN_IP6_5_3, FN_IP6_7_6,
61
62 /* GPSR3 */
63 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
64 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
65 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
66 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
67 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
68 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
69 FN_IP9_18_17,
70
71 /* GPSR4 */
72 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
73 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
74 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
75 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
76 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
77 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
78 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
79 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
80
81 /* GPSR5 */
82 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
83 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
84 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
85 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
86 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
87 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
88 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
89
90 /* GPSR6 */
91 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
92 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
93 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
94 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
95 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
96 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
97 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
98 FN_USB1_OVC, FN_DU0_DOTCLKIN,
99
100 /* GPSR7 */
101 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
102 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
103 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
104 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
105 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
106 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
107
108 /* IPSR0 */
109 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
110 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
111 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
112 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
113 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
114 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
115
116 /* IPSR1 */
117 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
118 FN_A9, FN_MSIOF1_SS2, FN_SDA0,
119 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
120 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
121 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
122 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
123 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
124 FN_A15, FN_BPFCLK_C,
125 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
126 FN_A17, FN_DACK2_B, FN_SDA0_C,
127 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
128
129 /* IPSR2 */
130 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
131 FN_A20, FN_SPCLK,
132 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
133 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
134 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
135 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
136 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
137 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
138 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
139 FN_EX_CS1_N, FN_MSIOF2_SCK,
140 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
141 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
142
143 /* IPSR3 */
144 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
145 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
146 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
147 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
148 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
149 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
150 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
151 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
152 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
153 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
154 FN_DACK0, FN_DRACK0, FN_REMOCON,
155 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
156 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
157 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
158 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
159
160 /* IPSR4 */
161 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
162 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
163 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
164 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
165 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
166 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
167 FN_GLO_Q1_D, FN_HCTS1_N_E,
168 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
169 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
170 FN_SSI_SCK4, FN_GLO_SS_D,
171 FN_SSI_WS4, FN_GLO_RFON_D,
172 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
173 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
174 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
175
176 /* IPSR5 */
177 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
178 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
179 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
180 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
181 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
182 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
183 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
184 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
185 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
186 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
187 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
188 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
189 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
190 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
191 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
192
193 /* IPSR6 */
194 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
195 FN_SCIF_CLK, FN_BPFCLK_E,
196 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
197 FN_SCIFA2_RXD, FN_FMIN_E,
198 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
199 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
200 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
201 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
202 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
203 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
204 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
205 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
206 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
207 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
208
209 /* IPSR7 */
210 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
211 FN_SCIF_CLK_B, FN_GPS_MAG_D,
212 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
213 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
214 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
215 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
216 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
217 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
218 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
219 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
220 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
221 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
222 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
223 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
224 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
225 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
226 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
227 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
228
229 /* IPSR8 */
230 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
231 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
232 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
233 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
234 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
235 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
236 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
237 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
238 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
239 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
240 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
241 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
242 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
243 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
244 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
245 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
246 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
247
248 /* IPSR9 */
249 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
250 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
251 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
252 FN_DU1_DOTCLKOUT0, FN_QCLK,
253 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
254 FN_TX3_B, FN_SCL2_B, FN_PWM4,
255 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
256 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
257 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
258 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
259 FN_DU1_DISP, FN_QPOLA,
260 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
261 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
262 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
263 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
264 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
265 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
266 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
267 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
268
269 /* IPSR10 */
270 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
271 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
272 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
273 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
274 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
275 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
276 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
277 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
278 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
279 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
280 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
281 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
282 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
283 FN_TS_SDATA0_C, FN_ATACS11_N,
284 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
285 FN_TS_SCK0_C, FN_ATAG1_N,
286 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
287 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
288 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
289
290 /* IPSR11 */
291 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
292 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
293 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
294 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
295 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
296 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
297 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
298 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
299 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
300 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
301 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
302 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
303 FN_VI1_DATA7, FN_AVB_MDC,
304 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
305 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
306
307 /* IPSR12 */
308 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
309 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
310 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
311 FN_SCL2_D, FN_MSIOF1_RXD_E,
312 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
313 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
314 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
315 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
316 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
317 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
318 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
319 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
320 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
321 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
322 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
323 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
324 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
325
326 /* IPSR13 */
327 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
328 FN_ADICLK_B, FN_MSIOF0_SS1_C,
329 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
330 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
331 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
332 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
333 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
334 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
335 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
336 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
337 FN_SCIFA5_TXD_B, FN_TX3_C,
338 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
339 FN_SCIFA5_RXD_B, FN_RX3_C,
340 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
341 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
342 FN_SD1_DATA3, FN_IERX_B,
343 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
344
345 /* IPSR14 */
346 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
347 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
348 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
349 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
350 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
351 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
352 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
353 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
354 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
355 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
356 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
357 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
358 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
359 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
360
361 /* IPSR15 */
362 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
363 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
364 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
365 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
366 FN_PWM5_B, FN_SCIFA3_TXD_C,
367 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
368 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
369 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
370 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
371 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
372 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
373 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
374 FN_TCLK2, FN_VI1_DATA3_C,
375 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
376 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
377
378 /* IPSR16 */
379 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
380 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
381 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
382 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
383 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
384
385 /* MOD_SEL */
386 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
387 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
388 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
389 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
390 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
391 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
392 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
393 FN_SEL_QSP_0, FN_SEL_QSP_1,
394 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
395 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
396 FN_SEL_HSCIF1_4,
397 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
398 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
399 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
400 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
401 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
402
403 /* MOD_SEL2 */
404 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
405 FN_SEL_SCIF0_4,
406 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
407 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
408 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
409 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
410 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
411 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
412 FN_SEL_ADG_0, FN_SEL_ADG_1,
413 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
414 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
415 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
416 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
417 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
418 FN_SEL_SIM_0, FN_SEL_SIM_1,
419 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
420
421 /* MOD_SEL3 */
422 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
423 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
424 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
425 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
426 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
427 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
428 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
429 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
430 FN_SEL_MMC_0, FN_SEL_MMC_1,
431 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
432 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
433 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
434 FN_SEL_IIC1_4,
435 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
436
437 /* MOD_SEL4 */
438 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
439 FN_SEL_SOF1_4,
440 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
441 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
442 FN_SEL_RAD_0, FN_SEL_RAD_1,
443 FN_SEL_RCN_0, FN_SEL_RCN_1,
444 FN_SEL_RSP_0, FN_SEL_RSP_1,
445 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
446 FN_SEL_SCIF2_4,
447 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
448 FN_SEL_SOF2_4,
449 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
450 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
451 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
452 PINMUX_FUNCTION_END,
453
454 PINMUX_MARK_BEGIN,
455
456 EX_CS0_N_MARK, RD_N_MARK,
457
458 AUDIO_CLKA_MARK,
459
460 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
461 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
462 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
463
464 SD1_CLK_MARK,
465
466 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
467 DU0_DOTCLKIN_MARK,
468
469 /* IPSR0 */
470 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
471 D6_MARK, D7_MARK, D8_MARK,
472 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
473 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
474 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
475 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
476 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
477
478 /* IPSR1 */
479 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
480 A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
481 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
482 A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
483 A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
484 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
485 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
486 A15_MARK, BPFCLK_C_MARK,
487 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
488 A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
489 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
490
491 /* IPSR2 */
492 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
493 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
494 A20_MARK, SPCLK_MARK,
495 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
496 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
497 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
498 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
499 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
500 RX1_MARK, SCIFA1_RXD_MARK,
501 CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
502 CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
503 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
504 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
505 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
506 ATAG0_N_MARK, EX_WAIT1_MARK,
507
508 /* IPSR3 */
509 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
510 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
511 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
512 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
513 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
514 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
515 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
516 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
517 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
518 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
519 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
520 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
521 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
522 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
523 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
524 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
525 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
526 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
527
528 /* IPSR4 */
529 SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
530 SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
531 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
532 SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
533 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
534 SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
535 SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
536 SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
537 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
538 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
539 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
540 SSI_SCK4_MARK, GLO_SS_D_MARK,
541 SSI_WS4_MARK, GLO_RFON_D_MARK,
542 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
543 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
544 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
545
546 /* IPSR5 */
547 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
548 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
549 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
550 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
551 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
552 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
553 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
554 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
555 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
556 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
557 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
558 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
559 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
560 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
561 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
562
563 /* IPSR6 */
564 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
565 SCIF_CLK_MARK, BPFCLK_E_MARK,
566 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
567 SCIFA2_RXD_MARK, FMIN_E_MARK,
568 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
569 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
570 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
571 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
572 IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
573 IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
574 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
575 IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
576 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
577 SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
578 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
579 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
580 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
581 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
582
583 /* IPSR7 */
584 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
585 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
586 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
587 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
588 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
589 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
590 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
591 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
592 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
593 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
594 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
595 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
596 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
597 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
598 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
599 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
600 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
601 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
602
603 /* IPSR8 */
604 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
605 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
606 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
607 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
608 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
609 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
610 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
611 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
612 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
613 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
614 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
615 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
616 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
617 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
618 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
619 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
620 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
621 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
622
623 /* IPSR9 */
624 DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
625 DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
626 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
627 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
628 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
629 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
630 TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
631 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
632 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
633 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
634 CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
635 DU1_DISP_MARK, QPOLA_MARK,
636 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
637 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
638 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
639 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
640 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
641 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
642 VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
643 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
644
645 /* IPSR10 */
646 VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
647 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
648 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
649 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
650 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
651 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
652 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
653 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
654 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
655 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
656 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
657 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
658 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
659 TS_SDATA0_C_MARK, ATACS11_N_MARK,
660 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
661 TS_SCK0_C_MARK, ATAG1_N_MARK,
662 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
663 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
664 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
665
666 /* IPSR11 */
667 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
668 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
669 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
670 SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
671 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
672 TX4_B_MARK, SCIFA4_TXD_B_MARK,
673 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
674 RX4_B_MARK, SCIFA4_RXD_B_MARK,
675 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
676 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
677 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
678 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
679 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
680 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
681 VI1_DATA7_MARK, AVB_MDC_MARK,
682 ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
683 ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
684
685 /* IPSR12 */
686 ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
687 ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
688 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
689 SCL2_D_MARK, MSIOF1_RXD_E_MARK,
690 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
691 SDA2_D_MARK, MSIOF1_SCK_E_MARK,
692 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
693 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
694 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
695 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
696 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
697 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
698 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
699 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
700 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
701 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
702 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
703 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
704
705 /* IPSR13 */
706 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
707 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
708 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
709 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
710 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
711 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
712 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
713 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
714 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
715 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
716 SCIFA5_TXD_B_MARK, TX3_C_MARK,
717 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
718 SCIFA5_RXD_B_MARK, RX3_C_MARK,
719 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
720 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
721 SD1_DATA3_MARK, IERX_B_MARK,
722 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
723
724 /* IPSR14 */
725 SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
726 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
727 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
728 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
729 SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
730 SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
731 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
732 VI1_CLK_C_MARK, VI1_G0_B_MARK,
733 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
734 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
735 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
736 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
737 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
738 VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
739 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
740 VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
741
742 /* IPSR15 */
743 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
744 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
745 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
746 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
747 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
748 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
749 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
750 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
751 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
752 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
753 TCLK1_MARK, VI1_DATA1_C_MARK,
754 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
755 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
756 TCLK2_MARK, VI1_DATA3_C_MARK,
757 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
758 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
759 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
760 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
761
762 /* IPSR16 */
763 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
764 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
765 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
766 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
767 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
768 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
769 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
770 PINMUX_MARK_END,
771};
772
773static const u16 pinmux_data[] = {
774 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
775
776 PINMUX_SINGLE(EX_CS0_N),
777 PINMUX_SINGLE(RD_N),
778 PINMUX_SINGLE(AUDIO_CLKA),
779 PINMUX_SINGLE(VI0_CLK),
780 PINMUX_SINGLE(VI0_DATA0_VI0_B0),
781 PINMUX_SINGLE(VI0_DATA1_VI0_B1),
782 PINMUX_SINGLE(VI0_DATA2_VI0_B2),
783 PINMUX_SINGLE(VI0_DATA4_VI0_B4),
784 PINMUX_SINGLE(VI0_DATA5_VI0_B5),
785 PINMUX_SINGLE(VI0_DATA6_VI0_B6),
786 PINMUX_SINGLE(VI0_DATA7_VI0_B7),
787 PINMUX_SINGLE(USB0_PWEN),
788 PINMUX_SINGLE(USB0_OVC),
789 PINMUX_SINGLE(USB1_PWEN),
790 PINMUX_SINGLE(USB1_OVC),
791 PINMUX_SINGLE(DU0_DOTCLKIN),
792 PINMUX_SINGLE(SD1_CLK),
793
794 /* IPSR0 */
795 PINMUX_IPSR_DATA(IP0_0, D0),
796 PINMUX_IPSR_DATA(IP0_1, D1),
797 PINMUX_IPSR_DATA(IP0_2, D2),
798 PINMUX_IPSR_DATA(IP0_3, D3),
799 PINMUX_IPSR_DATA(IP0_4, D4),
800 PINMUX_IPSR_DATA(IP0_5, D5),
801 PINMUX_IPSR_DATA(IP0_6, D6),
802 PINMUX_IPSR_DATA(IP0_7, D7),
803 PINMUX_IPSR_DATA(IP0_8, D8),
804 PINMUX_IPSR_DATA(IP0_9, D9),
805 PINMUX_IPSR_DATA(IP0_10, D10),
806 PINMUX_IPSR_DATA(IP0_11, D11),
807 PINMUX_IPSR_DATA(IP0_12, D12),
808 PINMUX_IPSR_DATA(IP0_13, D13),
809 PINMUX_IPSR_DATA(IP0_14, D14),
810 PINMUX_IPSR_DATA(IP0_15, D15),
811 PINMUX_IPSR_DATA(IP0_18_16, A0),
812 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
813 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
814 PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2),
815 PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
816 PINMUX_IPSR_DATA(IP0_20_19, A1),
817 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
818 PINMUX_IPSR_DATA(IP0_22_21, A2),
819 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
820 PINMUX_IPSR_DATA(IP0_24_23, A3),
821 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
822 PINMUX_IPSR_DATA(IP0_26_25, A4),
823 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
824 PINMUX_IPSR_DATA(IP0_28_27, A5),
825 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
826 PINMUX_IPSR_DATA(IP0_30_29, A6),
827 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
828
829 /* IPSR1 */
830 PINMUX_IPSR_DATA(IP1_1_0, A7),
831 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
832 PINMUX_IPSR_DATA(IP1_3_2, A8),
833 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
834 PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0),
835 PINMUX_IPSR_DATA(IP1_5_4, A9),
836 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
837 PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0),
838 PINMUX_IPSR_DATA(IP1_7_6, A10),
839 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
840 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
841 PINMUX_IPSR_DATA(IP1_10_8, A11),
842 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
843 PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3),
844 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
845 PINMUX_IPSR_DATA(IP1_13_11, A12),
846 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
847 PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3),
848 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
849 PINMUX_IPSR_DATA(IP1_16_14, A13),
850 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
851 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
852 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
853 PINMUX_IPSR_DATA(IP1_19_17, A14),
854 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
855 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
856 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
857 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
858 PINMUX_IPSR_DATA(IP1_22_20, A15),
859 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
860 PINMUX_IPSR_DATA(IP1_25_23, A16),
861 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
862 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
863 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
864 PINMUX_IPSR_DATA(IP1_28_26, A17),
865 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
866 PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2),
867 PINMUX_IPSR_DATA(IP1_31_29, A18),
868 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
869 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
870 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
871
872 /* IPSR2 */
873 PINMUX_IPSR_DATA(IP2_2_0, A19),
874 PINMUX_IPSR_DATA(IP2_2_0, DACK1),
875 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
876 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
877 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
878 PINMUX_IPSR_DATA(IP2_2_0, A20),
879 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
880 PINMUX_IPSR_DATA(IP2_6_5, A21),
881 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
882 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
883 PINMUX_IPSR_DATA(IP2_9_7, A22),
884 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
885 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
886 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
887 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
888 PINMUX_IPSR_DATA(IP2_12_10, A23),
889 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
890 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
891 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
892 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
893 PINMUX_IPSR_DATA(IP2_15_13, A24),
894 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
895 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
896 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
897 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
898 PINMUX_IPSR_DATA(IP2_18_16, A25),
899 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
900 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
901 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
902 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
903 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
904 PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
905 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
906 PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0),
907 PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
908 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
909 PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0),
910 PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
911 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
912 PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
913 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
914 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
915 PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
916 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
917 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
918 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
919 PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
920
921 /* IPSR3 */
922 PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
923 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
924 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
925 PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
926 PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
927 PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
928 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
929 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
930 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
931 PINMUX_IPSR_DATA(IP3_5_3, PWM1),
932 PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
933 PINMUX_IPSR_DATA(IP3_8_6, BS_N),
934 PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
935 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
936 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
937 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
938 PINMUX_IPSR_DATA(IP3_8_6, PWM2),
939 PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
940 PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
941 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
942 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
943 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
944 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
945 PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
946 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
947 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
948 PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
949 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
950 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
951 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
952 PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
953 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
954 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
955 PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
956 PINMUX_IPSR_DATA(IP3_19_18, PWM3),
957 PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
958 PINMUX_IPSR_DATA(IP3_21_20, DACK0),
959 PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
960 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
961 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
962 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
963 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
964 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
965 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
966 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
967 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
968 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
969 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
970 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
971 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
972 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
973 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
974 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
975 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
976 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
977 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
978
979 /* IPSR4 */
980 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
981 PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1),
982 PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1),
983 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
984 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
985 PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1),
986 PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1),
987 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
988 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
989 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
990 PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1),
991 PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1),
992 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
993 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
994 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
995 PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1),
996 PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1),
997 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
998 PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
999 PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
1000 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1001 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1002 PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1003 PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
1004 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1005 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1006 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1007 PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1008 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1009 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1010 PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1011 PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1012 PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1013 PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1014 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1015 PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1016 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1017 PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1018 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1019 PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1020 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1021 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1022 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1023 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1024 PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1025
1026 /* IPSR5 */
1027 PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1028 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1029 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1030 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1031 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1032 PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1033 PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1034 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1035 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1036 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1037 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1038 PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1039 PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1040 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1041 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1042 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1043 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1044 PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1045 PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1046 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1047 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1048 PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1049 PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1050 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1051 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1052 PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1053 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1054 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1055 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1056 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1057 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1058 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1059 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1060 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1061 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1062 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1063 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1064 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1065 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1066 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1067 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1068 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1069 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1070 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1071 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1072 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1073 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1074 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1075 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1076
1077 /* IPSR6 */
1078 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1079 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1080 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1081 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1082 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1083 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1084 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1085 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1086 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1087 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1088 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1089 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1090 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1091 PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
1092 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1093 PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1094 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1095 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1096 PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1097 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1098 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1099 PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1100 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1101 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1102 PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1103 PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2),
1104 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1105 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1106 PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1107 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1108 PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2),
1109 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1110 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1111 PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1112 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1113 PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4),
1114 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1115 PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1116 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1117 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1118 PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4),
1119 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1120 PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1121 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1122 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1123 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1124 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1125 PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1126 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1127 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1128 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1129 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1130
1131 /* IPSR7 */
1132 PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1133 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1134 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1135 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1136 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1137 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1138 PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1139 PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1140 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1141 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1142 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1143 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1144 PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1145 PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1146 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1147 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1148 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1149 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1150 PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1151 PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1152 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1153 PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1154 PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1155 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1156 PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1157 PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1158 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1159 PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1160 PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1161 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1162 PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1163 PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1164 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1165 PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1166 PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1167 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1168 PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1169 PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1170 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1171 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1172 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1173 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1174 PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1175 PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1176 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1177 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1178 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1179 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1180 PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1181 PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1182 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1183 PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1184 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1185 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1186
1187 /* IPSR8 */
1188 PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1189 PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1190 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1191 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1192 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1193 PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1194 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1195 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1196 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1197 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1198 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1199 PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1200 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1201 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1202 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1203 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1204 PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1205 PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1206 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1207 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1208 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1209 PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1210 PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1211 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1212 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1213 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1214 PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1215 PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1216 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1217 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1218 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1219 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1220 PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1221 PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1222 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1223 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1224 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1225 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1226 PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1227 PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1228 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1229 PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1230 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1231 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1232 PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1233 PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1234 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1235 PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1236 PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1237 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1238 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1239 PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1240 PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1241 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1242 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1243 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1244
1245 /* IPSR9 */
1246 PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1247 PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1248 PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2),
1249 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1250 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1251 PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1252 PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1253 PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2),
1254 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1255 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1256 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1257 PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1258 PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1259 PINMUX_IPSR_DATA(IP9_7, QCLK),
1260 PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1261 PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1262 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1263 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1264 PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1),
1265 PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1266 PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1267 PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1268 PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1269 PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1270 PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1271 PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1272 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1273 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1274 PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1),
1275 PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1276 PINMUX_IPSR_DATA(IP9_16, QPOLA),
1277 PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1278 PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1279 PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1280 PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1281 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1282 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1283 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1284 PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1285 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1286 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1287 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1288 PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1289 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1290 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1291 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1292 PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1293 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1294 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1295 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1296 PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1297 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1298 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1299 PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1300 PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0),
1301 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1302 PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0),
1303 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1304 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1305 PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1306
1307 /* IPSR10 */
1308 PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1309 PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0),
1310 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1311 PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0),
1312 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1313 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1314 PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1315 PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1316 PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1317 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1318 PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1),
1319 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1321 PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1322 PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1323 PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1324 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1325 PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1),
1326 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1328 PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1329 PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1330 PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1331 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1332 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1334 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1335 PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1336 PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1337 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1338 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1339 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1340 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1341 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1342 PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1343 PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1344 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1345 PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1346 PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1347 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1348 PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1349 PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1350 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1351 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1352 PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1353 PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1354 PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1355 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1356 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1357 PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1358 PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1359 PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1360 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1361 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1362 PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1363 PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1364 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1365 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1366 PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1367 PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1368 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1369 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1370 PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3),
1371
1372 /* IPSR11 */
1373 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1374 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1375 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1376 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1377 PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3),
1378 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1379 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1380 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1381 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1382 PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1),
1383 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1384 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1385 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1386 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1387 PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1),
1388 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1389 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1390 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1391 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1392 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1393 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1394 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1395 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1396 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1397 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1398 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1399 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1400 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1401 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1402 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1403 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1404 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1405 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1407 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1408 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1409 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1410 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1411 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1412 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1413 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1414 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1415 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1416 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1417 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1418 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1419 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1420 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1421 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1422 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1423 PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1424 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1425 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1426 PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2),
1427 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1428 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1429 PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2),
1430
1431 /* IPSR12 */
1432 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1433 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1434 PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0),
1435 PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0),
1436 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1437 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1438 PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0),
1439 PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0),
1440 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1441 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1442 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1443 PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3),
1444 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1445 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1446 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1447 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1448 PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3),
1449 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1450 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1451 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1452 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1453 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1454 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1455 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1456 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1457 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1458 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1459 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1460 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1461 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1462 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1463 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1464 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1465 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1466 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1467 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1468 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1469 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1470 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1471 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1472 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1473 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1474 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1475 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1476 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1477 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1478 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1479 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1480 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1481 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1482 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1483
1484 /* IPSR13 */
1485 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1486 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1487 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1488 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1489 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1490 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1491 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1492 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1493 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1494 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1495 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1496 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1497 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1498 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1499 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1500 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1501 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1502 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1503 PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1504 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1505 PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1506 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1507 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1508 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1509 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1510 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1511 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1512 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1513 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1514 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1515 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1516 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1517 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1518 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1519 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1520 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1521 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1522 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1523 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1524 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1525 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1526 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1527 PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1528 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1529 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1530 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1531 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1532 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1533 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1534 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1535 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1536 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1537 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1538 PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1539 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1540 PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2),
1541
1542 /* IPSR14 */
1543 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1544 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1545 PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2),
1546 PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1547 PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1548 PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1549 PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1550 PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1551 PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1552 PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1553 PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1554 PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1555 PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1556 PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1557 PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1558 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1559 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1560 PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2),
1561 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1562 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1563 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1564 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1565 PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2),
1566 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1567 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1568 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1569 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1570 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1571 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1572 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1573 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1574 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1575 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1576 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1577 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1578 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1579 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1580 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1581 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1582 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1583 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1584 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1585 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1586 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1587 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1588 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1589 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1590 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1591 PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2),
1592 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1593 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1594 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1595 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1596 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1597 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1598 PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2),
1599 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1600
1601 /* IPSR15 */
1602 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1603 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1604 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1605 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1606 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1607 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1608 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1609 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1610 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1611 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1612 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1613 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1614 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1615 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1616 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1617 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1618 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1619 PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1620 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1621 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1622 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1623 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1624 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1625 PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1626 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1627 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1628 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1629 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1630 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1631 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1632 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1633 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1634 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1635 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1636 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1637 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1638 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1639 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1640 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1641 PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1642 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1643 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1644 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1645 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1646 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1647 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1648 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1649 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1650 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1651 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1652 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1653
1654 /* IPSR16 */
1655 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1656 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1657 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1658 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1659 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1660 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1661 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1662 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1663 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1664 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1665 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1666 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1667 PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK),
1668 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1669 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1670 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1671 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1672 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1673 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1674 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1675 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1676 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1677};
1678
1679static const struct sh_pfc_pin pinmux_pins[] = {
1680 PINMUX_GPIO_GP_ALL(),
1681};
1682
1683/* - Audio Clock ------------------------------------------------------------ */
1684static const unsigned int audio_clk_a_pins[] = {
1685 /* CLK */
1686 RCAR_GP_PIN(2, 28),
1687};
1688
1689static const unsigned int audio_clk_a_mux[] = {
1690 AUDIO_CLKA_MARK,
1691};
1692
1693static const unsigned int audio_clk_b_pins[] = {
1694 /* CLK */
1695 RCAR_GP_PIN(2, 29),
1696};
1697
1698static const unsigned int audio_clk_b_mux[] = {
1699 AUDIO_CLKB_MARK,
1700};
1701
1702static const unsigned int audio_clk_b_b_pins[] = {
1703 /* CLK */
1704 RCAR_GP_PIN(7, 20),
1705};
1706
1707static const unsigned int audio_clk_b_b_mux[] = {
1708 AUDIO_CLKB_B_MARK,
1709};
1710
1711static const unsigned int audio_clk_c_pins[] = {
1712 /* CLK */
1713 RCAR_GP_PIN(2, 30),
1714};
1715
1716static const unsigned int audio_clk_c_mux[] = {
1717 AUDIO_CLKC_MARK,
1718};
1719
1720static const unsigned int audio_clkout_pins[] = {
1721 /* CLK */
1722 RCAR_GP_PIN(2, 31),
1723};
1724
1725static const unsigned int audio_clkout_mux[] = {
1726 AUDIO_CLKOUT_MARK,
1727};
1728
1729/* - AVB -------------------------------------------------------------------- */
1730static const unsigned int avb_link_pins[] = {
1731 RCAR_GP_PIN(5, 14),
1732};
1733static const unsigned int avb_link_mux[] = {
1734 AVB_LINK_MARK,
1735};
1736static const unsigned int avb_magic_pins[] = {
1737 RCAR_GP_PIN(5, 11),
1738};
1739static const unsigned int avb_magic_mux[] = {
1740 AVB_MAGIC_MARK,
1741};
1742static const unsigned int avb_phy_int_pins[] = {
1743 RCAR_GP_PIN(5, 16),
1744};
1745static const unsigned int avb_phy_int_mux[] = {
1746 AVB_PHY_INT_MARK,
1747};
1748static const unsigned int avb_mdio_pins[] = {
1749 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1750};
1751static const unsigned int avb_mdio_mux[] = {
1752 AVB_MDC_MARK, AVB_MDIO_MARK,
1753};
1754static const unsigned int avb_mii_pins[] = {
1755 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1756 RCAR_GP_PIN(5, 21),
1757
1758 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1759 RCAR_GP_PIN(5, 3),
1760
1761 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1762 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1763 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1764};
1765static const unsigned int avb_mii_mux[] = {
1766 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1767 AVB_TXD3_MARK,
1768
1769 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1770 AVB_RXD3_MARK,
1771
1772 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1773 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1774 AVB_TX_CLK_MARK, AVB_COL_MARK,
1775};
1776static const unsigned int avb_gmii_pins[] = {
1777 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1778 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1779 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1780
1781 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1782 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1783 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1784
1785 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1786 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1787 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1788 RCAR_GP_PIN(5, 29),
1789};
1790static const unsigned int avb_gmii_mux[] = {
1791 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1792 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1793 AVB_TXD6_MARK, AVB_TXD7_MARK,
1794
1795 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1796 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1797 AVB_RXD6_MARK, AVB_RXD7_MARK,
1798
1799 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1800 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1801 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1802 AVB_COL_MARK,
1803};
1804
1805/* - CAN -------------------------------------------------------------------- */
1806
1807static const unsigned int can0_data_pins[] = {
1808 /* TX, RX */
1809 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1810};
1811
1812static const unsigned int can0_data_mux[] = {
1813 CAN0_TX_MARK, CAN0_RX_MARK,
1814};
1815
1816static const unsigned int can0_data_b_pins[] = {
1817 /* TX, RX */
1818 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1819};
1820
1821static const unsigned int can0_data_b_mux[] = {
1822 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1823};
1824
1825static const unsigned int can0_data_c_pins[] = {
1826 /* TX, RX */
1827 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1828};
1829
1830static const unsigned int can0_data_c_mux[] = {
1831 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1832};
1833
1834static const unsigned int can0_data_d_pins[] = {
1835 /* TX, RX */
1836 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1837};
1838
1839static const unsigned int can0_data_d_mux[] = {
1840 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1841};
1842
1843static const unsigned int can0_data_e_pins[] = {
1844 /* TX, RX */
1845 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1846};
1847
1848static const unsigned int can0_data_e_mux[] = {
1849 CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1850};
1851
1852static const unsigned int can0_data_f_pins[] = {
1853 /* TX, RX */
1854 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1855};
1856
1857static const unsigned int can0_data_f_mux[] = {
1858 CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1859};
1860
1861static const unsigned int can1_data_pins[] = {
1862 /* TX, RX */
1863 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1864};
1865
1866static const unsigned int can1_data_mux[] = {
1867 CAN1_TX_MARK, CAN1_RX_MARK,
1868};
1869
1870static const unsigned int can1_data_b_pins[] = {
1871 /* TX, RX */
1872 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1873};
1874
1875static const unsigned int can1_data_b_mux[] = {
1876 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1877};
1878
1879static const unsigned int can1_data_c_pins[] = {
1880 /* TX, RX */
1881 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1882};
1883
1884static const unsigned int can1_data_c_mux[] = {
1885 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1886};
1887
1888static const unsigned int can1_data_d_pins[] = {
1889 /* TX, RX */
1890 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1891};
1892
1893static const unsigned int can1_data_d_mux[] = {
1894 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1895};
1896
1897static const unsigned int can_clk_pins[] = {
1898 /* CLK */
1899 RCAR_GP_PIN(7, 2),
1900};
1901
1902static const unsigned int can_clk_mux[] = {
1903 CAN_CLK_MARK,
1904};
1905
1906static const unsigned int can_clk_b_pins[] = {
1907 /* CLK */
1908 RCAR_GP_PIN(5, 21),
1909};
1910
1911static const unsigned int can_clk_b_mux[] = {
1912 CAN_CLK_B_MARK,
1913};
1914
1915static const unsigned int can_clk_c_pins[] = {
1916 /* CLK */
1917 RCAR_GP_PIN(4, 30),
1918};
1919
1920static const unsigned int can_clk_c_mux[] = {
1921 CAN_CLK_C_MARK,
1922};
1923
1924static const unsigned int can_clk_d_pins[] = {
1925 /* CLK */
1926 RCAR_GP_PIN(7, 19),
1927};
1928
1929static const unsigned int can_clk_d_mux[] = {
1930 CAN_CLK_D_MARK,
1931};
1932
1933/* - DU --------------------------------------------------------------------- */
1934static const unsigned int du_rgb666_pins[] = {
1935 /* R[7:2], G[7:2], B[7:2] */
1936 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1937 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1938 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1939 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1940 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1941 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1942};
1943static const unsigned int du_rgb666_mux[] = {
1944 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1945 DU1_DR3_MARK, DU1_DR2_MARK,
1946 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1947 DU1_DG3_MARK, DU1_DG2_MARK,
1948 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1949 DU1_DB3_MARK, DU1_DB2_MARK,
1950};
1951static const unsigned int du_rgb888_pins[] = {
1952 /* R[7:0], G[7:0], B[7:0] */
1953 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1954 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1955 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1956 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1957 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1958 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1959 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1960 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1961 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1962};
1963static const unsigned int du_rgb888_mux[] = {
1964 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1965 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1966 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1967 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1968 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1969 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1970};
1971static const unsigned int du_clk_out_0_pins[] = {
1972 /* CLKOUT */
1973 RCAR_GP_PIN(3, 25),
1974};
1975static const unsigned int du_clk_out_0_mux[] = {
1976 DU1_DOTCLKOUT0_MARK
1977};
1978static const unsigned int du_clk_out_1_pins[] = {
1979 /* CLKOUT */
1980 RCAR_GP_PIN(3, 26),
1981};
1982static const unsigned int du_clk_out_1_mux[] = {
1983 DU1_DOTCLKOUT1_MARK
1984};
1985static const unsigned int du_sync_pins[] = {
1986 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1987 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1988};
1989static const unsigned int du_sync_mux[] = {
1990 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1991};
1992static const unsigned int du_oddf_pins[] = {
1993 /* EXDISP/EXODDF/EXCDE */
1994 RCAR_GP_PIN(3, 29),
1995};
1996static const unsigned int du_oddf_mux[] = {
1997 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1998};
1999static const unsigned int du_cde_pins[] = {
2000 /* CDE */
2001 RCAR_GP_PIN(3, 31),
2002};
2003static const unsigned int du_cde_mux[] = {
2004 DU1_CDE_MARK,
2005};
2006static const unsigned int du_disp_pins[] = {
2007 /* DISP */
2008 RCAR_GP_PIN(3, 30),
2009};
2010static const unsigned int du_disp_mux[] = {
2011 DU1_DISP_MARK,
2012};
2013static const unsigned int du0_clk_in_pins[] = {
2014 /* CLKIN */
2015 RCAR_GP_PIN(6, 31),
2016};
2017static const unsigned int du0_clk_in_mux[] = {
2018 DU0_DOTCLKIN_MARK
2019};
2020static const unsigned int du1_clk_in_pins[] = {
2021 /* CLKIN */
2022 RCAR_GP_PIN(3, 24),
2023};
2024static const unsigned int du1_clk_in_mux[] = {
2025 DU1_DOTCLKIN_MARK
2026};
2027static const unsigned int du1_clk_in_b_pins[] = {
2028 /* CLKIN */
2029 RCAR_GP_PIN(7, 19),
2030};
2031static const unsigned int du1_clk_in_b_mux[] = {
2032 DU1_DOTCLKIN_B_MARK,
2033};
2034static const unsigned int du1_clk_in_c_pins[] = {
2035 /* CLKIN */
2036 RCAR_GP_PIN(7, 20),
2037};
2038static const unsigned int du1_clk_in_c_mux[] = {
2039 DU1_DOTCLKIN_C_MARK,
2040};
2041/* - ETH -------------------------------------------------------------------- */
2042static const unsigned int eth_link_pins[] = {
2043 /* LINK */
2044 RCAR_GP_PIN(5, 18),
2045};
2046static const unsigned int eth_link_mux[] = {
2047 ETH_LINK_MARK,
2048};
2049static const unsigned int eth_magic_pins[] = {
2050 /* MAGIC */
2051 RCAR_GP_PIN(5, 22),
2052};
2053static const unsigned int eth_magic_mux[] = {
2054 ETH_MAGIC_MARK,
2055};
2056static const unsigned int eth_mdio_pins[] = {
2057 /* MDC, MDIO */
2058 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2059};
2060static const unsigned int eth_mdio_mux[] = {
2061 ETH_MDC_MARK, ETH_MDIO_MARK,
2062};
2063static const unsigned int eth_rmii_pins[] = {
2064 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2065 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2066 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2067 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2068};
2069static const unsigned int eth_rmii_mux[] = {
2070 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2071 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2072};
2073
2074/* - HSCIF0 ----------------------------------------------------------------- */
2075static const unsigned int hscif0_data_pins[] = {
2076 /* RX, TX */
2077 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2078};
2079static const unsigned int hscif0_data_mux[] = {
2080 HRX0_MARK, HTX0_MARK,
2081};
2082static const unsigned int hscif0_clk_pins[] = {
2083 /* SCK */
2084 RCAR_GP_PIN(7, 2),
2085};
2086static const unsigned int hscif0_clk_mux[] = {
2087 HSCK0_MARK,
2088};
2089static const unsigned int hscif0_ctrl_pins[] = {
2090 /* RTS, CTS */
2091 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2092};
2093static const unsigned int hscif0_ctrl_mux[] = {
2094 HRTS0_N_MARK, HCTS0_N_MARK,
2095};
2096static const unsigned int hscif0_data_b_pins[] = {
2097 /* RX, TX */
2098 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2099};
2100static const unsigned int hscif0_data_b_mux[] = {
2101 HRX0_B_MARK, HTX0_B_MARK,
2102};
2103static const unsigned int hscif0_ctrl_b_pins[] = {
2104 /* RTS, CTS */
2105 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2106};
2107static const unsigned int hscif0_ctrl_b_mux[] = {
2108 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2109};
2110static const unsigned int hscif0_data_c_pins[] = {
2111 /* RX, TX */
2112 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2113};
2114static const unsigned int hscif0_data_c_mux[] = {
2115 HRX0_C_MARK, HTX0_C_MARK,
2116};
2117static const unsigned int hscif0_clk_c_pins[] = {
2118 /* SCK */
2119 RCAR_GP_PIN(5, 31),
2120};
2121static const unsigned int hscif0_clk_c_mux[] = {
2122 HSCK0_C_MARK,
2123};
2124/* - HSCIF1 ----------------------------------------------------------------- */
2125static const unsigned int hscif1_data_pins[] = {
2126 /* RX, TX */
2127 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2128};
2129static const unsigned int hscif1_data_mux[] = {
2130 HRX1_MARK, HTX1_MARK,
2131};
2132static const unsigned int hscif1_clk_pins[] = {
2133 /* SCK */
2134 RCAR_GP_PIN(7, 7),
2135};
2136static const unsigned int hscif1_clk_mux[] = {
2137 HSCK1_MARK,
2138};
2139static const unsigned int hscif1_ctrl_pins[] = {
2140 /* RTS, CTS */
2141 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2142};
2143static const unsigned int hscif1_ctrl_mux[] = {
2144 HRTS1_N_MARK, HCTS1_N_MARK,
2145};
2146static const unsigned int hscif1_data_b_pins[] = {
2147 /* RX, TX */
2148 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2149};
2150static const unsigned int hscif1_data_b_mux[] = {
2151 HRX1_B_MARK, HTX1_B_MARK,
2152};
2153static const unsigned int hscif1_data_c_pins[] = {
2154 /* RX, TX */
2155 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2156};
2157static const unsigned int hscif1_data_c_mux[] = {
2158 HRX1_C_MARK, HTX1_C_MARK,
2159};
2160static const unsigned int hscif1_clk_c_pins[] = {
2161 /* SCK */
2162 RCAR_GP_PIN(7, 16),
2163};
2164static const unsigned int hscif1_clk_c_mux[] = {
2165 HSCK1_C_MARK,
2166};
2167static const unsigned int hscif1_ctrl_c_pins[] = {
2168 /* RTS, CTS */
2169 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2170};
2171static const unsigned int hscif1_ctrl_c_mux[] = {
2172 HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2173};
2174static const unsigned int hscif1_data_d_pins[] = {
2175 /* RX, TX */
2176 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2177};
2178static const unsigned int hscif1_data_d_mux[] = {
2179 HRX1_D_MARK, HTX1_D_MARK,
2180};
2181static const unsigned int hscif1_data_e_pins[] = {
2182 /* RX, TX */
2183 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2184};
2185static const unsigned int hscif1_data_e_mux[] = {
2186 HRX1_C_MARK, HTX1_C_MARK,
2187};
2188static const unsigned int hscif1_clk_e_pins[] = {
2189 /* SCK */
2190 RCAR_GP_PIN(2, 6),
2191};
2192static const unsigned int hscif1_clk_e_mux[] = {
2193 HSCK1_E_MARK,
2194};
2195static const unsigned int hscif1_ctrl_e_pins[] = {
2196 /* RTS, CTS */
2197 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2198};
2199static const unsigned int hscif1_ctrl_e_mux[] = {
2200 HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2201};
2202/* - HSCIF2 ----------------------------------------------------------------- */
2203static const unsigned int hscif2_data_pins[] = {
2204 /* RX, TX */
2205 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2206};
2207static const unsigned int hscif2_data_mux[] = {
2208 HRX2_MARK, HTX2_MARK,
2209};
2210static const unsigned int hscif2_clk_pins[] = {
2211 /* SCK */
2212 RCAR_GP_PIN(4, 15),
2213};
2214static const unsigned int hscif2_clk_mux[] = {
2215 HSCK2_MARK,
2216};
2217static const unsigned int hscif2_ctrl_pins[] = {
2218 /* RTS, CTS */
2219 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2220};
2221static const unsigned int hscif2_ctrl_mux[] = {
2222 HRTS2_N_MARK, HCTS2_N_MARK,
2223};
2224static const unsigned int hscif2_data_b_pins[] = {
2225 /* RX, TX */
2226 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2227};
2228static const unsigned int hscif2_data_b_mux[] = {
2229 HRX2_B_MARK, HTX2_B_MARK,
2230};
2231static const unsigned int hscif2_ctrl_b_pins[] = {
2232 /* RTS, CTS */
2233 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2234};
2235static const unsigned int hscif2_ctrl_b_mux[] = {
2236 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2237};
2238static const unsigned int hscif2_data_c_pins[] = {
2239 /* RX, TX */
2240 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2241};
2242static const unsigned int hscif2_data_c_mux[] = {
2243 HRX2_C_MARK, HTX2_C_MARK,
2244};
2245static const unsigned int hscif2_clk_c_pins[] = {
2246 /* SCK */
2247 RCAR_GP_PIN(5, 31),
2248};
2249static const unsigned int hscif2_clk_c_mux[] = {
2250 HSCK2_C_MARK,
2251};
2252static const unsigned int hscif2_data_d_pins[] = {
2253 /* RX, TX */
2254 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2255};
2256static const unsigned int hscif2_data_d_mux[] = {
2257 HRX2_B_MARK, HTX2_D_MARK,
2258};
2259/* - I2C0 ------------------------------------------------------------------- */
2260static const unsigned int i2c0_pins[] = {
2261 /* SCL, SDA */
2262 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2263};
2264static const unsigned int i2c0_mux[] = {
2265 SCL0_MARK, SDA0_MARK,
2266};
2267static const unsigned int i2c0_b_pins[] = {
2268 /* SCL, SDA */
2269 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2270};
2271static const unsigned int i2c0_b_mux[] = {
2272 SCL0_B_MARK, SDA0_B_MARK,
2273};
2274static const unsigned int i2c0_c_pins[] = {
2275 /* SCL, SDA */
2276 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2277};
2278static const unsigned int i2c0_c_mux[] = {
2279 SCL0_C_MARK, SDA0_C_MARK,
2280};
2281/* - I2C1 ------------------------------------------------------------------- */
2282static const unsigned int i2c1_pins[] = {
2283 /* SCL, SDA */
2284 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2285};
2286static const unsigned int i2c1_mux[] = {
2287 SCL1_MARK, SDA1_MARK,
2288};
2289static const unsigned int i2c1_b_pins[] = {
2290 /* SCL, SDA */
2291 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2292};
2293static const unsigned int i2c1_b_mux[] = {
2294 SCL1_B_MARK, SDA1_B_MARK,
2295};
2296static const unsigned int i2c1_c_pins[] = {
2297 /* SCL, SDA */
2298 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2299};
2300static const unsigned int i2c1_c_mux[] = {
2301 SCL1_C_MARK, SDA1_C_MARK,
2302};
2303static const unsigned int i2c1_d_pins[] = {
2304 /* SCL, SDA */
2305 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2306};
2307static const unsigned int i2c1_d_mux[] = {
2308 SCL1_D_MARK, SDA1_D_MARK,
2309};
2310static const unsigned int i2c1_e_pins[] = {
2311 /* SCL, SDA */
2312 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2313};
2314static const unsigned int i2c1_e_mux[] = {
2315 SCL1_E_MARK, SDA1_E_MARK,
2316};
2317/* - I2C2 ------------------------------------------------------------------- */
2318static const unsigned int i2c2_pins[] = {
2319 /* SCL, SDA */
2320 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2321};
2322static const unsigned int i2c2_mux[] = {
2323 SCL2_MARK, SDA2_MARK,
2324};
2325static const unsigned int i2c2_b_pins[] = {
2326 /* SCL, SDA */
2327 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2328};
2329static const unsigned int i2c2_b_mux[] = {
2330 SCL2_B_MARK, SDA2_B_MARK,
2331};
2332static const unsigned int i2c2_c_pins[] = {
2333 /* SCL, SDA */
2334 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2335};
2336static const unsigned int i2c2_c_mux[] = {
2337 SCL2_C_MARK, SDA2_C_MARK,
2338};
2339static const unsigned int i2c2_d_pins[] = {
2340 /* SCL, SDA */
2341 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2342};
2343static const unsigned int i2c2_d_mux[] = {
2344 SCL2_D_MARK, SDA2_D_MARK,
2345};
2346/* - I2C3 ------------------------------------------------------------------- */
2347static const unsigned int i2c3_pins[] = {
2348 /* SCL, SDA */
2349 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2350};
2351static const unsigned int i2c3_mux[] = {
2352 SCL3_MARK, SDA3_MARK,
2353};
2354static const unsigned int i2c3_b_pins[] = {
2355 /* SCL, SDA */
2356 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2357};
2358static const unsigned int i2c3_b_mux[] = {
2359 SCL3_B_MARK, SDA3_B_MARK,
2360};
2361static const unsigned int i2c3_c_pins[] = {
2362 /* SCL, SDA */
2363 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2364};
2365static const unsigned int i2c3_c_mux[] = {
2366 SCL3_C_MARK, SDA3_C_MARK,
2367};
2368static const unsigned int i2c3_d_pins[] = {
2369 /* SCL, SDA */
2370 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2371};
2372static const unsigned int i2c3_d_mux[] = {
2373 SCL3_D_MARK, SDA3_D_MARK,
2374};
2375/* - I2C4 ------------------------------------------------------------------- */
2376static const unsigned int i2c4_pins[] = {
2377 /* SCL, SDA */
2378 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2379};
2380static const unsigned int i2c4_mux[] = {
2381 SCL4_MARK, SDA4_MARK,
2382};
2383static const unsigned int i2c4_b_pins[] = {
2384 /* SCL, SDA */
2385 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2386};
2387static const unsigned int i2c4_b_mux[] = {
2388 SCL4_B_MARK, SDA4_B_MARK,
2389};
2390static const unsigned int i2c4_c_pins[] = {
2391 /* SCL, SDA */
2392 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2393};
2394static const unsigned int i2c4_c_mux[] = {
2395 SCL4_C_MARK, SDA4_C_MARK,
2396};
2397/* - I2C7 ------------------------------------------------------------------- */
2398static const unsigned int i2c7_pins[] = {
2399 /* SCL, SDA */
2400 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2401};
2402static const unsigned int i2c7_mux[] = {
2403 SCL7_MARK, SDA7_MARK,
2404};
2405static const unsigned int i2c7_b_pins[] = {
2406 /* SCL, SDA */
2407 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2408};
2409static const unsigned int i2c7_b_mux[] = {
2410 SCL7_B_MARK, SDA7_B_MARK,
2411};
2412static const unsigned int i2c7_c_pins[] = {
2413 /* SCL, SDA */
2414 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2415};
2416static const unsigned int i2c7_c_mux[] = {
2417 SCL7_C_MARK, SDA7_C_MARK,
2418};
2419/* - I2C8 ------------------------------------------------------------------- */
2420static const unsigned int i2c8_pins[] = {
2421 /* SCL, SDA */
2422 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2423};
2424static const unsigned int i2c8_mux[] = {
2425 SCL8_MARK, SDA8_MARK,
2426};
2427static const unsigned int i2c8_b_pins[] = {
2428 /* SCL, SDA */
2429 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2430};
2431static const unsigned int i2c8_b_mux[] = {
2432 SCL8_B_MARK, SDA8_B_MARK,
2433};
2434static const unsigned int i2c8_c_pins[] = {
2435 /* SCL, SDA */
2436 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2437};
2438static const unsigned int i2c8_c_mux[] = {
2439 SCL8_C_MARK, SDA8_C_MARK,
2440};
2441/* - INTC ------------------------------------------------------------------- */
2442static const unsigned int intc_irq0_pins[] = {
2443 /* IRQ */
2444 RCAR_GP_PIN(7, 10),
2445};
2446static const unsigned int intc_irq0_mux[] = {
2447 IRQ0_MARK,
2448};
2449static const unsigned int intc_irq1_pins[] = {
2450 /* IRQ */
2451 RCAR_GP_PIN(7, 11),
2452};
2453static const unsigned int intc_irq1_mux[] = {
2454 IRQ1_MARK,
2455};
2456static const unsigned int intc_irq2_pins[] = {
2457 /* IRQ */
2458 RCAR_GP_PIN(7, 12),
2459};
2460static const unsigned int intc_irq2_mux[] = {
2461 IRQ2_MARK,
2462};
2463static const unsigned int intc_irq3_pins[] = {
2464 /* IRQ */
2465 RCAR_GP_PIN(7, 13),
2466};
2467static const unsigned int intc_irq3_mux[] = {
2468 IRQ3_MARK,
2469};
2470/* - MLB+ ------------------------------------------------------------------- */
2471static const unsigned int mlb_3pin_pins[] = {
2472 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2473};
2474static const unsigned int mlb_3pin_mux[] = {
2475 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2476};
2477/* - MMCIF ------------------------------------------------------------------ */
2478static const unsigned int mmc_data1_pins[] = {
2479 /* D[0] */
2480 RCAR_GP_PIN(6, 18),
2481};
2482static const unsigned int mmc_data1_mux[] = {
2483 MMC_D0_MARK,
2484};
2485static const unsigned int mmc_data4_pins[] = {
2486 /* D[0:3] */
2487 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2488 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2489};
2490static const unsigned int mmc_data4_mux[] = {
2491 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2492};
2493static const unsigned int mmc_data8_pins[] = {
2494 /* D[0:7] */
2495 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2496 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2497 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2498 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2499};
2500static const unsigned int mmc_data8_mux[] = {
2501 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2502 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2503};
2504static const unsigned int mmc_ctrl_pins[] = {
2505 /* CLK, CMD */
2506 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2507};
2508static const unsigned int mmc_ctrl_mux[] = {
2509 MMC_CLK_MARK, MMC_CMD_MARK,
2510};
2511/* - MSIOF0 ----------------------------------------------------------------- */
2512static const unsigned int msiof0_clk_pins[] = {
2513 /* SCK */
2514 RCAR_GP_PIN(6, 24),
2515};
2516static const unsigned int msiof0_clk_mux[] = {
2517 MSIOF0_SCK_MARK,
2518};
2519static const unsigned int msiof0_sync_pins[] = {
2520 /* SYNC */
2521 RCAR_GP_PIN(6, 25),
2522};
2523static const unsigned int msiof0_sync_mux[] = {
2524 MSIOF0_SYNC_MARK,
2525};
2526static const unsigned int msiof0_ss1_pins[] = {
2527 /* SS1 */
2528 RCAR_GP_PIN(6, 28),
2529};
2530static const unsigned int msiof0_ss1_mux[] = {
2531 MSIOF0_SS1_MARK,
2532};
2533static const unsigned int msiof0_ss2_pins[] = {
2534 /* SS2 */
2535 RCAR_GP_PIN(6, 29),
2536};
2537static const unsigned int msiof0_ss2_mux[] = {
2538 MSIOF0_SS2_MARK,
2539};
2540static const unsigned int msiof0_rx_pins[] = {
2541 /* RXD */
2542 RCAR_GP_PIN(6, 27),
2543};
2544static const unsigned int msiof0_rx_mux[] = {
2545 MSIOF0_RXD_MARK,
2546};
2547static const unsigned int msiof0_tx_pins[] = {
2548 /* TXD */
2549 RCAR_GP_PIN(6, 26),
2550};
2551static const unsigned int msiof0_tx_mux[] = {
2552 MSIOF0_TXD_MARK,
2553};
2554
2555static const unsigned int msiof0_clk_b_pins[] = {
2556 /* SCK */
2557 RCAR_GP_PIN(0, 16),
2558};
2559static const unsigned int msiof0_clk_b_mux[] = {
2560 MSIOF0_SCK_B_MARK,
2561};
2562static const unsigned int msiof0_sync_b_pins[] = {
2563 /* SYNC */
2564 RCAR_GP_PIN(0, 17),
2565};
2566static const unsigned int msiof0_sync_b_mux[] = {
2567 MSIOF0_SYNC_B_MARK,
2568};
2569static const unsigned int msiof0_ss1_b_pins[] = {
2570 /* SS1 */
2571 RCAR_GP_PIN(0, 18),
2572};
2573static const unsigned int msiof0_ss1_b_mux[] = {
2574 MSIOF0_SS1_B_MARK,
2575};
2576static const unsigned int msiof0_ss2_b_pins[] = {
2577 /* SS2 */
2578 RCAR_GP_PIN(0, 19),
2579};
2580static const unsigned int msiof0_ss2_b_mux[] = {
2581 MSIOF0_SS2_B_MARK,
2582};
2583static const unsigned int msiof0_rx_b_pins[] = {
2584 /* RXD */
2585 RCAR_GP_PIN(0, 21),
2586};
2587static const unsigned int msiof0_rx_b_mux[] = {
2588 MSIOF0_RXD_B_MARK,
2589};
2590static const unsigned int msiof0_tx_b_pins[] = {
2591 /* TXD */
2592 RCAR_GP_PIN(0, 20),
2593};
2594static const unsigned int msiof0_tx_b_mux[] = {
2595 MSIOF0_TXD_B_MARK,
2596};
2597
2598static const unsigned int msiof0_clk_c_pins[] = {
2599 /* SCK */
2600 RCAR_GP_PIN(5, 26),
2601};
2602static const unsigned int msiof0_clk_c_mux[] = {
2603 MSIOF0_SCK_C_MARK,
2604};
2605static const unsigned int msiof0_sync_c_pins[] = {
2606 /* SYNC */
2607 RCAR_GP_PIN(5, 25),
2608};
2609static const unsigned int msiof0_sync_c_mux[] = {
2610 MSIOF0_SYNC_C_MARK,
2611};
2612static const unsigned int msiof0_ss1_c_pins[] = {
2613 /* SS1 */
2614 RCAR_GP_PIN(5, 27),
2615};
2616static const unsigned int msiof0_ss1_c_mux[] = {
2617 MSIOF0_SS1_C_MARK,
2618};
2619static const unsigned int msiof0_ss2_c_pins[] = {
2620 /* SS2 */
2621 RCAR_GP_PIN(5, 28),
2622};
2623static const unsigned int msiof0_ss2_c_mux[] = {
2624 MSIOF0_SS2_C_MARK,
2625};
2626static const unsigned int msiof0_rx_c_pins[] = {
2627 /* RXD */
2628 RCAR_GP_PIN(5, 29),
2629};
2630static const unsigned int msiof0_rx_c_mux[] = {
2631 MSIOF0_RXD_C_MARK,
2632};
2633static const unsigned int msiof0_tx_c_pins[] = {
2634 /* TXD */
2635 RCAR_GP_PIN(5, 30),
2636};
2637static const unsigned int msiof0_tx_c_mux[] = {
2638 MSIOF0_TXD_C_MARK,
2639};
2640/* - MSIOF1 ----------------------------------------------------------------- */
2641static const unsigned int msiof1_clk_pins[] = {
2642 /* SCK */
2643 RCAR_GP_PIN(0, 22),
2644};
2645static const unsigned int msiof1_clk_mux[] = {
2646 MSIOF1_SCK_MARK,
2647};
2648static const unsigned int msiof1_sync_pins[] = {
2649 /* SYNC */
2650 RCAR_GP_PIN(0, 23),
2651};
2652static const unsigned int msiof1_sync_mux[] = {
2653 MSIOF1_SYNC_MARK,
2654};
2655static const unsigned int msiof1_ss1_pins[] = {
2656 /* SS1 */
2657 RCAR_GP_PIN(0, 24),
2658};
2659static const unsigned int msiof1_ss1_mux[] = {
2660 MSIOF1_SS1_MARK,
2661};
2662static const unsigned int msiof1_ss2_pins[] = {
2663 /* SS2 */
2664 RCAR_GP_PIN(0, 25),
2665};
2666static const unsigned int msiof1_ss2_mux[] = {
2667 MSIOF1_SS2_MARK,
2668};
2669static const unsigned int msiof1_rx_pins[] = {
2670 /* RXD */
2671 RCAR_GP_PIN(0, 27),
2672};
2673static const unsigned int msiof1_rx_mux[] = {
2674 MSIOF1_RXD_MARK,
2675};
2676static const unsigned int msiof1_tx_pins[] = {
2677 /* TXD */
2678 RCAR_GP_PIN(0, 26),
2679};
2680static const unsigned int msiof1_tx_mux[] = {
2681 MSIOF1_TXD_MARK,
2682};
2683
2684static const unsigned int msiof1_clk_b_pins[] = {
2685 /* SCK */
2686 RCAR_GP_PIN(2, 29),
2687};
2688static const unsigned int msiof1_clk_b_mux[] = {
2689 MSIOF1_SCK_B_MARK,
2690};
2691static const unsigned int msiof1_sync_b_pins[] = {
2692 /* SYNC */
2693 RCAR_GP_PIN(2, 30),
2694};
2695static const unsigned int msiof1_sync_b_mux[] = {
2696 MSIOF1_SYNC_B_MARK,
2697};
2698static const unsigned int msiof1_ss1_b_pins[] = {
2699 /* SS1 */
2700 RCAR_GP_PIN(2, 31),
2701};
2702static const unsigned int msiof1_ss1_b_mux[] = {
2703 MSIOF1_SS1_B_MARK,
2704};
2705static const unsigned int msiof1_ss2_b_pins[] = {
2706 /* SS2 */
2707 RCAR_GP_PIN(7, 16),
2708};
2709static const unsigned int msiof1_ss2_b_mux[] = {
2710 MSIOF1_SS2_B_MARK,
2711};
2712static const unsigned int msiof1_rx_b_pins[] = {
2713 /* RXD */
2714 RCAR_GP_PIN(7, 18),
2715};
2716static const unsigned int msiof1_rx_b_mux[] = {
2717 MSIOF1_RXD_B_MARK,
2718};
2719static const unsigned int msiof1_tx_b_pins[] = {
2720 /* TXD */
2721 RCAR_GP_PIN(7, 17),
2722};
2723static const unsigned int msiof1_tx_b_mux[] = {
2724 MSIOF1_TXD_B_MARK,
2725};
2726
2727static const unsigned int msiof1_clk_c_pins[] = {
2728 /* SCK */
2729 RCAR_GP_PIN(2, 15),
2730};
2731static const unsigned int msiof1_clk_c_mux[] = {
2732 MSIOF1_SCK_C_MARK,
2733};
2734static const unsigned int msiof1_sync_c_pins[] = {
2735 /* SYNC */
2736 RCAR_GP_PIN(2, 16),
2737};
2738static const unsigned int msiof1_sync_c_mux[] = {
2739 MSIOF1_SYNC_C_MARK,
2740};
2741static const unsigned int msiof1_rx_c_pins[] = {
2742 /* RXD */
2743 RCAR_GP_PIN(2, 18),
2744};
2745static const unsigned int msiof1_rx_c_mux[] = {
2746 MSIOF1_RXD_C_MARK,
2747};
2748static const unsigned int msiof1_tx_c_pins[] = {
2749 /* TXD */
2750 RCAR_GP_PIN(2, 17),
2751};
2752static const unsigned int msiof1_tx_c_mux[] = {
2753 MSIOF1_TXD_C_MARK,
2754};
2755
2756static const unsigned int msiof1_clk_d_pins[] = {
2757 /* SCK */
2758 RCAR_GP_PIN(0, 28),
2759};
2760static const unsigned int msiof1_clk_d_mux[] = {
2761 MSIOF1_SCK_D_MARK,
2762};
2763static const unsigned int msiof1_sync_d_pins[] = {
2764 /* SYNC */
2765 RCAR_GP_PIN(0, 30),
2766};
2767static const unsigned int msiof1_sync_d_mux[] = {
2768 MSIOF1_SYNC_D_MARK,
2769};
2770static const unsigned int msiof1_ss1_d_pins[] = {
2771 /* SS1 */
2772 RCAR_GP_PIN(0, 29),
2773};
2774static const unsigned int msiof1_ss1_d_mux[] = {
2775 MSIOF1_SS1_D_MARK,
2776};
2777static const unsigned int msiof1_rx_d_pins[] = {
2778 /* RXD */
2779 RCAR_GP_PIN(0, 27),
2780};
2781static const unsigned int msiof1_rx_d_mux[] = {
2782 MSIOF1_RXD_D_MARK,
2783};
2784static const unsigned int msiof1_tx_d_pins[] = {
2785 /* TXD */
2786 RCAR_GP_PIN(0, 26),
2787};
2788static const unsigned int msiof1_tx_d_mux[] = {
2789 MSIOF1_TXD_D_MARK,
2790};
2791
2792static const unsigned int msiof1_clk_e_pins[] = {
2793 /* SCK */
2794 RCAR_GP_PIN(5, 18),
2795};
2796static const unsigned int msiof1_clk_e_mux[] = {
2797 MSIOF1_SCK_E_MARK,
2798};
2799static const unsigned int msiof1_sync_e_pins[] = {
2800 /* SYNC */
2801 RCAR_GP_PIN(5, 19),
2802};
2803static const unsigned int msiof1_sync_e_mux[] = {
2804 MSIOF1_SYNC_E_MARK,
2805};
2806static const unsigned int msiof1_rx_e_pins[] = {
2807 /* RXD */
2808 RCAR_GP_PIN(5, 17),
2809};
2810static const unsigned int msiof1_rx_e_mux[] = {
2811 MSIOF1_RXD_E_MARK,
2812};
2813static const unsigned int msiof1_tx_e_pins[] = {
2814 /* TXD */
2815 RCAR_GP_PIN(5, 20),
2816};
2817static const unsigned int msiof1_tx_e_mux[] = {
2818 MSIOF1_TXD_E_MARK,
2819};
2820/* - MSIOF2 ----------------------------------------------------------------- */
2821static const unsigned int msiof2_clk_pins[] = {
2822 /* SCK */
2823 RCAR_GP_PIN(1, 13),
2824};
2825static const unsigned int msiof2_clk_mux[] = {
2826 MSIOF2_SCK_MARK,
2827};
2828static const unsigned int msiof2_sync_pins[] = {
2829 /* SYNC */
2830 RCAR_GP_PIN(1, 14),
2831};
2832static const unsigned int msiof2_sync_mux[] = {
2833 MSIOF2_SYNC_MARK,
2834};
2835static const unsigned int msiof2_ss1_pins[] = {
2836 /* SS1 */
2837 RCAR_GP_PIN(1, 17),
2838};
2839static const unsigned int msiof2_ss1_mux[] = {
2840 MSIOF2_SS1_MARK,
2841};
2842static const unsigned int msiof2_ss2_pins[] = {
2843 /* SS2 */
2844 RCAR_GP_PIN(1, 18),
2845};
2846static const unsigned int msiof2_ss2_mux[] = {
2847 MSIOF2_SS2_MARK,
2848};
2849static const unsigned int msiof2_rx_pins[] = {
2850 /* RXD */
2851 RCAR_GP_PIN(1, 16),
2852};
2853static const unsigned int msiof2_rx_mux[] = {
2854 MSIOF2_RXD_MARK,
2855};
2856static const unsigned int msiof2_tx_pins[] = {
2857 /* TXD */
2858 RCAR_GP_PIN(1, 15),
2859};
2860static const unsigned int msiof2_tx_mux[] = {
2861 MSIOF2_TXD_MARK,
2862};
2863
2864static const unsigned int msiof2_clk_b_pins[] = {
2865 /* SCK */
2866 RCAR_GP_PIN(3, 0),
2867};
2868static const unsigned int msiof2_clk_b_mux[] = {
2869 MSIOF2_SCK_B_MARK,
2870};
2871static const unsigned int msiof2_sync_b_pins[] = {
2872 /* SYNC */
2873 RCAR_GP_PIN(3, 1),
2874};
2875static const unsigned int msiof2_sync_b_mux[] = {
2876 MSIOF2_SYNC_B_MARK,
2877};
2878static const unsigned int msiof2_ss1_b_pins[] = {
2879 /* SS1 */
2880 RCAR_GP_PIN(3, 8),
2881};
2882static const unsigned int msiof2_ss1_b_mux[] = {
2883 MSIOF2_SS1_B_MARK,
2884};
2885static const unsigned int msiof2_ss2_b_pins[] = {
2886 /* SS2 */
2887 RCAR_GP_PIN(3, 9),
2888};
2889static const unsigned int msiof2_ss2_b_mux[] = {
2890 MSIOF2_SS2_B_MARK,
2891};
2892static const unsigned int msiof2_rx_b_pins[] = {
2893 /* RXD */
2894 RCAR_GP_PIN(3, 17),
2895};
2896static const unsigned int msiof2_rx_b_mux[] = {
2897 MSIOF2_RXD_B_MARK,
2898};
2899static const unsigned int msiof2_tx_b_pins[] = {
2900 /* TXD */
2901 RCAR_GP_PIN(3, 16),
2902};
2903static const unsigned int msiof2_tx_b_mux[] = {
2904 MSIOF2_TXD_B_MARK,
2905};
2906
2907static const unsigned int msiof2_clk_c_pins[] = {
2908 /* SCK */
2909 RCAR_GP_PIN(2, 2),
2910};
2911static const unsigned int msiof2_clk_c_mux[] = {
2912 MSIOF2_SCK_C_MARK,
2913};
2914static const unsigned int msiof2_sync_c_pins[] = {
2915 /* SYNC */
2916 RCAR_GP_PIN(2, 3),
2917};
2918static const unsigned int msiof2_sync_c_mux[] = {
2919 MSIOF2_SYNC_C_MARK,
2920};
2921static const unsigned int msiof2_rx_c_pins[] = {
2922 /* RXD */
2923 RCAR_GP_PIN(2, 5),
2924};
2925static const unsigned int msiof2_rx_c_mux[] = {
2926 MSIOF2_RXD_C_MARK,
2927};
2928static const unsigned int msiof2_tx_c_pins[] = {
2929 /* TXD */
2930 RCAR_GP_PIN(2, 4),
2931};
2932static const unsigned int msiof2_tx_c_mux[] = {
2933 MSIOF2_TXD_C_MARK,
2934};
2935
2936static const unsigned int msiof2_clk_d_pins[] = {
2937 /* SCK */
2938 RCAR_GP_PIN(2, 14),
2939};
2940static const unsigned int msiof2_clk_d_mux[] = {
2941 MSIOF2_SCK_D_MARK,
2942};
2943static const unsigned int msiof2_sync_d_pins[] = {
2944 /* SYNC */
2945 RCAR_GP_PIN(2, 15),
2946};
2947static const unsigned int msiof2_sync_d_mux[] = {
2948 MSIOF2_SYNC_D_MARK,
2949};
2950static const unsigned int msiof2_ss1_d_pins[] = {
2951 /* SS1 */
2952 RCAR_GP_PIN(2, 17),
2953};
2954static const unsigned int msiof2_ss1_d_mux[] = {
2955 MSIOF2_SS1_D_MARK,
2956};
2957static const unsigned int msiof2_ss2_d_pins[] = {
2958 /* SS2 */
2959 RCAR_GP_PIN(2, 19),
2960};
2961static const unsigned int msiof2_ss2_d_mux[] = {
2962 MSIOF2_SS2_D_MARK,
2963};
2964static const unsigned int msiof2_rx_d_pins[] = {
2965 /* RXD */
2966 RCAR_GP_PIN(2, 18),
2967};
2968static const unsigned int msiof2_rx_d_mux[] = {
2969 MSIOF2_RXD_D_MARK,
2970};
2971static const unsigned int msiof2_tx_d_pins[] = {
2972 /* TXD */
2973 RCAR_GP_PIN(2, 16),
2974};
2975static const unsigned int msiof2_tx_d_mux[] = {
2976 MSIOF2_TXD_D_MARK,
2977};
2978
2979static const unsigned int msiof2_clk_e_pins[] = {
2980 /* SCK */
2981 RCAR_GP_PIN(7, 15),
2982};
2983static const unsigned int msiof2_clk_e_mux[] = {
2984 MSIOF2_SCK_E_MARK,
2985};
2986static const unsigned int msiof2_sync_e_pins[] = {
2987 /* SYNC */
2988 RCAR_GP_PIN(7, 16),
2989};
2990static const unsigned int msiof2_sync_e_mux[] = {
2991 MSIOF2_SYNC_E_MARK,
2992};
2993static const unsigned int msiof2_rx_e_pins[] = {
2994 /* RXD */
2995 RCAR_GP_PIN(7, 14),
2996};
2997static const unsigned int msiof2_rx_e_mux[] = {
2998 MSIOF2_RXD_E_MARK,
2999};
3000static const unsigned int msiof2_tx_e_pins[] = {
3001 /* TXD */
3002 RCAR_GP_PIN(7, 13),
3003};
3004static const unsigned int msiof2_tx_e_mux[] = {
3005 MSIOF2_TXD_E_MARK,
3006};
3007/* - PWM -------------------------------------------------------------------- */
3008static const unsigned int pwm0_pins[] = {
3009 RCAR_GP_PIN(6, 14),
3010};
3011static const unsigned int pwm0_mux[] = {
3012 PWM0_MARK,
3013};
3014static const unsigned int pwm0_b_pins[] = {
3015 RCAR_GP_PIN(5, 30),
3016};
3017static const unsigned int pwm0_b_mux[] = {
3018 PWM0_B_MARK,
3019};
3020static const unsigned int pwm1_pins[] = {
3021 RCAR_GP_PIN(1, 17),
3022};
3023static const unsigned int pwm1_mux[] = {
3024 PWM1_MARK,
3025};
3026static const unsigned int pwm1_b_pins[] = {
3027 RCAR_GP_PIN(6, 15),
3028};
3029static const unsigned int pwm1_b_mux[] = {
3030 PWM1_B_MARK,
3031};
3032static const unsigned int pwm2_pins[] = {
3033 RCAR_GP_PIN(1, 18),
3034};
3035static const unsigned int pwm2_mux[] = {
3036 PWM2_MARK,
3037};
3038static const unsigned int pwm2_b_pins[] = {
3039 RCAR_GP_PIN(0, 16),
3040};
3041static const unsigned int pwm2_b_mux[] = {
3042 PWM2_B_MARK,
3043};
3044static const unsigned int pwm3_pins[] = {
3045 RCAR_GP_PIN(1, 24),
3046};
3047static const unsigned int pwm3_mux[] = {
3048 PWM3_MARK,
3049};
3050static const unsigned int pwm4_pins[] = {
3051 RCAR_GP_PIN(3, 26),
3052};
3053static const unsigned int pwm4_mux[] = {
3054 PWM4_MARK,
3055};
3056static const unsigned int pwm4_b_pins[] = {
3057 RCAR_GP_PIN(3, 31),
3058};
3059static const unsigned int pwm4_b_mux[] = {
3060 PWM4_B_MARK,
3061};
3062static const unsigned int pwm5_pins[] = {
3063 RCAR_GP_PIN(7, 21),
3064};
3065static const unsigned int pwm5_mux[] = {
3066 PWM5_MARK,
3067};
3068static const unsigned int pwm5_b_pins[] = {
3069 RCAR_GP_PIN(7, 20),
3070};
3071static const unsigned int pwm5_b_mux[] = {
3072 PWM5_B_MARK,
3073};
3074static const unsigned int pwm6_pins[] = {
3075 RCAR_GP_PIN(7, 22),
3076};
3077static const unsigned int pwm6_mux[] = {
3078 PWM6_MARK,
3079};
3080/* - QSPI ------------------------------------------------------------------- */
3081static const unsigned int qspi_ctrl_pins[] = {
3082 /* SPCLK, SSL */
3083 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3084};
3085static const unsigned int qspi_ctrl_mux[] = {
3086 SPCLK_MARK, SSL_MARK,
3087};
3088static const unsigned int qspi_data2_pins[] = {
3089 /* MOSI_IO0, MISO_IO1 */
3090 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3091};
3092static const unsigned int qspi_data2_mux[] = {
3093 MOSI_IO0_MARK, MISO_IO1_MARK,
3094};
3095static const unsigned int qspi_data4_pins[] = {
3096 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3097 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3098 RCAR_GP_PIN(1, 8),
3099};
3100static const unsigned int qspi_data4_mux[] = {
3101 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3102};
3103
3104static const unsigned int qspi_ctrl_b_pins[] = {
3105 /* SPCLK, SSL */
3106 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3107};
3108static const unsigned int qspi_ctrl_b_mux[] = {
3109 SPCLK_B_MARK, SSL_B_MARK,
3110};
3111static const unsigned int qspi_data2_b_pins[] = {
3112 /* MOSI_IO0, MISO_IO1 */
3113 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3114};
3115static const unsigned int qspi_data2_b_mux[] = {
3116 MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3117};
3118static const unsigned int qspi_data4_b_pins[] = {
3119 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3120 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3121 RCAR_GP_PIN(6, 4),
3122};
3123static const unsigned int qspi_data4_b_mux[] = {
3124 SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3125 IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3126};
3127/* - SCIF0 ------------------------------------------------------------------ */
3128static const unsigned int scif0_data_pins[] = {
3129 /* RX, TX */
3130 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3131};
3132static const unsigned int scif0_data_mux[] = {
3133 RX0_MARK, TX0_MARK,
3134};
3135static const unsigned int scif0_data_b_pins[] = {
3136 /* RX, TX */
3137 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3138};
3139static const unsigned int scif0_data_b_mux[] = {
3140 RX0_B_MARK, TX0_B_MARK,
3141};
3142static const unsigned int scif0_data_c_pins[] = {
3143 /* RX, TX */
3144 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3145};
3146static const unsigned int scif0_data_c_mux[] = {
3147 RX0_C_MARK, TX0_C_MARK,
3148};
3149static const unsigned int scif0_data_d_pins[] = {
3150 /* RX, TX */
3151 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3152};
3153static const unsigned int scif0_data_d_mux[] = {
3154 RX0_D_MARK, TX0_D_MARK,
3155};
3156static const unsigned int scif0_data_e_pins[] = {
3157 /* RX, TX */
3158 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3159};
3160static const unsigned int scif0_data_e_mux[] = {
3161 RX0_E_MARK, TX0_E_MARK,
3162};
3163/* - SCIF1 ------------------------------------------------------------------ */
3164static const unsigned int scif1_data_pins[] = {
3165 /* RX, TX */
3166 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3167};
3168static const unsigned int scif1_data_mux[] = {
3169 RX1_MARK, TX1_MARK,
3170};
3171static const unsigned int scif1_data_b_pins[] = {
3172 /* RX, TX */
3173 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3174};
3175static const unsigned int scif1_data_b_mux[] = {
3176 RX1_B_MARK, TX1_B_MARK,
3177};
3178static const unsigned int scif1_clk_b_pins[] = {
3179 /* SCK */
3180 RCAR_GP_PIN(3, 10),
3181};
3182static const unsigned int scif1_clk_b_mux[] = {
3183 SCIF1_SCK_B_MARK,
3184};
3185static const unsigned int scif1_data_c_pins[] = {
3186 /* RX, TX */
3187 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3188};
3189static const unsigned int scif1_data_c_mux[] = {
3190 RX1_C_MARK, TX1_C_MARK,
3191};
3192static const unsigned int scif1_data_d_pins[] = {
3193 /* RX, TX */
3194 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3195};
3196static const unsigned int scif1_data_d_mux[] = {
3197 RX1_D_MARK, TX1_D_MARK,
3198};
3199/* - SCIF2 ------------------------------------------------------------------ */
3200static const unsigned int scif2_data_pins[] = {
3201 /* RX, TX */
3202 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3203};
3204static const unsigned int scif2_data_mux[] = {
3205 RX2_MARK, TX2_MARK,
3206};
3207static const unsigned int scif2_data_b_pins[] = {
3208 /* RX, TX */
3209 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3210};
3211static const unsigned int scif2_data_b_mux[] = {
3212 RX2_B_MARK, TX2_B_MARK,
3213};
3214static const unsigned int scif2_clk_b_pins[] = {
3215 /* SCK */
3216 RCAR_GP_PIN(3, 18),
3217};
3218static const unsigned int scif2_clk_b_mux[] = {
3219 SCIF2_SCK_B_MARK,
3220};
3221static const unsigned int scif2_data_c_pins[] = {
3222 /* RX, TX */
3223 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3224};
3225static const unsigned int scif2_data_c_mux[] = {
3226 RX2_C_MARK, TX2_C_MARK,
3227};
3228static const unsigned int scif2_data_e_pins[] = {
3229 /* RX, TX */
3230 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3231};
3232static const unsigned int scif2_data_e_mux[] = {
3233 RX2_E_MARK, TX2_E_MARK,
3234};
3235/* - SCIF3 ------------------------------------------------------------------ */
3236static const unsigned int scif3_data_pins[] = {
3237 /* RX, TX */
3238 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3239};
3240static const unsigned int scif3_data_mux[] = {
3241 RX3_MARK, TX3_MARK,
3242};
3243static const unsigned int scif3_clk_pins[] = {
3244 /* SCK */
3245 RCAR_GP_PIN(3, 23),
3246};
3247static const unsigned int scif3_clk_mux[] = {
3248 SCIF3_SCK_MARK,
3249};
3250static const unsigned int scif3_data_b_pins[] = {
3251 /* RX, TX */
3252 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3253};
3254static const unsigned int scif3_data_b_mux[] = {
3255 RX3_B_MARK, TX3_B_MARK,
3256};
3257static const unsigned int scif3_clk_b_pins[] = {
3258 /* SCK */
3259 RCAR_GP_PIN(4, 8),
3260};
3261static const unsigned int scif3_clk_b_mux[] = {
3262 SCIF3_SCK_B_MARK,
3263};
3264static const unsigned int scif3_data_c_pins[] = {
3265 /* RX, TX */
3266 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3267};
3268static const unsigned int scif3_data_c_mux[] = {
3269 RX3_C_MARK, TX3_C_MARK,
3270};
3271static const unsigned int scif3_data_d_pins[] = {
3272 /* RX, TX */
3273 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3274};
3275static const unsigned int scif3_data_d_mux[] = {
3276 RX3_D_MARK, TX3_D_MARK,
3277};
3278/* - SCIF4 ------------------------------------------------------------------ */
3279static const unsigned int scif4_data_pins[] = {
3280 /* RX, TX */
3281 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3282};
3283static const unsigned int scif4_data_mux[] = {
3284 RX4_MARK, TX4_MARK,
3285};
3286static const unsigned int scif4_data_b_pins[] = {
3287 /* RX, TX */
3288 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3289};
3290static const unsigned int scif4_data_b_mux[] = {
3291 RX4_B_MARK, TX4_B_MARK,
3292};
3293static const unsigned int scif4_data_c_pins[] = {
3294 /* RX, TX */
3295 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3296};
3297static const unsigned int scif4_data_c_mux[] = {
3298 RX4_C_MARK, TX4_C_MARK,
3299};
3300/* - SCIF5 ------------------------------------------------------------------ */
3301static const unsigned int scif5_data_pins[] = {
3302 /* RX, TX */
3303 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3304};
3305static const unsigned int scif5_data_mux[] = {
3306 RX5_MARK, TX5_MARK,
3307};
3308static const unsigned int scif5_data_b_pins[] = {
3309 /* RX, TX */
3310 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3311};
3312static const unsigned int scif5_data_b_mux[] = {
3313 RX5_B_MARK, TX5_B_MARK,
3314};
3315/* - SCIFA0 ----------------------------------------------------------------- */
3316static const unsigned int scifa0_data_pins[] = {
3317 /* RXD, TXD */
3318 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3319};
3320static const unsigned int scifa0_data_mux[] = {
3321 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3322};
3323static const unsigned int scifa0_data_b_pins[] = {
3324 /* RXD, TXD */
3325 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3326};
3327static const unsigned int scifa0_data_b_mux[] = {
3328 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3329};
3330/* - SCIFA1 ----------------------------------------------------------------- */
3331static const unsigned int scifa1_data_pins[] = {
3332 /* RXD, TXD */
3333 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3334};
3335static const unsigned int scifa1_data_mux[] = {
3336 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3337};
3338static const unsigned int scifa1_clk_pins[] = {
3339 /* SCK */
3340 RCAR_GP_PIN(3, 10),
3341};
3342static const unsigned int scifa1_clk_mux[] = {
3343 SCIFA1_SCK_MARK,
3344};
3345static const unsigned int scifa1_data_b_pins[] = {
3346 /* RXD, TXD */
3347 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3348};
3349static const unsigned int scifa1_data_b_mux[] = {
3350 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3351};
3352static const unsigned int scifa1_clk_b_pins[] = {
3353 /* SCK */
3354 RCAR_GP_PIN(1, 0),
3355};
3356static const unsigned int scifa1_clk_b_mux[] = {
3357 SCIFA1_SCK_B_MARK,
3358};
3359static const unsigned int scifa1_data_c_pins[] = {
3360 /* RXD, TXD */
3361 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3362};
3363static const unsigned int scifa1_data_c_mux[] = {
3364 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3365};
3366/* - SCIFA2 ----------------------------------------------------------------- */
3367static const unsigned int scifa2_data_pins[] = {
3368 /* RXD, TXD */
3369 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3370};
3371static const unsigned int scifa2_data_mux[] = {
3372 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3373};
3374static const unsigned int scifa2_clk_pins[] = {
3375 /* SCK */
3376 RCAR_GP_PIN(3, 18),
3377};
3378static const unsigned int scifa2_clk_mux[] = {
3379 SCIFA2_SCK_MARK,
3380};
3381static const unsigned int scifa2_data_b_pins[] = {
3382 /* RXD, TXD */
3383 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3384};
3385static const unsigned int scifa2_data_b_mux[] = {
3386 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3387};
3388/* - SCIFA3 ----------------------------------------------------------------- */
3389static const unsigned int scifa3_data_pins[] = {
3390 /* RXD, TXD */
3391 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3392};
3393static const unsigned int scifa3_data_mux[] = {
3394 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3395};
3396static const unsigned int scifa3_clk_pins[] = {
3397 /* SCK */
3398 RCAR_GP_PIN(3, 23),
3399};
3400static const unsigned int scifa3_clk_mux[] = {
3401 SCIFA3_SCK_MARK,
3402};
3403static const unsigned int scifa3_data_b_pins[] = {
3404 /* RXD, TXD */
3405 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3406};
3407static const unsigned int scifa3_data_b_mux[] = {
3408 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3409};
3410static const unsigned int scifa3_clk_b_pins[] = {
3411 /* SCK */
3412 RCAR_GP_PIN(4, 8),
3413};
3414static const unsigned int scifa3_clk_b_mux[] = {
3415 SCIFA3_SCK_B_MARK,
3416};
3417static const unsigned int scifa3_data_c_pins[] = {
3418 /* RXD, TXD */
3419 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3420};
3421static const unsigned int scifa3_data_c_mux[] = {
3422 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3423};
3424static const unsigned int scifa3_clk_c_pins[] = {
3425 /* SCK */
3426 RCAR_GP_PIN(7, 22),
3427};
3428static const unsigned int scifa3_clk_c_mux[] = {
3429 SCIFA3_SCK_C_MARK,
3430};
3431/* - SCIFA4 ----------------------------------------------------------------- */
3432static const unsigned int scifa4_data_pins[] = {
3433 /* RXD, TXD */
3434 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3435};
3436static const unsigned int scifa4_data_mux[] = {
3437 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3438};
3439static const unsigned int scifa4_data_b_pins[] = {
3440 /* RXD, TXD */
3441 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3442};
3443static const unsigned int scifa4_data_b_mux[] = {
3444 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3445};
3446static const unsigned int scifa4_data_c_pins[] = {
3447 /* RXD, TXD */
3448 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3449};
3450static const unsigned int scifa4_data_c_mux[] = {
3451 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3452};
3453/* - SCIFA5 ----------------------------------------------------------------- */
3454static const unsigned int scifa5_data_pins[] = {
3455 /* RXD, TXD */
3456 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3457};
3458static const unsigned int scifa5_data_mux[] = {
3459 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3460};
3461static const unsigned int scifa5_data_b_pins[] = {
3462 /* RXD, TXD */
3463 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3464};
3465static const unsigned int scifa5_data_b_mux[] = {
3466 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3467};
3468static const unsigned int scifa5_data_c_pins[] = {
3469 /* RXD, TXD */
3470 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3471};
3472static const unsigned int scifa5_data_c_mux[] = {
3473 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3474};
3475/* - SCIFB0 ----------------------------------------------------------------- */
3476static const unsigned int scifb0_data_pins[] = {
3477 /* RXD, TXD */
3478 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3479};
3480static const unsigned int scifb0_data_mux[] = {
3481 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3482};
3483static const unsigned int scifb0_clk_pins[] = {
3484 /* SCK */
3485 RCAR_GP_PIN(7, 2),
3486};
3487static const unsigned int scifb0_clk_mux[] = {
3488 SCIFB0_SCK_MARK,
3489};
3490static const unsigned int scifb0_ctrl_pins[] = {
3491 /* RTS, CTS */
3492 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3493};
3494static const unsigned int scifb0_ctrl_mux[] = {
3495 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3496};
3497static const unsigned int scifb0_data_b_pins[] = {
3498 /* RXD, TXD */
3499 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3500};
3501static const unsigned int scifb0_data_b_mux[] = {
3502 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3503};
3504static const unsigned int scifb0_clk_b_pins[] = {
3505 /* SCK */
3506 RCAR_GP_PIN(5, 31),
3507};
3508static const unsigned int scifb0_clk_b_mux[] = {
3509 SCIFB0_SCK_B_MARK,
3510};
3511static const unsigned int scifb0_ctrl_b_pins[] = {
3512 /* RTS, CTS */
3513 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3514};
3515static const unsigned int scifb0_ctrl_b_mux[] = {
3516 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3517};
3518static const unsigned int scifb0_data_c_pins[] = {
3519 /* RXD, TXD */
3520 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3521};
3522static const unsigned int scifb0_data_c_mux[] = {
3523 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3524};
3525static const unsigned int scifb0_clk_c_pins[] = {
3526 /* SCK */
3527 RCAR_GP_PIN(2, 30),
3528};
3529static const unsigned int scifb0_clk_c_mux[] = {
3530 SCIFB0_SCK_C_MARK,
3531};
3532static const unsigned int scifb0_data_d_pins[] = {
3533 /* RXD, TXD */
3534 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3535};
3536static const unsigned int scifb0_data_d_mux[] = {
3537 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3538};
3539static const unsigned int scifb0_clk_d_pins[] = {
3540 /* SCK */
3541 RCAR_GP_PIN(4, 17),
3542};
3543static const unsigned int scifb0_clk_d_mux[] = {
3544 SCIFB0_SCK_D_MARK,
3545};
3546/* - SCIFB1 ----------------------------------------------------------------- */
3547static const unsigned int scifb1_data_pins[] = {
3548 /* RXD, TXD */
3549 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3550};
3551static const unsigned int scifb1_data_mux[] = {
3552 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3553};
3554static const unsigned int scifb1_clk_pins[] = {
3555 /* SCK */
3556 RCAR_GP_PIN(7, 7),
3557};
3558static const unsigned int scifb1_clk_mux[] = {
3559 SCIFB1_SCK_MARK,
3560};
3561static const unsigned int scifb1_ctrl_pins[] = {
3562 /* RTS, CTS */
3563 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3564};
3565static const unsigned int scifb1_ctrl_mux[] = {
3566 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3567};
3568static const unsigned int scifb1_data_b_pins[] = {
3569 /* RXD, TXD */
3570 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3571};
3572static const unsigned int scifb1_data_b_mux[] = {
3573 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3574};
3575static const unsigned int scifb1_clk_b_pins[] = {
3576 /* SCK */
3577 RCAR_GP_PIN(1, 3),
3578};
3579static const unsigned int scifb1_clk_b_mux[] = {
3580 SCIFB1_SCK_B_MARK,
3581};
3582static const unsigned int scifb1_data_c_pins[] = {
3583 /* RXD, TXD */
3584 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3585};
3586static const unsigned int scifb1_data_c_mux[] = {
3587 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3588};
3589static const unsigned int scifb1_clk_c_pins[] = {
3590 /* SCK */
3591 RCAR_GP_PIN(7, 11),
3592};
3593static const unsigned int scifb1_clk_c_mux[] = {
3594 SCIFB1_SCK_C_MARK,
3595};
3596static const unsigned int scifb1_data_d_pins[] = {
3597 /* RXD, TXD */
3598 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3599};
3600static const unsigned int scifb1_data_d_mux[] = {
3601 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3602};
3603/* - SCIFB2 ----------------------------------------------------------------- */
3604static const unsigned int scifb2_data_pins[] = {
3605 /* RXD, TXD */
3606 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3607};
3608static const unsigned int scifb2_data_mux[] = {
3609 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3610};
3611static const unsigned int scifb2_clk_pins[] = {
3612 /* SCK */
3613 RCAR_GP_PIN(4, 15),
3614};
3615static const unsigned int scifb2_clk_mux[] = {
3616 SCIFB2_SCK_MARK,
3617};
3618static const unsigned int scifb2_ctrl_pins[] = {
3619 /* RTS, CTS */
3620 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3621};
3622static const unsigned int scifb2_ctrl_mux[] = {
3623 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3624};
3625static const unsigned int scifb2_data_b_pins[] = {
3626 /* RXD, TXD */
3627 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3628};
3629static const unsigned int scifb2_data_b_mux[] = {
3630 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3631};
3632static const unsigned int scifb2_clk_b_pins[] = {
3633 /* SCK */
3634 RCAR_GP_PIN(5, 31),
3635};
3636static const unsigned int scifb2_clk_b_mux[] = {
3637 SCIFB2_SCK_B_MARK,
3638};
3639static const unsigned int scifb2_ctrl_b_pins[] = {
3640 /* RTS, CTS */
3641 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3642};
3643static const unsigned int scifb2_ctrl_b_mux[] = {
3644 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3645};
3646static const unsigned int scifb2_data_c_pins[] = {
3647 /* RXD, TXD */
3648 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3649};
3650static const unsigned int scifb2_data_c_mux[] = {
3651 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3652};
3653static const unsigned int scifb2_clk_c_pins[] = {
3654 /* SCK */
3655 RCAR_GP_PIN(5, 27),
3656};
3657static const unsigned int scifb2_clk_c_mux[] = {
3658 SCIFB2_SCK_C_MARK,
3659};
3660static const unsigned int scifb2_data_d_pins[] = {
3661 /* RXD, TXD */
3662 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3663};
3664static const unsigned int scifb2_data_d_mux[] = {
3665 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3666};
3667
3668/* - SCIF Clock ------------------------------------------------------------- */
3669static const unsigned int scif_clk_pins[] = {
3670 /* SCIF_CLK */
3671 RCAR_GP_PIN(2, 29),
3672};
3673static const unsigned int scif_clk_mux[] = {
3674 SCIF_CLK_MARK,
3675};
3676static const unsigned int scif_clk_b_pins[] = {
3677 /* SCIF_CLK */
3678 RCAR_GP_PIN(7, 19),
3679};
3680static const unsigned int scif_clk_b_mux[] = {
3681 SCIF_CLK_B_MARK,
3682};
3683
3684/* - SDHI0 ------------------------------------------------------------------ */
3685static const unsigned int sdhi0_data1_pins[] = {
3686 /* D0 */
3687 RCAR_GP_PIN(6, 2),
3688};
3689static const unsigned int sdhi0_data1_mux[] = {
3690 SD0_DATA0_MARK,
3691};
3692static const unsigned int sdhi0_data4_pins[] = {
3693 /* D[0:3] */
3694 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3695 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3696};
3697static const unsigned int sdhi0_data4_mux[] = {
3698 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3699};
3700static const unsigned int sdhi0_ctrl_pins[] = {
3701 /* CLK, CMD */
3702 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3703};
3704static const unsigned int sdhi0_ctrl_mux[] = {
3705 SD0_CLK_MARK, SD0_CMD_MARK,
3706};
3707static const unsigned int sdhi0_cd_pins[] = {
3708 /* CD */
3709 RCAR_GP_PIN(6, 6),
3710};
3711static const unsigned int sdhi0_cd_mux[] = {
3712 SD0_CD_MARK,
3713};
3714static const unsigned int sdhi0_wp_pins[] = {
3715 /* WP */
3716 RCAR_GP_PIN(6, 7),
3717};
3718static const unsigned int sdhi0_wp_mux[] = {
3719 SD0_WP_MARK,
3720};
3721/* - SDHI1 ------------------------------------------------------------------ */
3722static const unsigned int sdhi1_data1_pins[] = {
3723 /* D0 */
3724 RCAR_GP_PIN(6, 10),
3725};
3726static const unsigned int sdhi1_data1_mux[] = {
3727 SD1_DATA0_MARK,
3728};
3729static const unsigned int sdhi1_data4_pins[] = {
3730 /* D[0:3] */
3731 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3732 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3733};
3734static const unsigned int sdhi1_data4_mux[] = {
3735 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3736};
3737static const unsigned int sdhi1_ctrl_pins[] = {
3738 /* CLK, CMD */
3739 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3740};
3741static const unsigned int sdhi1_ctrl_mux[] = {
3742 SD1_CLK_MARK, SD1_CMD_MARK,
3743};
3744static const unsigned int sdhi1_cd_pins[] = {
3745 /* CD */
3746 RCAR_GP_PIN(6, 14),
3747};
3748static const unsigned int sdhi1_cd_mux[] = {
3749 SD1_CD_MARK,
3750};
3751static const unsigned int sdhi1_wp_pins[] = {
3752 /* WP */
3753 RCAR_GP_PIN(6, 15),
3754};
3755static const unsigned int sdhi1_wp_mux[] = {
3756 SD1_WP_MARK,
3757};
3758/* - SDHI2 ------------------------------------------------------------------ */
3759static const unsigned int sdhi2_data1_pins[] = {
3760 /* D0 */
3761 RCAR_GP_PIN(6, 18),
3762};
3763static const unsigned int sdhi2_data1_mux[] = {
3764 SD2_DATA0_MARK,
3765};
3766static const unsigned int sdhi2_data4_pins[] = {
3767 /* D[0:3] */
3768 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3769 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3770};
3771static const unsigned int sdhi2_data4_mux[] = {
3772 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3773};
3774static const unsigned int sdhi2_ctrl_pins[] = {
3775 /* CLK, CMD */
3776 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3777};
3778static const unsigned int sdhi2_ctrl_mux[] = {
3779 SD2_CLK_MARK, SD2_CMD_MARK,
3780};
3781static const unsigned int sdhi2_cd_pins[] = {
3782 /* CD */
3783 RCAR_GP_PIN(6, 22),
3784};
3785static const unsigned int sdhi2_cd_mux[] = {
3786 SD2_CD_MARK,
3787};
3788static const unsigned int sdhi2_wp_pins[] = {
3789 /* WP */
3790 RCAR_GP_PIN(6, 23),
3791};
3792static const unsigned int sdhi2_wp_mux[] = {
3793 SD2_WP_MARK,
3794};
3795
3796/* - SSI -------------------------------------------------------------------- */
3797static const unsigned int ssi0_data_pins[] = {
3798 /* SDATA */
3799 RCAR_GP_PIN(2, 2),
3800};
3801
3802static const unsigned int ssi0_data_mux[] = {
3803 SSI_SDATA0_MARK,
3804};
3805
3806static const unsigned int ssi0_data_b_pins[] = {
3807 /* SDATA */
3808 RCAR_GP_PIN(3, 4),
3809};
3810
3811static const unsigned int ssi0_data_b_mux[] = {
3812 SSI_SDATA0_B_MARK,
3813};
3814
3815static const unsigned int ssi0129_ctrl_pins[] = {
3816 /* SCK, WS */
3817 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3818};
3819
3820static const unsigned int ssi0129_ctrl_mux[] = {
3821 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3822};
3823
3824static const unsigned int ssi0129_ctrl_b_pins[] = {
3825 /* SCK, WS */
3826 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3827};
3828
3829static const unsigned int ssi0129_ctrl_b_mux[] = {
3830 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3831};
3832
3833static const unsigned int ssi1_data_pins[] = {
3834 /* SDATA */
3835 RCAR_GP_PIN(2, 5),
3836};
3837
3838static const unsigned int ssi1_data_mux[] = {
3839 SSI_SDATA1_MARK,
3840};
3841
3842static const unsigned int ssi1_data_b_pins[] = {
3843 /* SDATA */
3844 RCAR_GP_PIN(3, 7),
3845};
3846
3847static const unsigned int ssi1_data_b_mux[] = {
3848 SSI_SDATA1_B_MARK,
3849};
3850
3851static const unsigned int ssi1_ctrl_pins[] = {
3852 /* SCK, WS */
3853 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3854};
3855
3856static const unsigned int ssi1_ctrl_mux[] = {
3857 SSI_SCK1_MARK, SSI_WS1_MARK,
3858};
3859
3860static const unsigned int ssi1_ctrl_b_pins[] = {
3861 /* SCK, WS */
3862 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3863};
3864
3865static const unsigned int ssi1_ctrl_b_mux[] = {
3866 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3867};
3868
3869static const unsigned int ssi2_data_pins[] = {
3870 /* SDATA */
3871 RCAR_GP_PIN(2, 8),
3872};
3873
3874static const unsigned int ssi2_data_mux[] = {
3875 SSI_SDATA2_MARK,
3876};
3877
3878static const unsigned int ssi2_ctrl_pins[] = {
3879 /* SCK, WS */
3880 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3881};
3882
3883static const unsigned int ssi2_ctrl_mux[] = {
3884 SSI_SCK2_MARK, SSI_WS2_MARK,
3885};
3886
3887static const unsigned int ssi3_data_pins[] = {
3888 /* SDATA */
3889 RCAR_GP_PIN(2, 11),
3890};
3891
3892static const unsigned int ssi3_data_mux[] = {
3893 SSI_SDATA3_MARK,
3894};
3895
3896static const unsigned int ssi34_ctrl_pins[] = {
3897 /* SCK, WS */
3898 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3899};
3900
3901static const unsigned int ssi34_ctrl_mux[] = {
3902 SSI_SCK34_MARK, SSI_WS34_MARK,
3903};
3904
3905static const unsigned int ssi4_data_pins[] = {
3906 /* SDATA */
3907 RCAR_GP_PIN(2, 14),
3908};
3909
3910static const unsigned int ssi4_data_mux[] = {
3911 SSI_SDATA4_MARK,
3912};
3913
3914static const unsigned int ssi4_ctrl_pins[] = {
3915 /* SCK, WS */
3916 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3917};
3918
3919static const unsigned int ssi4_ctrl_mux[] = {
3920 SSI_SCK4_MARK, SSI_WS4_MARK,
3921};
3922
3923static const unsigned int ssi5_data_pins[] = {
3924 /* SDATA */
3925 RCAR_GP_PIN(2, 17),
3926};
3927
3928static const unsigned int ssi5_data_mux[] = {
3929 SSI_SDATA5_MARK,
3930};
3931
3932static const unsigned int ssi5_ctrl_pins[] = {
3933 /* SCK, WS */
3934 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3935};
3936
3937static const unsigned int ssi5_ctrl_mux[] = {
3938 SSI_SCK5_MARK, SSI_WS5_MARK,
3939};
3940
3941static const unsigned int ssi6_data_pins[] = {
3942 /* SDATA */
3943 RCAR_GP_PIN(2, 20),
3944};
3945
3946static const unsigned int ssi6_data_mux[] = {
3947 SSI_SDATA6_MARK,
3948};
3949
3950static const unsigned int ssi6_ctrl_pins[] = {
3951 /* SCK, WS */
3952 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
3953};
3954
3955static const unsigned int ssi6_ctrl_mux[] = {
3956 SSI_SCK6_MARK, SSI_WS6_MARK,
3957};
3958
3959static const unsigned int ssi7_data_pins[] = {
3960 /* SDATA */
3961 RCAR_GP_PIN(2, 23),
3962};
3963
3964static const unsigned int ssi7_data_mux[] = {
3965 SSI_SDATA7_MARK,
3966};
3967
3968static const unsigned int ssi7_data_b_pins[] = {
3969 /* SDATA */
3970 RCAR_GP_PIN(3, 12),
3971};
3972
3973static const unsigned int ssi7_data_b_mux[] = {
3974 SSI_SDATA7_B_MARK,
3975};
3976
3977static const unsigned int ssi78_ctrl_pins[] = {
3978 /* SCK, WS */
3979 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3980};
3981
3982static const unsigned int ssi78_ctrl_mux[] = {
3983 SSI_SCK78_MARK, SSI_WS78_MARK,
3984};
3985
3986static const unsigned int ssi78_ctrl_b_pins[] = {
3987 /* SCK, WS */
3988 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3989};
3990
3991static const unsigned int ssi78_ctrl_b_mux[] = {
3992 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3993};
3994
3995static const unsigned int ssi8_data_pins[] = {
3996 /* SDATA */
3997 RCAR_GP_PIN(2, 24),
3998};
3999
4000static const unsigned int ssi8_data_mux[] = {
4001 SSI_SDATA8_MARK,
4002};
4003
4004static const unsigned int ssi8_data_b_pins[] = {
4005 /* SDATA */
4006 RCAR_GP_PIN(3, 13),
4007};
4008
4009static const unsigned int ssi8_data_b_mux[] = {
4010 SSI_SDATA8_B_MARK,
4011};
4012
4013static const unsigned int ssi9_data_pins[] = {
4014 /* SDATA */
4015 RCAR_GP_PIN(2, 27),
4016};
4017
4018static const unsigned int ssi9_data_mux[] = {
4019 SSI_SDATA9_MARK,
4020};
4021
4022static const unsigned int ssi9_data_b_pins[] = {
4023 /* SDATA */
4024 RCAR_GP_PIN(3, 18),
4025};
4026
4027static const unsigned int ssi9_data_b_mux[] = {
4028 SSI_SDATA9_B_MARK,
4029};
4030
4031static const unsigned int ssi9_ctrl_pins[] = {
4032 /* SCK, WS */
4033 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4034};
4035
4036static const unsigned int ssi9_ctrl_mux[] = {
4037 SSI_SCK9_MARK, SSI_WS9_MARK,
4038};
4039
4040static const unsigned int ssi9_ctrl_b_pins[] = {
4041 /* SCK, WS */
4042 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4043};
4044
4045static const unsigned int ssi9_ctrl_b_mux[] = {
4046 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4047};
4048
4049/* - USB0 ------------------------------------------------------------------- */
4050static const unsigned int usb0_pins[] = {
4051 RCAR_GP_PIN(7, 23), /* PWEN */
4052 RCAR_GP_PIN(7, 24), /* OVC */
4053};
4054static const unsigned int usb0_mux[] = {
4055 USB0_PWEN_MARK,
4056 USB0_OVC_MARK,
4057};
4058/* - USB1 ------------------------------------------------------------------- */
4059static const unsigned int usb1_pins[] = {
4060 RCAR_GP_PIN(7, 25), /* PWEN */
4061 RCAR_GP_PIN(6, 30), /* OVC */
4062};
4063static const unsigned int usb1_mux[] = {
4064 USB1_PWEN_MARK,
4065 USB1_OVC_MARK,
4066};
4067/* - VIN0 ------------------------------------------------------------------- */
4068static const union vin_data vin0_data_pins = {
4069 .data24 = {
4070 /* B */
4071 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4072 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4073 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4074 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4075 /* G */
4076 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4077 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4078 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4079 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4080 /* R */
4081 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4082 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4083 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4084 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4085 },
4086};
4087static const union vin_data vin0_data_mux = {
4088 .data24 = {
4089 /* B */
4090 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4091 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4092 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4093 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4094 /* G */
4095 VI0_G0_MARK, VI0_G1_MARK,
4096 VI0_G2_MARK, VI0_G3_MARK,
4097 VI0_G4_MARK, VI0_G5_MARK,
4098 VI0_G6_MARK, VI0_G7_MARK,
4099 /* R */
4100 VI0_R0_MARK, VI0_R1_MARK,
4101 VI0_R2_MARK, VI0_R3_MARK,
4102 VI0_R4_MARK, VI0_R5_MARK,
4103 VI0_R6_MARK, VI0_R7_MARK,
4104 },
4105};
4106static const unsigned int vin0_data18_pins[] = {
4107 /* B */
4108 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4109 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4110 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4111 /* G */
4112 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4113 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4114 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4115 /* R */
4116 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4117 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4118 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4119};
4120static const unsigned int vin0_data18_mux[] = {
4121 /* B */
4122 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4123 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4124 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4125 /* G */
4126 VI0_G2_MARK, VI0_G3_MARK,
4127 VI0_G4_MARK, VI0_G5_MARK,
4128 VI0_G6_MARK, VI0_G7_MARK,
4129 /* R */
4130 VI0_R2_MARK, VI0_R3_MARK,
4131 VI0_R4_MARK, VI0_R5_MARK,
4132 VI0_R6_MARK, VI0_R7_MARK,
4133};
4134static const unsigned int vin0_sync_pins[] = {
4135 RCAR_GP_PIN(4, 3), /* HSYNC */
4136 RCAR_GP_PIN(4, 4), /* VSYNC */
4137};
4138static const unsigned int vin0_sync_mux[] = {
4139 VI0_HSYNC_N_MARK,
4140 VI0_VSYNC_N_MARK,
4141};
4142static const unsigned int vin0_field_pins[] = {
4143 RCAR_GP_PIN(4, 2),
4144};
4145static const unsigned int vin0_field_mux[] = {
4146 VI0_FIELD_MARK,
4147};
4148static const unsigned int vin0_clkenb_pins[] = {
4149 RCAR_GP_PIN(4, 1),
4150};
4151static const unsigned int vin0_clkenb_mux[] = {
4152 VI0_CLKENB_MARK,
4153};
4154static const unsigned int vin0_clk_pins[] = {
4155 RCAR_GP_PIN(4, 0),
4156};
4157static const unsigned int vin0_clk_mux[] = {
4158 VI0_CLK_MARK,
4159};
4160/* - VIN1 ----------------------------------------------------------------- */
4161static const unsigned int vin1_data8_pins[] = {
4162 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4163 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4164 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4165 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4166};
4167static const unsigned int vin1_data8_mux[] = {
4168 VI1_DATA0_MARK, VI1_DATA1_MARK,
4169 VI1_DATA2_MARK, VI1_DATA3_MARK,
4170 VI1_DATA4_MARK, VI1_DATA5_MARK,
4171 VI1_DATA6_MARK, VI1_DATA7_MARK,
4172};
4173static const unsigned int vin1_sync_pins[] = {
4174 RCAR_GP_PIN(5, 0), /* HSYNC */
4175 RCAR_GP_PIN(5, 1), /* VSYNC */
4176};
4177static const unsigned int vin1_sync_mux[] = {
4178 VI1_HSYNC_N_MARK,
4179 VI1_VSYNC_N_MARK,
4180};
4181static const unsigned int vin1_field_pins[] = {
4182 RCAR_GP_PIN(5, 3),
4183};
4184static const unsigned int vin1_field_mux[] = {
4185 VI1_FIELD_MARK,
4186};
4187static const unsigned int vin1_clkenb_pins[] = {
4188 RCAR_GP_PIN(5, 2),
4189};
4190static const unsigned int vin1_clkenb_mux[] = {
4191 VI1_CLKENB_MARK,
4192};
4193static const unsigned int vin1_clk_pins[] = {
4194 RCAR_GP_PIN(5, 4),
4195};
4196static const unsigned int vin1_clk_mux[] = {
4197 VI1_CLK_MARK,
4198};
4199static const union vin_data vin1_b_data_pins = {
4200 .data24 = {
4201 /* B */
4202 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4203 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4204 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4205 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4206 /* G */
4207 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4208 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4209 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4210 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4211 /* R */
4212 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4213 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4214 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4215 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4216 },
4217};
4218static const union vin_data vin1_b_data_mux = {
4219 .data24 = {
4220 /* B */
4221 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4222 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4223 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4224 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4225 /* G */
4226 VI1_G0_B_MARK, VI1_G1_B_MARK,
4227 VI1_G2_B_MARK, VI1_G3_B_MARK,
4228 VI1_G4_B_MARK, VI1_G5_B_MARK,
4229 VI1_G6_B_MARK, VI1_G7_B_MARK,
4230 /* R */
4231 VI1_R0_B_MARK, VI1_R1_B_MARK,
4232 VI1_R2_B_MARK, VI1_R3_B_MARK,
4233 VI1_R4_B_MARK, VI1_R5_B_MARK,
4234 VI1_R6_B_MARK, VI1_R7_B_MARK,
4235 },
4236};
4237static const unsigned int vin1_b_data18_pins[] = {
4238 /* B */
4239 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4240 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4241 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4242 /* G */
4243 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4244 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4245 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4246 /* R */
4247 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4248 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4249 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4250};
4251static const unsigned int vin1_b_data18_mux[] = {
4252 /* B */
4253 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4254 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4255 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4256 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4257 /* G */
4258 VI1_G0_B_MARK, VI1_G1_B_MARK,
4259 VI1_G2_B_MARK, VI1_G3_B_MARK,
4260 VI1_G4_B_MARK, VI1_G5_B_MARK,
4261 VI1_G6_B_MARK, VI1_G7_B_MARK,
4262 /* R */
4263 VI1_R0_B_MARK, VI1_R1_B_MARK,
4264 VI1_R2_B_MARK, VI1_R3_B_MARK,
4265 VI1_R4_B_MARK, VI1_R5_B_MARK,
4266 VI1_R6_B_MARK, VI1_R7_B_MARK,
4267};
4268static const unsigned int vin1_b_sync_pins[] = {
4269 RCAR_GP_PIN(3, 17), /* HSYNC */
4270 RCAR_GP_PIN(3, 18), /* VSYNC */
4271};
4272static const unsigned int vin1_b_sync_mux[] = {
4273 VI1_HSYNC_N_B_MARK,
4274 VI1_VSYNC_N_B_MARK,
4275};
4276static const unsigned int vin1_b_field_pins[] = {
4277 RCAR_GP_PIN(3, 20),
4278};
4279static const unsigned int vin1_b_field_mux[] = {
4280 VI1_FIELD_B_MARK,
4281};
4282static const unsigned int vin1_b_clkenb_pins[] = {
4283 RCAR_GP_PIN(3, 19),
4284};
4285static const unsigned int vin1_b_clkenb_mux[] = {
4286 VI1_CLKENB_B_MARK,
4287};
4288static const unsigned int vin1_b_clk_pins[] = {
4289 RCAR_GP_PIN(3, 16),
4290};
4291static const unsigned int vin1_b_clk_mux[] = {
4292 VI1_CLK_B_MARK,
4293};
4294/* - VIN2 ----------------------------------------------------------------- */
4295static const unsigned int vin2_data8_pins[] = {
4296 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4297 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4298 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4299 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4300};
4301static const unsigned int vin2_data8_mux[] = {
4302 VI2_DATA0_MARK, VI2_DATA1_MARK,
4303 VI2_DATA2_MARK, VI2_DATA3_MARK,
4304 VI2_DATA4_MARK, VI2_DATA5_MARK,
4305 VI2_DATA6_MARK, VI2_DATA7_MARK,
4306};
4307static const unsigned int vin2_sync_pins[] = {
4308 RCAR_GP_PIN(4, 15), /* HSYNC */
4309 RCAR_GP_PIN(4, 16), /* VSYNC */
4310};
4311static const unsigned int vin2_sync_mux[] = {
4312 VI2_HSYNC_N_MARK,
4313 VI2_VSYNC_N_MARK,
4314};
4315static const unsigned int vin2_field_pins[] = {
4316 RCAR_GP_PIN(4, 18),
4317};
4318static const unsigned int vin2_field_mux[] = {
4319 VI2_FIELD_MARK,
4320};
4321static const unsigned int vin2_clkenb_pins[] = {
4322 RCAR_GP_PIN(4, 17),
4323};
4324static const unsigned int vin2_clkenb_mux[] = {
4325 VI2_CLKENB_MARK,
4326};
4327static const unsigned int vin2_clk_pins[] = {
4328 RCAR_GP_PIN(4, 19),
4329};
4330static const unsigned int vin2_clk_mux[] = {
4331 VI2_CLK_MARK,
4332};
4333
4334static const struct sh_pfc_pin_group pinmux_groups[] = {
4335 SH_PFC_PIN_GROUP(audio_clk_a),
4336 SH_PFC_PIN_GROUP(audio_clk_b),
4337 SH_PFC_PIN_GROUP(audio_clk_b_b),
4338 SH_PFC_PIN_GROUP(audio_clk_c),
4339 SH_PFC_PIN_GROUP(audio_clkout),
4340 SH_PFC_PIN_GROUP(avb_link),
4341 SH_PFC_PIN_GROUP(avb_magic),
4342 SH_PFC_PIN_GROUP(avb_phy_int),
4343 SH_PFC_PIN_GROUP(avb_mdio),
4344 SH_PFC_PIN_GROUP(avb_mii),
4345 SH_PFC_PIN_GROUP(avb_gmii),
4346 SH_PFC_PIN_GROUP(can0_data),
4347 SH_PFC_PIN_GROUP(can0_data_b),
4348 SH_PFC_PIN_GROUP(can0_data_c),
4349 SH_PFC_PIN_GROUP(can0_data_d),
4350 SH_PFC_PIN_GROUP(can0_data_e),
4351 SH_PFC_PIN_GROUP(can0_data_f),
4352 SH_PFC_PIN_GROUP(can1_data),
4353 SH_PFC_PIN_GROUP(can1_data_b),
4354 SH_PFC_PIN_GROUP(can1_data_c),
4355 SH_PFC_PIN_GROUP(can1_data_d),
4356 SH_PFC_PIN_GROUP(can_clk),
4357 SH_PFC_PIN_GROUP(can_clk_b),
4358 SH_PFC_PIN_GROUP(can_clk_c),
4359 SH_PFC_PIN_GROUP(can_clk_d),
4360 SH_PFC_PIN_GROUP(du_rgb666),
4361 SH_PFC_PIN_GROUP(du_rgb888),
4362 SH_PFC_PIN_GROUP(du_clk_out_0),
4363 SH_PFC_PIN_GROUP(du_clk_out_1),
4364 SH_PFC_PIN_GROUP(du_sync),
4365 SH_PFC_PIN_GROUP(du_oddf),
4366 SH_PFC_PIN_GROUP(du_cde),
4367 SH_PFC_PIN_GROUP(du_disp),
4368 SH_PFC_PIN_GROUP(du0_clk_in),
4369 SH_PFC_PIN_GROUP(du1_clk_in),
4370 SH_PFC_PIN_GROUP(du1_clk_in_b),
4371 SH_PFC_PIN_GROUP(du1_clk_in_c),
4372 SH_PFC_PIN_GROUP(eth_link),
4373 SH_PFC_PIN_GROUP(eth_magic),
4374 SH_PFC_PIN_GROUP(eth_mdio),
4375 SH_PFC_PIN_GROUP(eth_rmii),
4376 SH_PFC_PIN_GROUP(hscif0_data),
4377 SH_PFC_PIN_GROUP(hscif0_clk),
4378 SH_PFC_PIN_GROUP(hscif0_ctrl),
4379 SH_PFC_PIN_GROUP(hscif0_data_b),
4380 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4381 SH_PFC_PIN_GROUP(hscif0_data_c),
4382 SH_PFC_PIN_GROUP(hscif0_clk_c),
4383 SH_PFC_PIN_GROUP(hscif1_data),
4384 SH_PFC_PIN_GROUP(hscif1_clk),
4385 SH_PFC_PIN_GROUP(hscif1_ctrl),
4386 SH_PFC_PIN_GROUP(hscif1_data_b),
4387 SH_PFC_PIN_GROUP(hscif1_data_c),
4388 SH_PFC_PIN_GROUP(hscif1_clk_c),
4389 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4390 SH_PFC_PIN_GROUP(hscif1_data_d),
4391 SH_PFC_PIN_GROUP(hscif1_data_e),
4392 SH_PFC_PIN_GROUP(hscif1_clk_e),
4393 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4394 SH_PFC_PIN_GROUP(hscif2_data),
4395 SH_PFC_PIN_GROUP(hscif2_clk),
4396 SH_PFC_PIN_GROUP(hscif2_ctrl),
4397 SH_PFC_PIN_GROUP(hscif2_data_b),
4398 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4399 SH_PFC_PIN_GROUP(hscif2_data_c),
4400 SH_PFC_PIN_GROUP(hscif2_clk_c),
4401 SH_PFC_PIN_GROUP(hscif2_data_d),
4402 SH_PFC_PIN_GROUP(i2c0),
4403 SH_PFC_PIN_GROUP(i2c0_b),
4404 SH_PFC_PIN_GROUP(i2c0_c),
4405 SH_PFC_PIN_GROUP(i2c1),
4406 SH_PFC_PIN_GROUP(i2c1_b),
4407 SH_PFC_PIN_GROUP(i2c1_c),
4408 SH_PFC_PIN_GROUP(i2c1_d),
4409 SH_PFC_PIN_GROUP(i2c1_e),
4410 SH_PFC_PIN_GROUP(i2c2),
4411 SH_PFC_PIN_GROUP(i2c2_b),
4412 SH_PFC_PIN_GROUP(i2c2_c),
4413 SH_PFC_PIN_GROUP(i2c2_d),
4414 SH_PFC_PIN_GROUP(i2c3),
4415 SH_PFC_PIN_GROUP(i2c3_b),
4416 SH_PFC_PIN_GROUP(i2c3_c),
4417 SH_PFC_PIN_GROUP(i2c3_d),
4418 SH_PFC_PIN_GROUP(i2c4),
4419 SH_PFC_PIN_GROUP(i2c4_b),
4420 SH_PFC_PIN_GROUP(i2c4_c),
4421 SH_PFC_PIN_GROUP(i2c7),
4422 SH_PFC_PIN_GROUP(i2c7_b),
4423 SH_PFC_PIN_GROUP(i2c7_c),
4424 SH_PFC_PIN_GROUP(i2c8),
4425 SH_PFC_PIN_GROUP(i2c8_b),
4426 SH_PFC_PIN_GROUP(i2c8_c),
4427 SH_PFC_PIN_GROUP(intc_irq0),
4428 SH_PFC_PIN_GROUP(intc_irq1),
4429 SH_PFC_PIN_GROUP(intc_irq2),
4430 SH_PFC_PIN_GROUP(intc_irq3),
4431 SH_PFC_PIN_GROUP(mlb_3pin),
4432 SH_PFC_PIN_GROUP(mmc_data1),
4433 SH_PFC_PIN_GROUP(mmc_data4),
4434 SH_PFC_PIN_GROUP(mmc_data8),
4435 SH_PFC_PIN_GROUP(mmc_ctrl),
4436 SH_PFC_PIN_GROUP(msiof0_clk),
4437 SH_PFC_PIN_GROUP(msiof0_sync),
4438 SH_PFC_PIN_GROUP(msiof0_ss1),
4439 SH_PFC_PIN_GROUP(msiof0_ss2),
4440 SH_PFC_PIN_GROUP(msiof0_rx),
4441 SH_PFC_PIN_GROUP(msiof0_tx),
4442 SH_PFC_PIN_GROUP(msiof0_clk_b),
4443 SH_PFC_PIN_GROUP(msiof0_sync_b),
4444 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4445 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4446 SH_PFC_PIN_GROUP(msiof0_rx_b),
4447 SH_PFC_PIN_GROUP(msiof0_tx_b),
4448 SH_PFC_PIN_GROUP(msiof0_clk_c),
4449 SH_PFC_PIN_GROUP(msiof0_sync_c),
4450 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4451 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4452 SH_PFC_PIN_GROUP(msiof0_rx_c),
4453 SH_PFC_PIN_GROUP(msiof0_tx_c),
4454 SH_PFC_PIN_GROUP(msiof1_clk),
4455 SH_PFC_PIN_GROUP(msiof1_sync),
4456 SH_PFC_PIN_GROUP(msiof1_ss1),
4457 SH_PFC_PIN_GROUP(msiof1_ss2),
4458 SH_PFC_PIN_GROUP(msiof1_rx),
4459 SH_PFC_PIN_GROUP(msiof1_tx),
4460 SH_PFC_PIN_GROUP(msiof1_clk_b),
4461 SH_PFC_PIN_GROUP(msiof1_sync_b),
4462 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4463 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4464 SH_PFC_PIN_GROUP(msiof1_rx_b),
4465 SH_PFC_PIN_GROUP(msiof1_tx_b),
4466 SH_PFC_PIN_GROUP(msiof1_clk_c),
4467 SH_PFC_PIN_GROUP(msiof1_sync_c),
4468 SH_PFC_PIN_GROUP(msiof1_rx_c),
4469 SH_PFC_PIN_GROUP(msiof1_tx_c),
4470 SH_PFC_PIN_GROUP(msiof1_clk_d),
4471 SH_PFC_PIN_GROUP(msiof1_sync_d),
4472 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4473 SH_PFC_PIN_GROUP(msiof1_rx_d),
4474 SH_PFC_PIN_GROUP(msiof1_tx_d),
4475 SH_PFC_PIN_GROUP(msiof1_clk_e),
4476 SH_PFC_PIN_GROUP(msiof1_sync_e),
4477 SH_PFC_PIN_GROUP(msiof1_rx_e),
4478 SH_PFC_PIN_GROUP(msiof1_tx_e),
4479 SH_PFC_PIN_GROUP(msiof2_clk),
4480 SH_PFC_PIN_GROUP(msiof2_sync),
4481 SH_PFC_PIN_GROUP(msiof2_ss1),
4482 SH_PFC_PIN_GROUP(msiof2_ss2),
4483 SH_PFC_PIN_GROUP(msiof2_rx),
4484 SH_PFC_PIN_GROUP(msiof2_tx),
4485 SH_PFC_PIN_GROUP(msiof2_clk_b),
4486 SH_PFC_PIN_GROUP(msiof2_sync_b),
4487 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4488 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4489 SH_PFC_PIN_GROUP(msiof2_rx_b),
4490 SH_PFC_PIN_GROUP(msiof2_tx_b),
4491 SH_PFC_PIN_GROUP(msiof2_clk_c),
4492 SH_PFC_PIN_GROUP(msiof2_sync_c),
4493 SH_PFC_PIN_GROUP(msiof2_rx_c),
4494 SH_PFC_PIN_GROUP(msiof2_tx_c),
4495 SH_PFC_PIN_GROUP(msiof2_clk_d),
4496 SH_PFC_PIN_GROUP(msiof2_sync_d),
4497 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4498 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4499 SH_PFC_PIN_GROUP(msiof2_rx_d),
4500 SH_PFC_PIN_GROUP(msiof2_tx_d),
4501 SH_PFC_PIN_GROUP(msiof2_clk_e),
4502 SH_PFC_PIN_GROUP(msiof2_sync_e),
4503 SH_PFC_PIN_GROUP(msiof2_rx_e),
4504 SH_PFC_PIN_GROUP(msiof2_tx_e),
4505 SH_PFC_PIN_GROUP(pwm0),
4506 SH_PFC_PIN_GROUP(pwm0_b),
4507 SH_PFC_PIN_GROUP(pwm1),
4508 SH_PFC_PIN_GROUP(pwm1_b),
4509 SH_PFC_PIN_GROUP(pwm2),
4510 SH_PFC_PIN_GROUP(pwm2_b),
4511 SH_PFC_PIN_GROUP(pwm3),
4512 SH_PFC_PIN_GROUP(pwm4),
4513 SH_PFC_PIN_GROUP(pwm4_b),
4514 SH_PFC_PIN_GROUP(pwm5),
4515 SH_PFC_PIN_GROUP(pwm5_b),
4516 SH_PFC_PIN_GROUP(pwm6),
4517 SH_PFC_PIN_GROUP(qspi_ctrl),
4518 SH_PFC_PIN_GROUP(qspi_data2),
4519 SH_PFC_PIN_GROUP(qspi_data4),
4520 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4521 SH_PFC_PIN_GROUP(qspi_data2_b),
4522 SH_PFC_PIN_GROUP(qspi_data4_b),
4523 SH_PFC_PIN_GROUP(scif0_data),
4524 SH_PFC_PIN_GROUP(scif0_data_b),
4525 SH_PFC_PIN_GROUP(scif0_data_c),
4526 SH_PFC_PIN_GROUP(scif0_data_d),
4527 SH_PFC_PIN_GROUP(scif0_data_e),
4528 SH_PFC_PIN_GROUP(scif1_data),
4529 SH_PFC_PIN_GROUP(scif1_data_b),
4530 SH_PFC_PIN_GROUP(scif1_clk_b),
4531 SH_PFC_PIN_GROUP(scif1_data_c),
4532 SH_PFC_PIN_GROUP(scif1_data_d),
4533 SH_PFC_PIN_GROUP(scif2_data),
4534 SH_PFC_PIN_GROUP(scif2_data_b),
4535 SH_PFC_PIN_GROUP(scif2_clk_b),
4536 SH_PFC_PIN_GROUP(scif2_data_c),
4537 SH_PFC_PIN_GROUP(scif2_data_e),
4538 SH_PFC_PIN_GROUP(scif3_data),
4539 SH_PFC_PIN_GROUP(scif3_clk),
4540 SH_PFC_PIN_GROUP(scif3_data_b),
4541 SH_PFC_PIN_GROUP(scif3_clk_b),
4542 SH_PFC_PIN_GROUP(scif3_data_c),
4543 SH_PFC_PIN_GROUP(scif3_data_d),
4544 SH_PFC_PIN_GROUP(scif4_data),
4545 SH_PFC_PIN_GROUP(scif4_data_b),
4546 SH_PFC_PIN_GROUP(scif4_data_c),
4547 SH_PFC_PIN_GROUP(scif5_data),
4548 SH_PFC_PIN_GROUP(scif5_data_b),
4549 SH_PFC_PIN_GROUP(scifa0_data),
4550 SH_PFC_PIN_GROUP(scifa0_data_b),
4551 SH_PFC_PIN_GROUP(scifa1_data),
4552 SH_PFC_PIN_GROUP(scifa1_clk),
4553 SH_PFC_PIN_GROUP(scifa1_data_b),
4554 SH_PFC_PIN_GROUP(scifa1_clk_b),
4555 SH_PFC_PIN_GROUP(scifa1_data_c),
4556 SH_PFC_PIN_GROUP(scifa2_data),
4557 SH_PFC_PIN_GROUP(scifa2_clk),
4558 SH_PFC_PIN_GROUP(scifa2_data_b),
4559 SH_PFC_PIN_GROUP(scifa3_data),
4560 SH_PFC_PIN_GROUP(scifa3_clk),
4561 SH_PFC_PIN_GROUP(scifa3_data_b),
4562 SH_PFC_PIN_GROUP(scifa3_clk_b),
4563 SH_PFC_PIN_GROUP(scifa3_data_c),
4564 SH_PFC_PIN_GROUP(scifa3_clk_c),
4565 SH_PFC_PIN_GROUP(scifa4_data),
4566 SH_PFC_PIN_GROUP(scifa4_data_b),
4567 SH_PFC_PIN_GROUP(scifa4_data_c),
4568 SH_PFC_PIN_GROUP(scifa5_data),
4569 SH_PFC_PIN_GROUP(scifa5_data_b),
4570 SH_PFC_PIN_GROUP(scifa5_data_c),
4571 SH_PFC_PIN_GROUP(scifb0_data),
4572 SH_PFC_PIN_GROUP(scifb0_clk),
4573 SH_PFC_PIN_GROUP(scifb0_ctrl),
4574 SH_PFC_PIN_GROUP(scifb0_data_b),
4575 SH_PFC_PIN_GROUP(scifb0_clk_b),
4576 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4577 SH_PFC_PIN_GROUP(scifb0_data_c),
4578 SH_PFC_PIN_GROUP(scifb0_clk_c),
4579 SH_PFC_PIN_GROUP(scifb0_data_d),
4580 SH_PFC_PIN_GROUP(scifb0_clk_d),
4581 SH_PFC_PIN_GROUP(scifb1_data),
4582 SH_PFC_PIN_GROUP(scifb1_clk),
4583 SH_PFC_PIN_GROUP(scifb1_ctrl),
4584 SH_PFC_PIN_GROUP(scifb1_data_b),
4585 SH_PFC_PIN_GROUP(scifb1_clk_b),
4586 SH_PFC_PIN_GROUP(scifb1_data_c),
4587 SH_PFC_PIN_GROUP(scifb1_clk_c),
4588 SH_PFC_PIN_GROUP(scifb1_data_d),
4589 SH_PFC_PIN_GROUP(scifb2_data),
4590 SH_PFC_PIN_GROUP(scifb2_clk),
4591 SH_PFC_PIN_GROUP(scifb2_ctrl),
4592 SH_PFC_PIN_GROUP(scifb2_data_b),
4593 SH_PFC_PIN_GROUP(scifb2_clk_b),
4594 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4595 SH_PFC_PIN_GROUP(scifb2_data_c),
4596 SH_PFC_PIN_GROUP(scifb2_clk_c),
4597 SH_PFC_PIN_GROUP(scifb2_data_d),
4598 SH_PFC_PIN_GROUP(scif_clk),
4599 SH_PFC_PIN_GROUP(scif_clk_b),
4600 SH_PFC_PIN_GROUP(sdhi0_data1),
4601 SH_PFC_PIN_GROUP(sdhi0_data4),
4602 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4603 SH_PFC_PIN_GROUP(sdhi0_cd),
4604 SH_PFC_PIN_GROUP(sdhi0_wp),
4605 SH_PFC_PIN_GROUP(sdhi1_data1),
4606 SH_PFC_PIN_GROUP(sdhi1_data4),
4607 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4608 SH_PFC_PIN_GROUP(sdhi1_cd),
4609 SH_PFC_PIN_GROUP(sdhi1_wp),
4610 SH_PFC_PIN_GROUP(sdhi2_data1),
4611 SH_PFC_PIN_GROUP(sdhi2_data4),
4612 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4613 SH_PFC_PIN_GROUP(sdhi2_cd),
4614 SH_PFC_PIN_GROUP(sdhi2_wp),
4615 SH_PFC_PIN_GROUP(ssi0_data),
4616 SH_PFC_PIN_GROUP(ssi0_data_b),
4617 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4618 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4619 SH_PFC_PIN_GROUP(ssi1_data),
4620 SH_PFC_PIN_GROUP(ssi1_data_b),
4621 SH_PFC_PIN_GROUP(ssi1_ctrl),
4622 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4623 SH_PFC_PIN_GROUP(ssi2_data),
4624 SH_PFC_PIN_GROUP(ssi2_ctrl),
4625 SH_PFC_PIN_GROUP(ssi3_data),
4626 SH_PFC_PIN_GROUP(ssi34_ctrl),
4627 SH_PFC_PIN_GROUP(ssi4_data),
4628 SH_PFC_PIN_GROUP(ssi4_ctrl),
4629 SH_PFC_PIN_GROUP(ssi5_data),
4630 SH_PFC_PIN_GROUP(ssi5_ctrl),
4631 SH_PFC_PIN_GROUP(ssi6_data),
4632 SH_PFC_PIN_GROUP(ssi6_ctrl),
4633 SH_PFC_PIN_GROUP(ssi7_data),
4634 SH_PFC_PIN_GROUP(ssi7_data_b),
4635 SH_PFC_PIN_GROUP(ssi78_ctrl),
4636 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4637 SH_PFC_PIN_GROUP(ssi8_data),
4638 SH_PFC_PIN_GROUP(ssi8_data_b),
4639 SH_PFC_PIN_GROUP(ssi9_data),
4640 SH_PFC_PIN_GROUP(ssi9_data_b),
4641 SH_PFC_PIN_GROUP(ssi9_ctrl),
4642 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4643 SH_PFC_PIN_GROUP(usb0),
4644 SH_PFC_PIN_GROUP(usb1),
4645 VIN_DATA_PIN_GROUP(vin0_data, 24),
4646 VIN_DATA_PIN_GROUP(vin0_data, 20),
4647 SH_PFC_PIN_GROUP(vin0_data18),
4648 VIN_DATA_PIN_GROUP(vin0_data, 16),
4649 VIN_DATA_PIN_GROUP(vin0_data, 12),
4650 VIN_DATA_PIN_GROUP(vin0_data, 10),
4651 VIN_DATA_PIN_GROUP(vin0_data, 8),
4652 SH_PFC_PIN_GROUP(vin0_sync),
4653 SH_PFC_PIN_GROUP(vin0_field),
4654 SH_PFC_PIN_GROUP(vin0_clkenb),
4655 SH_PFC_PIN_GROUP(vin0_clk),
4656 SH_PFC_PIN_GROUP(vin1_data8),
4657 SH_PFC_PIN_GROUP(vin1_sync),
4658 SH_PFC_PIN_GROUP(vin1_field),
4659 SH_PFC_PIN_GROUP(vin1_clkenb),
4660 SH_PFC_PIN_GROUP(vin1_clk),
4661 VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4662 VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4663 SH_PFC_PIN_GROUP(vin1_b_data18),
4664 VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4665 VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4666 VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4667 VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4668 SH_PFC_PIN_GROUP(vin1_b_sync),
4669 SH_PFC_PIN_GROUP(vin1_b_field),
4670 SH_PFC_PIN_GROUP(vin1_b_clkenb),
4671 SH_PFC_PIN_GROUP(vin1_b_clk),
4672 SH_PFC_PIN_GROUP(vin2_data8),
4673 SH_PFC_PIN_GROUP(vin2_sync),
4674 SH_PFC_PIN_GROUP(vin2_field),
4675 SH_PFC_PIN_GROUP(vin2_clkenb),
4676 SH_PFC_PIN_GROUP(vin2_clk),
4677};
4678
4679static const char * const audio_clk_groups[] = {
4680 "audio_clk_a",
4681 "audio_clk_b",
4682 "audio_clk_b_b",
4683 "audio_clk_c",
4684 "audio_clkout",
4685};
4686
4687static const char * const avb_groups[] = {
4688 "avb_link",
4689 "avb_magic",
4690 "avb_phy_int",
4691 "avb_mdio",
4692 "avb_mii",
4693 "avb_gmii",
4694};
4695
4696static const char * const can0_groups[] = {
4697 "can0_data",
4698 "can0_data_b",
4699 "can0_data_c",
4700 "can0_data_d",
4701 "can0_data_e",
4702 "can0_data_f",
4703 "can_clk",
4704 "can_clk_b",
4705 "can_clk_c",
4706 "can_clk_d",
4707};
4708
4709static const char * const can1_groups[] = {
4710 "can1_data",
4711 "can1_data_b",
4712 "can1_data_c",
4713 "can1_data_d",
4714 "can_clk",
4715 "can_clk_b",
4716 "can_clk_c",
4717 "can_clk_d",
4718};
4719
4720static const char * const du_groups[] = {
4721 "du_rgb666",
4722 "du_rgb888",
4723 "du_clk_out_0",
4724 "du_clk_out_1",
4725 "du_sync",
4726 "du_oddf",
4727 "du_cde",
4728 "du_disp",
4729};
4730
4731static const char * const du0_groups[] = {
4732 "du0_clk_in",
4733};
4734
4735static const char * const du1_groups[] = {
4736 "du1_clk_in",
4737 "du1_clk_in_b",
4738 "du1_clk_in_c",
4739};
4740
4741static const char * const eth_groups[] = {
4742 "eth_link",
4743 "eth_magic",
4744 "eth_mdio",
4745 "eth_rmii",
4746};
4747
4748static const char * const hscif0_groups[] = {
4749 "hscif0_data",
4750 "hscif0_clk",
4751 "hscif0_ctrl",
4752 "hscif0_data_b",
4753 "hscif0_ctrl_b",
4754 "hscif0_data_c",
4755 "hscif0_clk_c",
4756};
4757
4758static const char * const hscif1_groups[] = {
4759 "hscif1_data",
4760 "hscif1_clk",
4761 "hscif1_ctrl",
4762 "hscif1_data_b",
4763 "hscif1_data_c",
4764 "hscif1_clk_c",
4765 "hscif1_ctrl_c",
4766 "hscif1_data_d",
4767 "hscif1_data_e",
4768 "hscif1_clk_e",
4769 "hscif1_ctrl_e",
4770};
4771
4772static const char * const hscif2_groups[] = {
4773 "hscif2_data",
4774 "hscif2_clk",
4775 "hscif2_ctrl",
4776 "hscif2_data_b",
4777 "hscif2_ctrl_b",
4778 "hscif2_data_c",
4779 "hscif2_clk_c",
4780 "hscif2_data_d",
4781};
4782
4783static const char * const i2c0_groups[] = {
4784 "i2c0",
4785 "i2c0_b",
4786 "i2c0_c",
4787};
4788
4789static const char * const i2c1_groups[] = {
4790 "i2c1",
4791 "i2c1_b",
4792 "i2c1_c",
4793 "i2c1_d",
4794 "i2c1_e",
4795};
4796
4797static const char * const i2c2_groups[] = {
4798 "i2c2",
4799 "i2c2_b",
4800 "i2c2_c",
4801 "i2c2_d",
4802};
4803
4804static const char * const i2c3_groups[] = {
4805 "i2c3",
4806 "i2c3_b",
4807 "i2c3_c",
4808 "i2c3_d",
4809};
4810
4811static const char * const i2c4_groups[] = {
4812 "i2c4",
4813 "i2c4_b",
4814 "i2c4_c",
4815};
4816
4817static const char * const i2c7_groups[] = {
4818 "i2c7",
4819 "i2c7_b",
4820 "i2c7_c",
4821};
4822
4823static const char * const i2c8_groups[] = {
4824 "i2c8",
4825 "i2c8_b",
4826 "i2c8_c",
4827};
4828
4829static const char * const intc_groups[] = {
4830 "intc_irq0",
4831 "intc_irq1",
4832 "intc_irq2",
4833 "intc_irq3",
4834};
4835
4836static const char * const mlb_groups[] = {
4837 "mlb_3pin",
4838};
4839
4840static const char * const mmc_groups[] = {
4841 "mmc_data1",
4842 "mmc_data4",
4843 "mmc_data8",
4844 "mmc_ctrl",
4845};
4846
4847static const char * const msiof0_groups[] = {
4848 "msiof0_clk",
4849 "msiof0_sync",
4850 "msiof0_ss1",
4851 "msiof0_ss2",
4852 "msiof0_rx",
4853 "msiof0_tx",
4854 "msiof0_clk_b",
4855 "msiof0_sync_b",
4856 "msiof0_ss1_b",
4857 "msiof0_ss2_b",
4858 "msiof0_rx_b",
4859 "msiof0_tx_b",
4860 "msiof0_clk_c",
4861 "msiof0_sync_c",
4862 "msiof0_ss1_c",
4863 "msiof0_ss2_c",
4864 "msiof0_rx_c",
4865 "msiof0_tx_c",
4866};
4867
4868static const char * const msiof1_groups[] = {
4869 "msiof1_clk",
4870 "msiof1_sync",
4871 "msiof1_ss1",
4872 "msiof1_ss2",
4873 "msiof1_rx",
4874 "msiof1_tx",
4875 "msiof1_clk_b",
4876 "msiof1_sync_b",
4877 "msiof1_ss1_b",
4878 "msiof1_ss2_b",
4879 "msiof1_rx_b",
4880 "msiof1_tx_b",
4881 "msiof1_clk_c",
4882 "msiof1_sync_c",
4883 "msiof1_rx_c",
4884 "msiof1_tx_c",
4885 "msiof1_clk_d",
4886 "msiof1_sync_d",
4887 "msiof1_ss1_d",
4888 "msiof1_rx_d",
4889 "msiof1_tx_d",
4890 "msiof1_clk_e",
4891 "msiof1_sync_e",
4892 "msiof1_rx_e",
4893 "msiof1_tx_e",
4894};
4895
4896static const char * const msiof2_groups[] = {
4897 "msiof2_clk",
4898 "msiof2_sync",
4899 "msiof2_ss1",
4900 "msiof2_ss2",
4901 "msiof2_rx",
4902 "msiof2_tx",
4903 "msiof2_clk_b",
4904 "msiof2_sync_b",
4905 "msiof2_ss1_b",
4906 "msiof2_ss2_b",
4907 "msiof2_rx_b",
4908 "msiof2_tx_b",
4909 "msiof2_clk_c",
4910 "msiof2_sync_c",
4911 "msiof2_rx_c",
4912 "msiof2_tx_c",
4913 "msiof2_clk_d",
4914 "msiof2_sync_d",
4915 "msiof2_ss1_d",
4916 "msiof2_ss2_d",
4917 "msiof2_rx_d",
4918 "msiof2_tx_d",
4919 "msiof2_clk_e",
4920 "msiof2_sync_e",
4921 "msiof2_rx_e",
4922 "msiof2_tx_e",
4923};
4924
4925static const char * const pwm0_groups[] = {
4926 "pwm0",
4927 "pwm0_b",
4928};
4929
4930static const char * const pwm1_groups[] = {
4931 "pwm1",
4932 "pwm1_b",
4933};
4934
4935static const char * const pwm2_groups[] = {
4936 "pwm2",
4937 "pwm2_b",
4938};
4939
4940static const char * const pwm3_groups[] = {
4941 "pwm3",
4942};
4943
4944static const char * const pwm4_groups[] = {
4945 "pwm4",
4946 "pwm4_b",
4947};
4948
4949static const char * const pwm5_groups[] = {
4950 "pwm5",
4951 "pwm5_b",
4952};
4953
4954static const char * const pwm6_groups[] = {
4955 "pwm6",
4956};
4957
4958static const char * const qspi_groups[] = {
4959 "qspi_ctrl",
4960 "qspi_data2",
4961 "qspi_data4",
4962 "qspi_ctrl_b",
4963 "qspi_data2_b",
4964 "qspi_data4_b",
4965};
4966
4967static const char * const scif0_groups[] = {
4968 "scif0_data",
4969 "scif0_data_b",
4970 "scif0_data_c",
4971 "scif0_data_d",
4972 "scif0_data_e",
4973};
4974
4975static const char * const scif1_groups[] = {
4976 "scif1_data",
4977 "scif1_data_b",
4978 "scif1_clk_b",
4979 "scif1_data_c",
4980 "scif1_data_d",
4981};
4982
4983static const char * const scif2_groups[] = {
4984 "scif2_data",
4985 "scif2_data_b",
4986 "scif2_clk_b",
4987 "scif2_data_c",
4988 "scif2_data_e",
4989};
4990static const char * const scif3_groups[] = {
4991 "scif3_data",
4992 "scif3_clk",
4993 "scif3_data_b",
4994 "scif3_clk_b",
4995 "scif3_data_c",
4996 "scif3_data_d",
4997};
4998static const char * const scif4_groups[] = {
4999 "scif4_data",
5000 "scif4_data_b",
5001 "scif4_data_c",
5002};
5003static const char * const scif5_groups[] = {
5004 "scif5_data",
5005 "scif5_data_b",
5006};
5007static const char * const scifa0_groups[] = {
5008 "scifa0_data",
5009 "scifa0_data_b",
5010};
5011static const char * const scifa1_groups[] = {
5012 "scifa1_data",
5013 "scifa1_clk",
5014 "scifa1_data_b",
5015 "scifa1_clk_b",
5016 "scifa1_data_c",
5017};
5018static const char * const scifa2_groups[] = {
5019 "scifa2_data",
5020 "scifa2_clk",
5021 "scifa2_data_b",
5022};
5023static const char * const scifa3_groups[] = {
5024 "scifa3_data",
5025 "scifa3_clk",
5026 "scifa3_data_b",
5027 "scifa3_clk_b",
5028 "scifa3_data_c",
5029 "scifa3_clk_c",
5030};
5031static const char * const scifa4_groups[] = {
5032 "scifa4_data",
5033 "scifa4_data_b",
5034 "scifa4_data_c",
5035};
5036static const char * const scifa5_groups[] = {
5037 "scifa5_data",
5038 "scifa5_data_b",
5039 "scifa5_data_c",
5040};
5041static const char * const scifb0_groups[] = {
5042 "scifb0_data",
5043 "scifb0_clk",
5044 "scifb0_ctrl",
5045 "scifb0_data_b",
5046 "scifb0_clk_b",
5047 "scifb0_ctrl_b",
5048 "scifb0_data_c",
5049 "scifb0_clk_c",
5050 "scifb0_data_d",
5051 "scifb0_clk_d",
5052};
5053static const char * const scifb1_groups[] = {
5054 "scifb1_data",
5055 "scifb1_clk",
5056 "scifb1_ctrl",
5057 "scifb1_data_b",
5058 "scifb1_clk_b",
5059 "scifb1_data_c",
5060 "scifb1_clk_c",
5061 "scifb1_data_d",
5062};
5063static const char * const scifb2_groups[] = {
5064 "scifb2_data",
5065 "scifb2_clk",
5066 "scifb2_ctrl",
5067 "scifb2_data_b",
5068 "scifb2_clk_b",
5069 "scifb2_ctrl_b",
5070 "scifb0_data_c",
5071 "scifb2_clk_c",
5072 "scifb2_data_d",
5073};
5074
5075static const char * const scif_clk_groups[] = {
5076 "scif_clk",
5077 "scif_clk_b",
5078};
5079
5080static const char * const sdhi0_groups[] = {
5081 "sdhi0_data1",
5082 "sdhi0_data4",
5083 "sdhi0_ctrl",
5084 "sdhi0_cd",
5085 "sdhi0_wp",
5086};
5087
5088static const char * const sdhi1_groups[] = {
5089 "sdhi1_data1",
5090 "sdhi1_data4",
5091 "sdhi1_ctrl",
5092 "sdhi1_cd",
5093 "sdhi1_wp",
5094};
5095
5096static const char * const sdhi2_groups[] = {
5097 "sdhi2_data1",
5098 "sdhi2_data4",
5099 "sdhi2_ctrl",
5100 "sdhi2_cd",
5101 "sdhi2_wp",
5102};
5103
5104static const char * const ssi_groups[] = {
5105 "ssi0_data",
5106 "ssi0_data_b",
5107 "ssi0129_ctrl",
5108 "ssi0129_ctrl_b",
5109 "ssi1_data",
5110 "ssi1_data_b",
5111 "ssi1_ctrl",
5112 "ssi1_ctrl_b",
5113 "ssi2_data",
5114 "ssi2_ctrl",
5115 "ssi3_data",
5116 "ssi34_ctrl",
5117 "ssi4_data",
5118 "ssi4_ctrl",
5119 "ssi5_data",
5120 "ssi5_ctrl",
5121 "ssi6_data",
5122 "ssi6_ctrl",
5123 "ssi7_data",
5124 "ssi7_data_b",
5125 "ssi78_ctrl",
5126 "ssi78_ctrl_b",
5127 "ssi8_data",
5128 "ssi8_data_b",
5129 "ssi9_data",
5130 "ssi9_data_b",
5131 "ssi9_ctrl",
5132 "ssi9_ctrl_b",
5133};
5134
5135static const char * const usb0_groups[] = {
5136 "usb0",
5137};
5138static const char * const usb1_groups[] = {
5139 "usb1",
5140};
5141
5142static const char * const vin0_groups[] = {
5143 "vin0_data24",
5144 "vin0_data20",
5145 "vin0_data18",
5146 "vin0_data16",
5147 "vin0_data12",
5148 "vin0_data10",
5149 "vin0_data8",
5150 "vin0_sync",
5151 "vin0_field",
5152 "vin0_clkenb",
5153 "vin0_clk",
5154};
5155
5156static const char * const vin1_groups[] = {
5157 "vin1_data8",
5158 "vin1_sync",
5159 "vin1_field",
5160 "vin1_clkenb",
5161 "vin1_clk",
5162 "vin1_b_data24",
5163 "vin1_b_data20",
5164 "vin1_b_data18",
5165 "vin1_b_data16",
5166 "vin1_b_data12",
5167 "vin1_b_data10",
5168 "vin1_b_data8",
5169 "vin1_b_sync",
5170 "vin1_b_field",
5171 "vin1_b_clkenb",
5172 "vin1_b_clk",
5173};
5174
5175static const char * const vin2_groups[] = {
5176 "vin2_data8",
5177 "vin2_sync",
5178 "vin2_field",
5179 "vin2_clkenb",
5180 "vin2_clk",
5181};
5182
5183static const struct sh_pfc_function pinmux_functions[] = {
5184 SH_PFC_FUNCTION(audio_clk),
5185 SH_PFC_FUNCTION(avb),
5186 SH_PFC_FUNCTION(can0),
5187 SH_PFC_FUNCTION(can1),
5188 SH_PFC_FUNCTION(du),
5189 SH_PFC_FUNCTION(du0),
5190 SH_PFC_FUNCTION(du1),
5191 SH_PFC_FUNCTION(eth),
5192 SH_PFC_FUNCTION(hscif0),
5193 SH_PFC_FUNCTION(hscif1),
5194 SH_PFC_FUNCTION(hscif2),
5195 SH_PFC_FUNCTION(i2c0),
5196 SH_PFC_FUNCTION(i2c1),
5197 SH_PFC_FUNCTION(i2c2),
5198 SH_PFC_FUNCTION(i2c3),
5199 SH_PFC_FUNCTION(i2c4),
5200 SH_PFC_FUNCTION(i2c7),
5201 SH_PFC_FUNCTION(i2c8),
5202 SH_PFC_FUNCTION(intc),
5203 SH_PFC_FUNCTION(mlb),
5204 SH_PFC_FUNCTION(mmc),
5205 SH_PFC_FUNCTION(msiof0),
5206 SH_PFC_FUNCTION(msiof1),
5207 SH_PFC_FUNCTION(msiof2),
5208 SH_PFC_FUNCTION(pwm0),
5209 SH_PFC_FUNCTION(pwm1),
5210 SH_PFC_FUNCTION(pwm2),
5211 SH_PFC_FUNCTION(pwm3),
5212 SH_PFC_FUNCTION(pwm4),
5213 SH_PFC_FUNCTION(pwm5),
5214 SH_PFC_FUNCTION(pwm6),
5215 SH_PFC_FUNCTION(qspi),
5216 SH_PFC_FUNCTION(scif0),
5217 SH_PFC_FUNCTION(scif1),
5218 SH_PFC_FUNCTION(scif2),
5219 SH_PFC_FUNCTION(scif3),
5220 SH_PFC_FUNCTION(scif4),
5221 SH_PFC_FUNCTION(scif5),
5222 SH_PFC_FUNCTION(scifa0),
5223 SH_PFC_FUNCTION(scifa1),
5224 SH_PFC_FUNCTION(scifa2),
5225 SH_PFC_FUNCTION(scifa3),
5226 SH_PFC_FUNCTION(scifa4),
5227 SH_PFC_FUNCTION(scifa5),
5228 SH_PFC_FUNCTION(scifb0),
5229 SH_PFC_FUNCTION(scifb1),
5230 SH_PFC_FUNCTION(scifb2),
5231 SH_PFC_FUNCTION(scif_clk),
5232 SH_PFC_FUNCTION(sdhi0),
5233 SH_PFC_FUNCTION(sdhi1),
5234 SH_PFC_FUNCTION(sdhi2),
5235 SH_PFC_FUNCTION(ssi),
5236 SH_PFC_FUNCTION(usb0),
5237 SH_PFC_FUNCTION(usb1),
5238 SH_PFC_FUNCTION(vin0),
5239 SH_PFC_FUNCTION(vin1),
5240 SH_PFC_FUNCTION(vin2),
5241};
5242
5243static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5244 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5245 GP_0_31_FN, FN_IP1_22_20,
5246 GP_0_30_FN, FN_IP1_19_17,
5247 GP_0_29_FN, FN_IP1_16_14,
5248 GP_0_28_FN, FN_IP1_13_11,
5249 GP_0_27_FN, FN_IP1_10_8,
5250 GP_0_26_FN, FN_IP1_7_6,
5251 GP_0_25_FN, FN_IP1_5_4,
5252 GP_0_24_FN, FN_IP1_3_2,
5253 GP_0_23_FN, FN_IP1_1_0,
5254 GP_0_22_FN, FN_IP0_30_29,
5255 GP_0_21_FN, FN_IP0_28_27,
5256 GP_0_20_FN, FN_IP0_26_25,
5257 GP_0_19_FN, FN_IP0_24_23,
5258 GP_0_18_FN, FN_IP0_22_21,
5259 GP_0_17_FN, FN_IP0_20_19,
5260 GP_0_16_FN, FN_IP0_18_16,
5261 GP_0_15_FN, FN_IP0_15,
5262 GP_0_14_FN, FN_IP0_14,
5263 GP_0_13_FN, FN_IP0_13,
5264 GP_0_12_FN, FN_IP0_12,
5265 GP_0_11_FN, FN_IP0_11,
5266 GP_0_10_FN, FN_IP0_10,
5267 GP_0_9_FN, FN_IP0_9,
5268 GP_0_8_FN, FN_IP0_8,
5269 GP_0_7_FN, FN_IP0_7,
5270 GP_0_6_FN, FN_IP0_6,
5271 GP_0_5_FN, FN_IP0_5,
5272 GP_0_4_FN, FN_IP0_4,
5273 GP_0_3_FN, FN_IP0_3,
5274 GP_0_2_FN, FN_IP0_2,
5275 GP_0_1_FN, FN_IP0_1,
5276 GP_0_0_FN, FN_IP0_0, }
5277 },
5278 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5279 0, 0,
5280 0, 0,
5281 0, 0,
5282 0, 0,
5283 0, 0,
5284 0, 0,
5285 GP_1_25_FN, FN_IP3_21_20,
5286 GP_1_24_FN, FN_IP3_19_18,
5287 GP_1_23_FN, FN_IP3_17_16,
5288 GP_1_22_FN, FN_IP3_15_14,
5289 GP_1_21_FN, FN_IP3_13_12,
5290 GP_1_20_FN, FN_IP3_11_9,
5291 GP_1_19_FN, FN_RD_N,
5292 GP_1_18_FN, FN_IP3_8_6,
5293 GP_1_17_FN, FN_IP3_5_3,
5294 GP_1_16_FN, FN_IP3_2_0,
5295 GP_1_15_FN, FN_IP2_29_27,
5296 GP_1_14_FN, FN_IP2_26_25,
5297 GP_1_13_FN, FN_IP2_24_23,
5298 GP_1_12_FN, FN_EX_CS0_N,
5299 GP_1_11_FN, FN_IP2_22_21,
5300 GP_1_10_FN, FN_IP2_20_19,
5301 GP_1_9_FN, FN_IP2_18_16,
5302 GP_1_8_FN, FN_IP2_15_13,
5303 GP_1_7_FN, FN_IP2_12_10,
5304 GP_1_6_FN, FN_IP2_9_7,
5305 GP_1_5_FN, FN_IP2_6_5,
5306 GP_1_4_FN, FN_IP2_4_3,
5307 GP_1_3_FN, FN_IP2_2_0,
5308 GP_1_2_FN, FN_IP1_31_29,
5309 GP_1_1_FN, FN_IP1_28_26,
5310 GP_1_0_FN, FN_IP1_25_23, }
5311 },
5312 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5313 GP_2_31_FN, FN_IP6_7_6,
5314 GP_2_30_FN, FN_IP6_5_3,
5315 GP_2_29_FN, FN_IP6_2_0,
5316 GP_2_28_FN, FN_AUDIO_CLKA,
5317 GP_2_27_FN, FN_IP5_31_29,
5318 GP_2_26_FN, FN_IP5_28_26,
5319 GP_2_25_FN, FN_IP5_25_24,
5320 GP_2_24_FN, FN_IP5_23_22,
5321 GP_2_23_FN, FN_IP5_21_20,
5322 GP_2_22_FN, FN_IP5_19_17,
5323 GP_2_21_FN, FN_IP5_16_15,
5324 GP_2_20_FN, FN_IP5_14_12,
5325 GP_2_19_FN, FN_IP5_11_9,
5326 GP_2_18_FN, FN_IP5_8_6,
5327 GP_2_17_FN, FN_IP5_5_3,
5328 GP_2_16_FN, FN_IP5_2_0,
5329 GP_2_15_FN, FN_IP4_30_28,
5330 GP_2_14_FN, FN_IP4_27_26,
5331 GP_2_13_FN, FN_IP4_25_24,
5332 GP_2_12_FN, FN_IP4_23_22,
5333 GP_2_11_FN, FN_IP4_21,
5334 GP_2_10_FN, FN_IP4_20,
5335 GP_2_9_FN, FN_IP4_19,
5336 GP_2_8_FN, FN_IP4_18_16,
5337 GP_2_7_FN, FN_IP4_15_13,
5338 GP_2_6_FN, FN_IP4_12_10,
5339 GP_2_5_FN, FN_IP4_9_8,
5340 GP_2_4_FN, FN_IP4_7_5,
5341 GP_2_3_FN, FN_IP4_4_2,
5342 GP_2_2_FN, FN_IP4_1_0,
5343 GP_2_1_FN, FN_IP3_30_28,
5344 GP_2_0_FN, FN_IP3_27_25 }
5345 },
5346 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5347 GP_3_31_FN, FN_IP9_18_17,
5348 GP_3_30_FN, FN_IP9_16,
5349 GP_3_29_FN, FN_IP9_15_13,
5350 GP_3_28_FN, FN_IP9_12,
5351 GP_3_27_FN, FN_IP9_11,
5352 GP_3_26_FN, FN_IP9_10_8,
5353 GP_3_25_FN, FN_IP9_7,
5354 GP_3_24_FN, FN_IP9_6,
5355 GP_3_23_FN, FN_IP9_5_3,
5356 GP_3_22_FN, FN_IP9_2_0,
5357 GP_3_21_FN, FN_IP8_30_28,
5358 GP_3_20_FN, FN_IP8_27_26,
5359 GP_3_19_FN, FN_IP8_25_24,
5360 GP_3_18_FN, FN_IP8_23_21,
5361 GP_3_17_FN, FN_IP8_20_18,
5362 GP_3_16_FN, FN_IP8_17_15,
5363 GP_3_15_FN, FN_IP8_14_12,
5364 GP_3_14_FN, FN_IP8_11_9,
5365 GP_3_13_FN, FN_IP8_8_6,
5366 GP_3_12_FN, FN_IP8_5_3,
5367 GP_3_11_FN, FN_IP8_2_0,
5368 GP_3_10_FN, FN_IP7_29_27,
5369 GP_3_9_FN, FN_IP7_26_24,
5370 GP_3_8_FN, FN_IP7_23_21,
5371 GP_3_7_FN, FN_IP7_20_19,
5372 GP_3_6_FN, FN_IP7_18_17,
5373 GP_3_5_FN, FN_IP7_16_15,
5374 GP_3_4_FN, FN_IP7_14_13,
5375 GP_3_3_FN, FN_IP7_12_11,
5376 GP_3_2_FN, FN_IP7_10_9,
5377 GP_3_1_FN, FN_IP7_8_6,
5378 GP_3_0_FN, FN_IP7_5_3 }
5379 },
5380 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5381 GP_4_31_FN, FN_IP15_5_4,
5382 GP_4_30_FN, FN_IP15_3_2,
5383 GP_4_29_FN, FN_IP15_1_0,
5384 GP_4_28_FN, FN_IP11_8_6,
5385 GP_4_27_FN, FN_IP11_5_3,
5386 GP_4_26_FN, FN_IP11_2_0,
5387 GP_4_25_FN, FN_IP10_31_29,
5388 GP_4_24_FN, FN_IP10_28_27,
5389 GP_4_23_FN, FN_IP10_26_25,
5390 GP_4_22_FN, FN_IP10_24_22,
5391 GP_4_21_FN, FN_IP10_21_19,
5392 GP_4_20_FN, FN_IP10_18_17,
5393 GP_4_19_FN, FN_IP10_16_15,
5394 GP_4_18_FN, FN_IP10_14_12,
5395 GP_4_17_FN, FN_IP10_11_9,
5396 GP_4_16_FN, FN_IP10_8_6,
5397 GP_4_15_FN, FN_IP10_5_3,
5398 GP_4_14_FN, FN_IP10_2_0,
5399 GP_4_13_FN, FN_IP9_31_29,
5400 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5401 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5402 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5403 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5404 GP_4_8_FN, FN_IP9_28_27,
5405 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5406 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5407 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5408 GP_4_4_FN, FN_IP9_26_25,
5409 GP_4_3_FN, FN_IP9_24_23,
5410 GP_4_2_FN, FN_IP9_22_21,
5411 GP_4_1_FN, FN_IP9_20_19,
5412 GP_4_0_FN, FN_VI0_CLK }
5413 },
5414 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5415 GP_5_31_FN, FN_IP3_24_22,
5416 GP_5_30_FN, FN_IP13_9_7,
5417 GP_5_29_FN, FN_IP13_6_5,
5418 GP_5_28_FN, FN_IP13_4_3,
5419 GP_5_27_FN, FN_IP13_2_0,
5420 GP_5_26_FN, FN_IP12_29_27,
5421 GP_5_25_FN, FN_IP12_26_24,
5422 GP_5_24_FN, FN_IP12_23_22,
5423 GP_5_23_FN, FN_IP12_21_20,
5424 GP_5_22_FN, FN_IP12_19_18,
5425 GP_5_21_FN, FN_IP12_17_16,
5426 GP_5_20_FN, FN_IP12_15_13,
5427 GP_5_19_FN, FN_IP12_12_10,
5428 GP_5_18_FN, FN_IP12_9_7,
5429 GP_5_17_FN, FN_IP12_6_4,
5430 GP_5_16_FN, FN_IP12_3_2,
5431 GP_5_15_FN, FN_IP12_1_0,
5432 GP_5_14_FN, FN_IP11_31_30,
5433 GP_5_13_FN, FN_IP11_29_28,
5434 GP_5_12_FN, FN_IP11_27,
5435 GP_5_11_FN, FN_IP11_26,
5436 GP_5_10_FN, FN_IP11_25,
5437 GP_5_9_FN, FN_IP11_24,
5438 GP_5_8_FN, FN_IP11_23,
5439 GP_5_7_FN, FN_IP11_22,
5440 GP_5_6_FN, FN_IP11_21,
5441 GP_5_5_FN, FN_IP11_20,
5442 GP_5_4_FN, FN_IP11_19,
5443 GP_5_3_FN, FN_IP11_18_17,
5444 GP_5_2_FN, FN_IP11_16_15,
5445 GP_5_1_FN, FN_IP11_14_12,
5446 GP_5_0_FN, FN_IP11_11_9 }
5447 },
5448 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5449 GP_6_31_FN, FN_DU0_DOTCLKIN,
5450 GP_6_30_FN, FN_USB1_OVC,
5451 GP_6_29_FN, FN_IP14_31_29,
5452 GP_6_28_FN, FN_IP14_28_26,
5453 GP_6_27_FN, FN_IP14_25_23,
5454 GP_6_26_FN, FN_IP14_22_20,
5455 GP_6_25_FN, FN_IP14_19_17,
5456 GP_6_24_FN, FN_IP14_16_14,
5457 GP_6_23_FN, FN_IP14_13_11,
5458 GP_6_22_FN, FN_IP14_10_8,
5459 GP_6_21_FN, FN_IP14_7,
5460 GP_6_20_FN, FN_IP14_6,
5461 GP_6_19_FN, FN_IP14_5,
5462 GP_6_18_FN, FN_IP14_4,
5463 GP_6_17_FN, FN_IP14_3,
5464 GP_6_16_FN, FN_IP14_2,
5465 GP_6_15_FN, FN_IP14_1_0,
5466 GP_6_14_FN, FN_IP13_30_28,
5467 GP_6_13_FN, FN_IP13_27,
5468 GP_6_12_FN, FN_IP13_26,
5469 GP_6_11_FN, FN_IP13_25,
5470 GP_6_10_FN, FN_IP13_24_23,
5471 GP_6_9_FN, FN_IP13_22,
5472 GP_6_8_FN, FN_SD1_CLK,
5473 GP_6_7_FN, FN_IP13_21_19,
5474 GP_6_6_FN, FN_IP13_18_16,
5475 GP_6_5_FN, FN_IP13_15,
5476 GP_6_4_FN, FN_IP13_14,
5477 GP_6_3_FN, FN_IP13_13,
5478 GP_6_2_FN, FN_IP13_12,
5479 GP_6_1_FN, FN_IP13_11,
5480 GP_6_0_FN, FN_IP13_10 }
5481 },
5482 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5483 0, 0,
5484 0, 0,
5485 0, 0,
5486 0, 0,
5487 0, 0,
5488 0, 0,
5489 GP_7_25_FN, FN_USB1_PWEN,
5490 GP_7_24_FN, FN_USB0_OVC,
5491 GP_7_23_FN, FN_USB0_PWEN,
5492 GP_7_22_FN, FN_IP15_14_12,
5493 GP_7_21_FN, FN_IP15_11_9,
5494 GP_7_20_FN, FN_IP15_8_6,
5495 GP_7_19_FN, FN_IP7_2_0,
5496 GP_7_18_FN, FN_IP6_29_27,
5497 GP_7_17_FN, FN_IP6_26_24,
5498 GP_7_16_FN, FN_IP6_23_21,
5499 GP_7_15_FN, FN_IP6_20_19,
5500 GP_7_14_FN, FN_IP6_18_16,
5501 GP_7_13_FN, FN_IP6_15_14,
5502 GP_7_12_FN, FN_IP6_13_12,
5503 GP_7_11_FN, FN_IP6_11_10,
5504 GP_7_10_FN, FN_IP6_9_8,
5505 GP_7_9_FN, FN_IP16_11_10,
5506 GP_7_8_FN, FN_IP16_9_8,
5507 GP_7_7_FN, FN_IP16_7_6,
5508 GP_7_6_FN, FN_IP16_5_3,
5509 GP_7_5_FN, FN_IP16_2_0,
5510 GP_7_4_FN, FN_IP15_29_27,
5511 GP_7_3_FN, FN_IP15_26_24,
5512 GP_7_2_FN, FN_IP15_23_21,
5513 GP_7_1_FN, FN_IP15_20_18,
5514 GP_7_0_FN, FN_IP15_17_15 }
5515 },
5516 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5517 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5518 1, 1, 1, 1, 1, 1, 1, 1) {
5519 /* IP0_31 [1] */
5520 0, 0,
5521 /* IP0_30_29 [2] */
5522 FN_A6, FN_MSIOF1_SCK,
5523 0, 0,
5524 /* IP0_28_27 [2] */
5525 FN_A5, FN_MSIOF0_RXD_B,
5526 0, 0,
5527 /* IP0_26_25 [2] */
5528 FN_A4, FN_MSIOF0_TXD_B,
5529 0, 0,
5530 /* IP0_24_23 [2] */
5531 FN_A3, FN_MSIOF0_SS2_B,
5532 0, 0,
5533 /* IP0_22_21 [2] */
5534 FN_A2, FN_MSIOF0_SS1_B,
5535 0, 0,
5536 /* IP0_20_19 [2] */
5537 FN_A1, FN_MSIOF0_SYNC_B,
5538 0, 0,
5539 /* IP0_18_16 [3] */
5540 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
5541 0, 0, 0,
5542 /* IP0_15 [1] */
5543 FN_D15, 0,
5544 /* IP0_14 [1] */
5545 FN_D14, 0,
5546 /* IP0_13 [1] */
5547 FN_D13, 0,
5548 /* IP0_12 [1] */
5549 FN_D12, 0,
5550 /* IP0_11 [1] */
5551 FN_D11, 0,
5552 /* IP0_10 [1] */
5553 FN_D10, 0,
5554 /* IP0_9 [1] */
5555 FN_D9, 0,
5556 /* IP0_8 [1] */
5557 FN_D8, 0,
5558 /* IP0_7 [1] */
5559 FN_D7, 0,
5560 /* IP0_6 [1] */
5561 FN_D6, 0,
5562 /* IP0_5 [1] */
5563 FN_D5, 0,
5564 /* IP0_4 [1] */
5565 FN_D4, 0,
5566 /* IP0_3 [1] */
5567 FN_D3, 0,
5568 /* IP0_2 [1] */
5569 FN_D2, 0,
5570 /* IP0_1 [1] */
5571 FN_D1, 0,
5572 /* IP0_0 [1] */
5573 FN_D0, 0, }
5574 },
5575 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5576 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5577 /* IP1_31_29 [3] */
5578 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5579 0, 0, 0,
5580 /* IP1_28_26 [3] */
5581 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
5582 0, 0, 0, 0,
5583 /* IP1_25_23 [3] */
5584 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5585 0, 0, 0,
5586 /* IP1_22_20 [3] */
5587 FN_A15, FN_BPFCLK_C,
5588 0, 0, 0, 0, 0, 0,
5589 /* IP1_19_17 [3] */
5590 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5591 0, 0, 0,
5592 /* IP1_16_14 [3] */
5593 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5594 0, 0, 0, 0,
5595 /* IP1_13_11 [3] */
5596 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
5597 0, 0, 0, 0,
5598 /* IP1_10_8 [3] */
5599 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
5600 0, 0, 0, 0,
5601 /* IP1_7_6 [2] */
5602 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5603 /* IP1_5_4 [2] */
5604 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
5605 /* IP1_3_2 [2] */
5606 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
5607 /* IP1_1_0 [2] */
5608 FN_A7, FN_MSIOF1_SYNC,
5609 0, 0, }
5610 },
5611 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5612 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5613 /* IP2_31_20 [2] */
5614 0, 0, 0, 0,
5615 /* IP2_29_27 [3] */
5616 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5617 FN_ATAG0_N, 0, FN_EX_WAIT1,
5618 0, 0,
5619 /* IP2_26_25 [2] */
5620 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5621 /* IP2_24_23 [2] */
5622 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5623 /* IP2_22_21 [2] */
5624 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
5625 /* IP2_20_19 [2] */
5626 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
5627 /* IP2_18_16 [3] */
5628 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5629 0, 0,
5630 /* IP2_15_13 [3] */
5631 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5632 0, 0, 0,
5633 /* IP2_12_0 [3] */
5634 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5635 0, 0, 0,
5636 /* IP2_9_7 [3] */
5637 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5638 0, 0, 0,
5639 /* IP2_6_5 [2] */
5640 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5641 /* IP2_4_3 [2] */
5642 FN_A20, FN_SPCLK, 0, 0,
5643 /* IP2_2_0 [3] */
5644 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5645 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5646 },
5647 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5648 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5649 /* IP3_31 [1] */
5650 0, 0,
5651 /* IP3_30_28 [3] */
5652 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5653 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5654 0, 0, 0,
5655 /* IP3_27_25 [3] */
5656 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5657 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5658 0, 0, 0,
5659 /* IP3_24_22 [3] */
5660 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5661 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5662 /* IP3_21_20 [2] */
5663 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5664 /* IP3_19_18 [2] */
5665 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5666 /* IP3_17_16 [2] */
5667 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5668 /* IP3_15_14 [2] */
5669 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5670 /* IP3_13_12 [2] */
5671 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5672 /* IP3_11_9 [3] */
5673 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5674 0, 0, 0,
5675 /* IP3_8_6 [3] */
5676 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5677 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5678 /* IP3_5_3 [3] */
5679 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5680 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5681 /* IP3_2_0 [3] */
5682 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5683 0, 0, 0, }
5684 },
5685 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5686 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5687 /* IP4_31 [1] */
5688 0, 0,
5689 /* IP4_30_28 [3] */
5690 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5691 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5692 0, 0,
5693 /* IP4_27_26 [2] */
5694 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5695 /* IP4_25_24 [2] */
5696 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5697 /* IP4_23_22 [2] */
5698 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5699 /* IP4_21 [1] */
5700 FN_SSI_SDATA3, 0,
5701 /* IP4_20 [1] */
5702 FN_SSI_WS34, 0,
5703 /* IP4_19 [1] */
5704 FN_SSI_SCK34, 0,
5705 /* IP4_18_16 [3] */
5706 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5707 0, 0, 0, 0,
5708 /* IP4_15_13 [3] */
5709 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
5710 FN_GLO_Q1_D, FN_HCTS1_N_E,
5711 0, 0,
5712 /* IP4_12_10 [3] */
5713 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5714 0, 0, 0,
5715 /* IP4_9_8 [2] */
5716 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
5717 /* IP4_7_5 [3] */
5718 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
5719 0, 0, 0,
5720 /* IP4_4_2 [3] */
5721 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
5722 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5723 0, 0, 0,
5724 /* IP4_1_0 [2] */
5725 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
5726 },
5727 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5728 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5729 /* IP5_31_29 [3] */
5730 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5731 0, 0, 0, 0, 0,
5732 /* IP5_28_26 [3] */
5733 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5734 0, 0, 0, 0,
5735 /* IP5_25_24 [2] */
5736 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5737 /* IP5_23_22 [2] */
5738 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5739 /* IP5_21_20 [2] */
5740 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5741 /* IP5_19_17 [3] */
5742 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5743 0, 0, 0, 0,
5744 /* IP5_16_15 [2] */
5745 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5746 /* IP5_14_12 [3] */
5747 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5748 0, 0, 0, 0,
5749 /* IP5_11_9 [3] */
5750 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5751 0, 0, 0, 0,
5752 /* IP5_8_6 [3] */
5753 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5754 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5755 0, 0,
5756 /* IP5_5_3 [3] */
5757 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5758 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5759 0, 0,
5760 /* IP5_2_0 [3] */
5761 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5762 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5763 0, 0, }
5764 },
5765 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5766 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5767 /* IP6_31_30 [2] */
5768 0, 0, 0, 0,
5769 /* IP6_29_27 [3] */
5770 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5771 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5772 0, 0, 0,
5773 /* IP6_26_24 [3] */
5774 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5775 FN_GPS_CLK_C, FN_GPS_CLK_D,
5776 0, 0, 0,
5777 /* IP6_23_21 [3] */
5778 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5779 FN_SDA1_E, FN_MSIOF2_SYNC_E,
5780 0, 0, 0,
5781 /* IP6_20_19 [2] */
5782 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
5783 /* IP6_18_16 [3] */
5784 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
5785 0, 0, 0,
5786 /* IP6_15_14 [2] */
5787 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5788 /* IP6_13_12 [2] */
5789 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5790 /* IP6_11_10 [2] */
5791 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5792 /* IP6_9_8 [2] */
5793 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5794 /* IP6_7_6 [2] */
5795 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5796 /* IP6_5_3 [3] */
5797 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5798 FN_SCIFA2_RXD, FN_FMIN_E,
5799 0, 0,
5800 /* IP6_2_0 [3] */
5801 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5802 FN_SCIF_CLK, 0, FN_BPFCLK_E,
5803 0, 0, }
5804 },
5805 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5806 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5807 /* IP7_31_30 [2] */
5808 0, 0, 0, 0,
5809 /* IP7_29_27 [3] */
5810 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5811 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5812 0, 0,
5813 /* IP7_26_24 [3] */
5814 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5815 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5816 0, 0,
5817 /* IP7_23_21 [3] */
5818 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5819 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5820 0, 0,
5821 /* IP7_20_19 [2] */
5822 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5823 /* IP7_18_17 [2] */
5824 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5825 /* IP7_16_15 [2] */
5826 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5827 /* IP7_14_13 [2] */
5828 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5829 /* IP7_12_11 [2] */
5830 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5831 /* IP7_10_9 [2] */
5832 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5833 /* IP7_8_6 [3] */
5834 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5835 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5836 0, 0,
5837 /* IP7_5_3 [3] */
5838 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5839 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5840 0, 0,
5841 /* IP7_2_0 [3] */
5842 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5843 FN_SCIF_CLK_B, FN_GPS_MAG_D,
5844 0, 0, }
5845 },
5846 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5847 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5848 /* IP8_31 [1] */
5849 0, 0,
5850 /* IP8_30_28 [3] */
5851 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5852 0, 0, 0,
5853 /* IP8_27_26 [2] */
5854 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5855 /* IP8_25_24 [2] */
5856 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5857 /* IP8_23_21 [3] */
5858 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5859 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5860 0, 0,
5861 /* IP8_20_18 [3] */
5862 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
5863 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
5864 0, 0,
5865 /* IP8_17_15 [3] */
5866 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
5867 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
5868 0, 0,
5869 /* IP8_14_12 [3] */
5870 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
5871 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
5872 0, 0, 0,
5873 /* IP8_11_9 [3] */
5874 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
5875 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
5876 0, 0, 0,
5877 /* IP8_8_6 [3] */
5878 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
5879 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
5880 0, 0,
5881 /* IP8_5_3 [3] */
5882 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
5883 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
5884 0, 0,
5885 /* IP8_2_0 [3] */
5886 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
5887 0, 0, 0, }
5888 },
5889 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5890 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
5891 /* IP9_31_29 [3] */
5892 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
5893 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
5894 /* IP9_28_27 [2] */
5895 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
5896 /* IP9_26_25 [2] */
5897 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
5898 /* IP9_24_23 [2] */
5899 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
5900 /* IP9_22_21 [2] */
5901 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
5902 /* IP9_20_19 [2] */
5903 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
5904 /* IP9_18_17 [2] */
5905 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
5906 /* IP9_16 [1] */
5907 FN_DU1_DISP, FN_QPOLA,
5908 /* IP9_15_13 [3] */
5909 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
5910 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
5911 0, 0, 0,
5912 /* IP9_12 [1] */
5913 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
5914 /* IP9_11 [1] */
5915 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
5916 /* IP9_10_8 [3] */
5917 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
5918 FN_TX3_B, FN_SCL2_B, FN_PWM4,
5919 0, 0,
5920 /* IP9_7 [1] */
5921 FN_DU1_DOTCLKOUT0, FN_QCLK,
5922 /* IP9_6 [1] */
5923 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
5924 /* IP9_5_3 [3] */
5925 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
5926 FN_SCIF3_SCK, FN_SCIFA3_SCK,
5927 0, 0, 0,
5928 /* IP9_2_0 [3] */
5929 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
5930 0, 0, 0, }
5931 },
5932 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5933 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
5934 /* IP10_31_29 [3] */
5935 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
5936 0, 0, 0,
5937 /* IP10_28_27 [2] */
5938 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
5939 /* IP10_26_25 [2] */
5940 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
5941 /* IP10_24_22 [3] */
5942 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
5943 0, 0, 0,
5944 /* IP10_21_29 [3] */
5945 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
5946 FN_TS_SDATA0_C, FN_ATACS11_N,
5947 0, 0, 0,
5948 /* IP10_18_17 [2] */
5949 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
5950 /* IP10_16_15 [2] */
5951 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
5952 /* IP10_14_12 [3] */
5953 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
5954 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
5955 /* IP10_11_9 [3] */
5956 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
5957 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
5958 0, 0,
5959 /* IP10_8_6 [3] */
5960 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
5961 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
5962 /* IP10_5_3 [3] */
5963 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
5964 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
5965 /* IP10_2_0 [3] */
5966 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
5967 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
5968 },
5969 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5970 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
5971 3, 3, 3, 3, 3) {
5972 /* IP11_31_30 [2] */
5973 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
5974 /* IP11_29_28 [2] */
5975 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
5976 /* IP11_27 [1] */
5977 FN_VI1_DATA7, FN_AVB_MDC,
5978 /* IP11_26 [1] */
5979 FN_VI1_DATA6, FN_AVB_MAGIC,
5980 /* IP11_25 [1] */
5981 FN_VI1_DATA5, FN_AVB_RX_DV,
5982 /* IP11_24 [1] */
5983 FN_VI1_DATA4, FN_AVB_MDIO,
5984 /* IP11_23 [1] */
5985 FN_VI1_DATA3, FN_AVB_RX_ER,
5986 /* IP11_22 [1] */
5987 FN_VI1_DATA2, FN_AVB_RXD7,
5988 /* IP11_21 [1] */
5989 FN_VI1_DATA1, FN_AVB_RXD6,
5990 /* IP11_20 [1] */
5991 FN_VI1_DATA0, FN_AVB_RXD5,
5992 /* IP11_19 [1] */
5993 FN_VI1_CLK, FN_AVB_RXD4,
5994 /* IP11_18_17 [2] */
5995 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
5996 /* IP11_16_15 [2] */
5997 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
5998 /* IP11_14_12 [3] */
5999 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6000 FN_RX4_B, FN_SCIFA4_RXD_B,
6001 0, 0, 0,
6002 /* IP11_11_9 [3] */
6003 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6004 FN_TX4_B, FN_SCIFA4_TXD_B,
6005 0, 0, 0,
6006 /* IP11_8_6 [3] */
6007 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6008 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6009 /* IP11_5_3 [3] */
6010 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
6011 0, 0, 0,
6012 /* IP11_2_0 [3] */
6013 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
6014 0, 0, 0, }
6015 },
6016 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6017 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6018 /* IP12_31_30 [2] */
6019 0, 0, 0, 0,
6020 /* IP12_29_27 [3] */
6021 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6022 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6023 0, 0, 0,
6024 /* IP12_26_24 [3] */
6025 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6026 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6027 0, 0, 0,
6028 /* IP12_23_22 [2] */
6029 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6030 /* IP12_21_20 [2] */
6031 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6032 /* IP12_19_18 [2] */
6033 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6034 /* IP12_17_16 [2] */
6035 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6036 /* IP12_15_13 [3] */
6037 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6038 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6039 0, 0, 0,
6040 /* IP12_12_10 [3] */
6041 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6042 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6043 0, 0, 0,
6044 /* IP12_9_7 [3] */
6045 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6046 FN_SDA2_D, FN_MSIOF1_SCK_E,
6047 0, 0, 0,
6048 /* IP12_6_4 [3] */
6049 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6050 FN_SCL2_D, FN_MSIOF1_RXD_E,
6051 0, 0, 0,
6052 /* IP12_3_2 [2] */
6053 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
6054 /* IP12_1_0 [2] */
6055 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
6056 },
6057 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6058 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6059 3, 2, 2, 3) {
6060 /* IP13_31 [1] */
6061 0, 0,
6062 /* IP13_30_28 [3] */
6063 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
6064 0, 0, 0, 0,
6065 /* IP13_27 [1] */
6066 FN_SD1_DATA3, FN_IERX_B,
6067 /* IP13_26 [1] */
6068 FN_SD1_DATA2, FN_IECLK_B,
6069 /* IP13_25 [1] */
6070 FN_SD1_DATA1, FN_IETX_B,
6071 /* IP13_24_23 [2] */
6072 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6073 /* IP13_22 [1] */
6074 FN_SD1_CMD, FN_REMOCON_B,
6075 /* IP13_21_19 [3] */
6076 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6077 FN_SCIFA5_RXD_B, FN_RX3_C,
6078 0, 0,
6079 /* IP13_18_16 [3] */
6080 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6081 FN_SCIFA5_TXD_B, FN_TX3_C,
6082 0, 0,
6083 /* IP13_15 [1] */
6084 FN_SD0_DATA3, FN_SSL_B,
6085 /* IP13_14 [1] */
6086 FN_SD0_DATA2, FN_IO3_B,
6087 /* IP13_13 [1] */
6088 FN_SD0_DATA1, FN_IO2_B,
6089 /* IP13_12 [1] */
6090 FN_SD0_DATA0, FN_MISO_IO1_B,
6091 /* IP13_11 [1] */
6092 FN_SD0_CMD, FN_MOSI_IO0_B,
6093 /* IP13_10 [1] */
6094 FN_SD0_CLK, FN_SPCLK_B,
6095 /* IP13_9_7 [3] */
6096 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6097 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6098 0, 0, 0,
6099 /* IP13_6_5 [2] */
6100 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6101 /* IP13_4_3 [2] */
6102 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6103 /* IP13_2_0 [3] */
6104 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6105 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6106 0, 0, 0, }
6107 },
6108 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6109 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6110 /* IP14_31_29 [3] */
6111 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6112 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
6113 /* IP14_28_26 [3] */
6114 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6115 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
6116 /* IP14_25_23 [3] */
6117 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6118 0, 0, 0,
6119 /* IP14_22_20 [3] */
6120 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6121 0, 0, 0,
6122 /* IP14_19_17 [3] */
6123 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6124 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6125 0, 0,
6126 /* IP14_16_14 [3] */
6127 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6128 FN_VI1_CLK_C, FN_VI1_G0_B,
6129 0, 0,
6130 /* IP14_13_11 [3] */
6131 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6132 0, 0, 0,
6133 /* IP14_10_8 [3] */
6134 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6135 0, 0, 0,
6136 /* IP14_7 [1] */
6137 FN_SD2_DATA3, FN_MMC_D3,
6138 /* IP14_6 [1] */
6139 FN_SD2_DATA2, FN_MMC_D2,
6140 /* IP14_5 [1] */
6141 FN_SD2_DATA1, FN_MMC_D1,
6142 /* IP14_4 [1] */
6143 FN_SD2_DATA0, FN_MMC_D0,
6144 /* IP14_3 [1] */
6145 FN_SD2_CMD, FN_MMC_CMD,
6146 /* IP14_2 [1] */
6147 FN_SD2_CLK, FN_MMC_CLK,
6148 /* IP14_1_0 [2] */
6149 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
6150 },
6151 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6152 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6153 /* IP15_31_30 [2] */
6154 0, 0, 0, 0,
6155 /* IP15_29_27 [3] */
6156 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6157 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6158 0, 0,
6159 /* IP15_26_24 [3] */
6160 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6161 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6162 0, 0,
6163 /* IP15_23_21 [3] */
6164 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6165 FN_TCLK2, FN_VI1_DATA3_C, 0,
6166 /* IP15_20_18 [3] */
6167 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6168 0, 0, 0,
6169 /* IP15_17_15 [3] */
6170 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6171 FN_TCLK1, FN_VI1_DATA1_C,
6172 0, 0,
6173 /* IP15_14_12 [3] */
6174 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6175 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6176 0, 0,
6177 /* IP15_11_9 [3] */
6178 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6179 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6180 0, 0,
6181 /* IP15_8_6 [3] */
6182 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6183 FN_PWM5_B, FN_SCIFA3_TXD_C,
6184 0, 0, 0,
6185 /* IP15_5_4 [2] */
6186 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6187 /* IP15_3_2 [2] */
6188 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6189 /* IP15_1_0 [2] */
6190 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6191 },
6192 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6193 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6194 /* IP16_31_28 [4] */
6195 0, 0, 0, 0, 0, 0, 0, 0,
6196 0, 0, 0, 0, 0, 0, 0, 0,
6197 /* IP16_27_24 [4] */
6198 0, 0, 0, 0, 0, 0, 0, 0,
6199 0, 0, 0, 0, 0, 0, 0, 0,
6200 /* IP16_23_20 [4] */
6201 0, 0, 0, 0, 0, 0, 0, 0,
6202 0, 0, 0, 0, 0, 0, 0, 0,
6203 /* IP16_19_16 [4] */
6204 0, 0, 0, 0, 0, 0, 0, 0,
6205 0, 0, 0, 0, 0, 0, 0, 0,
6206 /* IP16_15_12 [4] */
6207 0, 0, 0, 0, 0, 0, 0, 0,
6208 0, 0, 0, 0, 0, 0, 0, 0,
6209 /* IP16_11_10 [2] */
6210 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6211 /* IP16_9_8 [2] */
6212 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6213 /* IP16_7_6 [2] */
6214 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6215 /* IP16_5_3 [3] */
6216 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6217 FN_GLO_SS_C, FN_VI1_DATA7_C,
6218 0, 0, 0,
6219 /* IP16_2_0 [3] */
6220 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6221 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6222 0, 0, 0, }
6223 },
6224 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6225 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6226 3, 2, 2, 2, 1, 2, 2, 2) {
6227 /* RESERVED [1] */
6228 0, 0,
6229 /* SEL_SCIF1 [2] */
6230 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6231 /* SEL_SCIFB [2] */
6232 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6233 /* SEL_SCIFB2 [2] */
6234 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6235 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6236 /* SEL_SCIFB1 [3] */
6237 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6238 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6239 0, 0, 0, 0,
6240 /* SEL_SCIFA1 [2] */
6241 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6242 /* SEL_SSI9 [1] */
6243 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6244 /* SEL_SCFA [1] */
6245 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6246 /* SEL_QSP [1] */
6247 FN_SEL_QSP_0, FN_SEL_QSP_1,
6248 /* SEL_SSI7 [1] */
6249 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6250 /* SEL_HSCIF1 [3] */
6251 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6252 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6253 0, 0, 0,
6254 /* RESERVED [2] */
6255 0, 0, 0, 0,
6256 /* SEL_VI1 [2] */
6257 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6258 /* RESERVED [2] */
6259 0, 0, 0, 0,
6260 /* SEL_TMU [1] */
6261 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6262 /* SEL_LBS [2] */
6263 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6264 /* SEL_TSIF0 [2] */
6265 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6266 /* SEL_SOF0 [2] */
6267 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6268 },
6269 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6270 3, 1, 1, 3, 2, 1, 1, 2, 2,
6271 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6272 /* SEL_SCIF0 [3] */
6273 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6274 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6275 0, 0, 0,
6276 /* RESERVED [1] */
6277 0, 0,
6278 /* SEL_SCIF [1] */
6279 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6280 /* SEL_CAN0 [3] */
6281 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6282 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6283 0, 0,
6284 /* SEL_CAN1 [2] */
6285 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6286 /* RESERVED [1] */
6287 0, 0,
6288 /* SEL_SCIFA2 [1] */
6289 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6290 /* SEL_SCIF4 [2] */
6291 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6292 /* RESERVED [2] */
6293 0, 0, 0, 0,
6294 /* SEL_ADG [1] */
6295 FN_SEL_ADG_0, FN_SEL_ADG_1,
6296 /* SEL_FM [3] */
6297 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6298 FN_SEL_FM_3, FN_SEL_FM_4,
6299 0, 0, 0,
6300 /* SEL_SCIFA5 [2] */
6301 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6302 /* RESERVED [1] */
6303 0, 0,
6304 /* SEL_GPS [2] */
6305 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6306 /* SEL_SCIFA4 [2] */
6307 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6308 /* SEL_SCIFA3 [2] */
6309 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6310 /* SEL_SIM [1] */
6311 FN_SEL_SIM_0, FN_SEL_SIM_1,
6312 /* RESERVED [1] */
6313 0, 0,
6314 /* SEL_SSI8 [1] */
6315 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6316 },
6317 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6318 2, 2, 2, 2, 2, 2, 2, 2,
6319 1, 1, 2, 2, 3, 2, 2, 2, 1) {
6320 /* SEL_HSCIF2 [2] */
6321 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6322 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6323 /* SEL_CANCLK [2] */
6324 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6325 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6326 /* SEL_IIC8 [2] */
6327 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
6328 /* SEL_IIC7 [2] */
6329 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
6330 /* SEL_IIC4 [2] */
6331 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
6332 /* SEL_IIC3 [2] */
6333 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
6334 /* SEL_SCIF3 [2] */
6335 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6336 /* SEL_IEB [2] */
6337 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6338 /* SEL_MMC [1] */
6339 FN_SEL_MMC_0, FN_SEL_MMC_1,
6340 /* SEL_SCIF5 [1] */
6341 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6342 /* RESERVED [2] */
6343 0, 0, 0, 0,
6344 /* SEL_IIC2 [2] */
6345 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
6346 /* SEL_IIC1 [3] */
6347 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
6348 FN_SEL_IIC1_4,
6349 0, 0, 0,
6350 /* SEL_IIC0 [2] */
6351 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6352 /* RESERVED [2] */
6353 0, 0, 0, 0,
6354 /* RESERVED [2] */
6355 0, 0, 0, 0,
6356 /* RESERVED [1] */
6357 0, 0, }
6358 },
6359 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6360 3, 2, 2, 1, 1, 1, 1, 3, 2,
6361 2, 3, 1, 1, 1, 2, 2, 2, 2) {
6362 /* SEL_SOF1 [3] */
6363 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6364 FN_SEL_SOF1_4,
6365 0, 0, 0,
6366 /* SEL_HSCIF0 [2] */
6367 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6368 /* SEL_DIS [2] */
6369 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6370 /* RESERVED [1] */
6371 0, 0,
6372 /* SEL_RAD [1] */
6373 FN_SEL_RAD_0, FN_SEL_RAD_1,
6374 /* SEL_RCN [1] */
6375 FN_SEL_RCN_0, FN_SEL_RCN_1,
6376 /* SEL_RSP [1] */
6377 FN_SEL_RSP_0, FN_SEL_RSP_1,
6378 /* SEL_SCIF2 [3] */
6379 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6380 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6381 0, 0, 0,
6382 /* RESERVED [2] */
6383 0, 0, 0, 0,
6384 /* RESERVED [2] */
6385 0, 0, 0, 0,
6386 /* SEL_SOF2 [3] */
6387 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6388 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6389 0, 0, 0,
6390 /* RESERVED [1] */
6391 0, 0,
6392 /* SEL_SSI1 [1] */
6393 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6394 /* SEL_SSI0 [1] */
6395 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6396 /* SEL_SSP [2] */
6397 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6398 /* RESERVED [2] */
6399 0, 0, 0, 0,
6400 /* RESERVED [2] */
6401 0, 0, 0, 0,
6402 /* RESERVED [2] */
6403 0, 0, 0, 0, }
6404 },
6405 { },
6406};
6407
6408#ifdef CONFIG_PINCTRL_PFC_R8A7791
6409const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6410 .name = "r8a77910_pfc",
6411 .unlock_reg = 0xe6060000, /* PMMR */
6412
6413 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6414
6415 .pins = pinmux_pins,
6416 .nr_pins = ARRAY_SIZE(pinmux_pins),
6417 .groups = pinmux_groups,
6418 .nr_groups = ARRAY_SIZE(pinmux_groups),
6419 .functions = pinmux_functions,
6420 .nr_functions = ARRAY_SIZE(pinmux_functions),
6421
6422 .cfg_regs = pinmux_config_regs,
6423
6424 .pinmux_data = pinmux_data,
6425 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6426};
6427#endif
6428
6429#ifdef CONFIG_PINCTRL_PFC_R8A7793
6430const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6431 .name = "r8a77930_pfc",
6432 .unlock_reg = 0xe6060000, /* PMMR */
6433
6434 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6435
6436 .pins = pinmux_pins,
6437 .nr_pins = ARRAY_SIZE(pinmux_pins),
6438 .groups = pinmux_groups,
6439 .nr_groups = ARRAY_SIZE(pinmux_groups),
6440 .functions = pinmux_functions,
6441 .nr_functions = ARRAY_SIZE(pinmux_functions),
6442
6443 .cfg_regs = pinmux_config_regs,
6444
6445 .pinmux_data = pinmux_data,
6446 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6447};
6448#endif