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at v4.5-rc4 41 lines 1.0 kB view raw
1ROCKCHIP USB2 PHY 2 3Required properties: 4 - compatible: matching the soc type, one of 5 "rockchip,rk3066a-usb-phy" 6 "rockchip,rk3188-usb-phy" 7 "rockchip,rk3288-usb-phy" 8 - rockchip,grf : phandle to the syscon managing the "general 9 register files" 10 - #address-cells: should be 1 11 - #size-cells: should be 0 12 13Sub-nodes: 14Each PHY should be represented as a sub-node. 15 16Sub-nodes 17required properties: 18- #phy-cells: should be 0 19- reg: PHY configure reg address offset in GRF 20 "0x320" - for PHY attach to OTG controller 21 "0x334" - for PHY attach to HOST0 controller 22 "0x348" - for PHY attach to HOST1 controller 23 24Optional Properties: 25- clocks : phandle + clock specifier for the phy clocks 26- clock-names: string, clock name, must be "phyclk" 27- #clock-cells: for users of the phy-pll, should be 0 28 29Example: 30 31usbphy: phy { 32 compatible = "rockchip,rk3288-usb-phy"; 33 rockchip,grf = <&grf>; 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 usbphy0: usb-phy0 { 38 #phy-cells = <0>; 39 reg = <0x320>; 40 }; 41};