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1* ARM Generic Interrupt Controller
2
3ARM SMP cores are often associated with a GIC, providing per processor
4interrupts (PPI), shared processor interrupts (SPI) and software
5generated interrupts (SGI).
6
7Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8Secondary GICs are cascaded into the upward interrupt controller and do not
9have PPIs or SGIs.
10
11Main node required properties:
12
13- compatible : should be one of:
14 "arm,arm1176jzf-devchip-gic"
15 "arm,arm11mp-gic"
16 "arm,cortex-a15-gic"
17 "arm,cortex-a7-gic"
18 "arm,cortex-a9-gic"
19 "arm,gic-400"
20 "arm,pl390"
21 "arm,tc11mp-gic"
22 "brcm,brahma-b15-gic"
23 "qcom,msm-8660-qgic"
24 "qcom,msm-qgic2"
25- interrupt-controller : Identifies the node as an interrupt controller
26- #interrupt-cells : Specifies the number of cells needed to encode an
27 interrupt source. The type shall be a <u32> and the value shall be 3.
28
29 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
30 interrupts.
31
32 The 2nd cell contains the interrupt number for the interrupt type.
33 SPI interrupts are in the range [0-987]. PPI interrupts are in the
34 range [0-15].
35
36 The 3rd cell is the flags, encoded as follows:
37 bits[3:0] trigger type and level flags.
38 1 = low-to-high edge triggered
39 2 = high-to-low edge triggered (invalid for SPIs)
40 4 = active high level-sensitive
41 8 = active low level-sensitive (invalid for SPIs).
42 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
43 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
44 the interrupt is wired to that CPU. Only valid for PPI interrupts.
45 Also note that the configurability of PPI interrupts is IMPLEMENTATION
46 DEFINED and as such not guaranteed to be present (most SoC available
47 in 2014 seem to ignore the setting of this flag and use the hardware
48 default value).
49
50- reg : Specifies base physical address(s) and size of the GIC registers. The
51 first region is the GIC distributor register base and size. The 2nd region is
52 the GIC cpu interface register base and size.
53
54Optional
55- interrupts : Interrupt source of the parent interrupt controller on
56 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
57 below).
58
59- cpu-offset : per-cpu offset within the distributor and cpu interface
60 regions, used when the GIC doesn't have banked registers. The offset is
61 cpu-offset * cpu-nr.
62
63- clocks : List of phandle and clock-specific pairs, one for each entry
64 in clock-names.
65- clock-names : List of names for the GIC clock input(s). Valid clock names
66 depend on the GIC variant:
67 "ic_clk" (for "arm,arm11mp-gic")
68 "PERIPHCLKEN" (for "arm,cortex-a15-gic")
69 "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
70 "clk" (for "arm,gic-400")
71 "gclk" (for "arm,pl390")
72
73- power-domains : A phandle and PM domain specifier as defined by bindings of
74 the power controller specified by phandle, used when the GIC
75 is part of a Power or Clock Domain.
76
77
78Example:
79
80 intc: interrupt-controller@fff11000 {
81 compatible = "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
83 #address-cells = <1>;
84 interrupt-controller;
85 reg = <0xfff11000 0x1000>,
86 <0xfff10100 0x100>;
87 };
88
89
90* GIC virtualization extensions (VGIC)
91
92For ARM cores that support the virtualization extensions, additional
93properties must be described (they only exist if the GIC is the
94primary interrupt controller).
95
96Required properties:
97
98- reg : Additional regions specifying the base physical address and
99 size of the VGIC registers. The first additional region is the GIC
100 virtual interface control register base and size. The 2nd additional
101 region is the GIC virtual cpu interface register base and size.
102
103- interrupts : VGIC maintenance interrupt.
104
105Example:
106
107 interrupt-controller@2c001000 {
108 compatible = "arm,cortex-a15-gic";
109 #interrupt-cells = <3>;
110 interrupt-controller;
111 reg = <0x2c001000 0x1000>,
112 <0x2c002000 0x1000>,
113 <0x2c004000 0x2000>,
114 <0x2c006000 0x2000>;
115 interrupts = <1 9 0xf04>;
116 };
117
118
119* GICv2m extension for MSI/MSI-x support (Optional)
120
121Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
122This is enabled by specifying v2m sub-node(s).
123
124Required properties:
125
126- compatible : The value here should contain "arm,gic-v2m-frame".
127
128- msi-controller : Identifies the node as an MSI controller.
129
130- reg : GICv2m MSI interface register base and size
131
132Optional properties:
133
134- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
135 value, this property should contain the SPI base of
136 the MSI frame, overriding the HW value.
137
138- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
139 value, this property should contain the number of
140 SPIs assigned to the frame, overriding the HW value.
141
142Example:
143
144 interrupt-controller@e1101000 {
145 compatible = "arm,gic-400";
146 #interrupt-cells = <3>;
147 #address-cells = <2>;
148 #size-cells = <2>;
149 interrupt-controller;
150 interrupts = <1 8 0xf04>;
151 ranges = <0 0 0 0xe1100000 0 0x100000>;
152 reg = <0x0 0xe1110000 0 0x01000>,
153 <0x0 0xe112f000 0 0x02000>,
154 <0x0 0xe1140000 0 0x10000>,
155 <0x0 0xe1160000 0 0x10000>;
156 v2m0: v2m@0x8000 {
157 compatible = "arm,gic-v2m-frame";
158 msi-controller;
159 reg = <0x0 0x80000 0 0x1000>;
160 };
161
162 ....
163
164 v2mN: v2m@0x9000 {
165 compatible = "arm,gic-v2m-frame";
166 msi-controller;
167 reg = <0x0 0x90000 0 0x1000>;
168 };
169 };