tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 *
3 * Copyright (C) 2015 Altera Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef _ALTERA_EDAC_H
19#define _ALTERA_EDAC_H
20
21#include <linux/edac.h>
22#include <linux/types.h>
23
24/* SDRAM Controller CtrlCfg Register */
25#define CV_CTLCFG_OFST 0x00
26
27/* SDRAM Controller CtrlCfg Register Bit Masks */
28#define CV_CTLCFG_ECC_EN 0x400
29#define CV_CTLCFG_ECC_CORR_EN 0x800
30#define CV_CTLCFG_GEN_SB_ERR 0x2000
31#define CV_CTLCFG_GEN_DB_ERR 0x4000
32
33#define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN)
34
35/* SDRAM Controller Address Width Register */
36#define CV_DRAMADDRW_OFST 0x2C
37
38/* SDRAM Controller Address Widths Field Register */
39#define DRAMADDRW_COLBIT_MASK 0x001F
40#define DRAMADDRW_COLBIT_SHIFT 0
41#define DRAMADDRW_ROWBIT_MASK 0x03E0
42#define DRAMADDRW_ROWBIT_SHIFT 5
43#define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
44#define CV_DRAMADDRW_BANKBIT_SHIFT 10
45#define CV_DRAMADDRW_CSBIT_MASK 0xE000
46#define CV_DRAMADDRW_CSBIT_SHIFT 13
47
48/* SDRAM Controller Interface Data Width Register */
49#define CV_DRAMIFWIDTH_OFST 0x30
50
51/* SDRAM Controller Interface Data Width Defines */
52#define CV_DRAMIFWIDTH_16B_ECC 24
53#define CV_DRAMIFWIDTH_32B_ECC 40
54
55/* SDRAM Controller DRAM Status Register */
56#define CV_DRAMSTS_OFST 0x38
57
58/* SDRAM Controller DRAM Status Register Bit Masks */
59#define CV_DRAMSTS_SBEERR 0x04
60#define CV_DRAMSTS_DBEERR 0x08
61#define CV_DRAMSTS_CORR_DROP 0x10
62
63/* SDRAM Controller DRAM IRQ Register */
64#define CV_DRAMINTR_OFST 0x3C
65
66/* SDRAM Controller DRAM IRQ Register Bit Masks */
67#define CV_DRAMINTR_INTREN 0x01
68#define CV_DRAMINTR_SBEMASK 0x02
69#define CV_DRAMINTR_DBEMASK 0x04
70#define CV_DRAMINTR_CORRDROPMASK 0x08
71#define CV_DRAMINTR_INTRCLR 0x10
72
73/* SDRAM Controller Single Bit Error Count Register */
74#define CV_SBECOUNT_OFST 0x40
75
76/* SDRAM Controller Double Bit Error Count Register */
77#define CV_DBECOUNT_OFST 0x44
78
79/* SDRAM Controller ECC Error Address Register */
80#define CV_ERRADDR_OFST 0x48
81
82/*-----------------------------------------*/
83
84/* SDRAM Controller EccCtrl Register */
85#define A10_ECCCTRL1_OFST 0x00
86
87/* SDRAM Controller EccCtrl Register Bit Masks */
88#define A10_ECCCTRL1_ECC_EN 0x001
89#define A10_ECCCTRL1_CNT_RST 0x010
90#define A10_ECCCTRL1_AWB_CNT_RST 0x100
91#define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \
92 A10_ECCCTRL1_AWB_CNT_RST)
93
94/* SDRAM Controller Address Width Register */
95#define CV_DRAMADDRW 0xFFC2502C
96#define A10_DRAMADDRW 0xFFCFA0A8
97
98/* SDRAM Controller Address Widths Field Register */
99#define DRAMADDRW_COLBIT_MASK 0x001F
100#define DRAMADDRW_COLBIT_SHIFT 0
101#define DRAMADDRW_ROWBIT_MASK 0x03E0
102#define DRAMADDRW_ROWBIT_SHIFT 5
103#define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
104#define CV_DRAMADDRW_BANKBIT_SHIFT 10
105#define CV_DRAMADDRW_CSBIT_MASK 0xE000
106#define CV_DRAMADDRW_CSBIT_SHIFT 13
107
108#define A10_DRAMADDRW_BANKBIT_MASK 0x3C00
109#define A10_DRAMADDRW_BANKBIT_SHIFT 10
110#define A10_DRAMADDRW_GRPBIT_MASK 0xC000
111#define A10_DRAMADDRW_GRPBIT_SHIFT 14
112#define A10_DRAMADDRW_CSBIT_MASK 0x70000
113#define A10_DRAMADDRW_CSBIT_SHIFT 16
114
115/* SDRAM Controller Interface Data Width Register */
116#define CV_DRAMIFWIDTH 0xFFC25030
117#define A10_DRAMIFWIDTH 0xFFCFB008
118
119/* SDRAM Controller Interface Data Width Defines */
120#define CV_DRAMIFWIDTH_16B_ECC 24
121#define CV_DRAMIFWIDTH_32B_ECC 40
122
123#define A10_DRAMIFWIDTH_16B 0x0
124#define A10_DRAMIFWIDTH_32B 0x1
125#define A10_DRAMIFWIDTH_64B 0x2
126
127/* SDRAM Controller DRAM IRQ Register */
128#define A10_ERRINTEN_OFST 0x10
129
130/* SDRAM Controller DRAM IRQ Register Bit Masks */
131#define A10_ERRINTEN_SERRINTEN 0x01
132#define A10_ERRINTEN_DERRINTEN 0x02
133#define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \
134 A10_ERRINTEN_DERRINTEN)
135
136/* SDRAM Interrupt Mode Register */
137#define A10_INTMODE_OFST 0x1C
138#define A10_INTMODE_SB_INT 1
139
140/* SDRAM Controller Error Status Register */
141#define A10_INTSTAT_OFST 0x20
142
143/* SDRAM Controller Error Status Register Bit Masks */
144#define A10_INTSTAT_SBEERR 0x01
145#define A10_INTSTAT_DBEERR 0x02
146
147/* SDRAM Controller ECC Error Address Register */
148#define A10_DERRADDR_OFST 0x2C
149#define A10_SERRADDR_OFST 0x30
150
151/* SDRAM Controller ECC Diagnostic Register */
152#define A10_DIAGINTTEST_OFST 0x24
153
154#define A10_DIAGINT_TSERRA_MASK 0x0001
155#define A10_DIAGINT_TDERRA_MASK 0x0100
156
157#define A10_SBERR_IRQ 34
158#define A10_DBERR_IRQ 32
159
160/* SDRAM Single Bit Error Count Compare Set Register */
161#define A10_SERRCNTREG_OFST 0x3C
162
163#define A10_SYMAN_INTMASK_CLR 0xFFD06098
164#define A10_INTMASK_CLR_OFST 0x10
165#define A10_DDR0_IRQ_MASK BIT(17)
166
167struct altr_sdram_prv_data {
168 int ecc_ctrl_offset;
169 int ecc_ctl_en_mask;
170 int ecc_cecnt_offset;
171 int ecc_uecnt_offset;
172 int ecc_stat_offset;
173 int ecc_stat_ce_mask;
174 int ecc_stat_ue_mask;
175 int ecc_saddr_offset;
176 int ecc_daddr_offset;
177 int ecc_irq_en_offset;
178 int ecc_irq_en_mask;
179 int ecc_irq_clr_offset;
180 int ecc_irq_clr_mask;
181 int ecc_cnt_rst_offset;
182 int ecc_cnt_rst_mask;
183 struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
184 int ecc_enable_mask;
185 int ce_set_mask;
186 int ue_set_mask;
187 int ce_ue_trgr_offset;
188};
189
190/* Altera SDRAM Memory Controller data */
191struct altr_sdram_mc_data {
192 struct regmap *mc_vbase;
193 int sb_irq;
194 int db_irq;
195 const struct altr_sdram_prv_data *data;
196};
197
198#endif /* #ifndef _ALTERA_EDAC_H */