tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Header file for Samsung DP (Display Port) interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef _EXYNOS_DP_CORE_H
14#define _EXYNOS_DP_CORE_H
15
16#include <drm/drm_crtc.h>
17#include <drm/drm_dp_helper.h>
18#include <drm/exynos_drm.h>
19
20#include "exynos_drm_drv.h"
21
22#define DP_TIMEOUT_LOOP_COUNT 100
23#define MAX_CR_LOOP 5
24#define MAX_EQ_LOOP 5
25
26enum link_rate_type {
27 LINK_RATE_1_62GBPS = 0x06,
28 LINK_RATE_2_70GBPS = 0x0a
29};
30
31enum link_lane_count_type {
32 LANE_COUNT1 = 1,
33 LANE_COUNT2 = 2,
34 LANE_COUNT4 = 4
35};
36
37enum link_training_state {
38 START,
39 CLOCK_RECOVERY,
40 EQUALIZER_TRAINING,
41 FINISHED,
42 FAILED
43};
44
45enum voltage_swing_level {
46 VOLTAGE_LEVEL_0,
47 VOLTAGE_LEVEL_1,
48 VOLTAGE_LEVEL_2,
49 VOLTAGE_LEVEL_3,
50};
51
52enum pre_emphasis_level {
53 PRE_EMPHASIS_LEVEL_0,
54 PRE_EMPHASIS_LEVEL_1,
55 PRE_EMPHASIS_LEVEL_2,
56 PRE_EMPHASIS_LEVEL_3,
57};
58
59enum pattern_set {
60 PRBS7,
61 D10_2,
62 TRAINING_PTN1,
63 TRAINING_PTN2,
64 DP_NONE
65};
66
67enum color_space {
68 COLOR_RGB,
69 COLOR_YCBCR422,
70 COLOR_YCBCR444
71};
72
73enum color_depth {
74 COLOR_6,
75 COLOR_8,
76 COLOR_10,
77 COLOR_12
78};
79
80enum color_coefficient {
81 COLOR_YCBCR601,
82 COLOR_YCBCR709
83};
84
85enum dynamic_range {
86 VESA,
87 CEA
88};
89
90enum pll_status {
91 PLL_UNLOCKED,
92 PLL_LOCKED
93};
94
95enum clock_recovery_m_value_type {
96 CALCULATED_M,
97 REGISTER_M
98};
99
100enum video_timing_recognition_type {
101 VIDEO_TIMING_FROM_CAPTURE,
102 VIDEO_TIMING_FROM_REGISTER
103};
104
105enum analog_power_block {
106 AUX_BLOCK,
107 CH0_BLOCK,
108 CH1_BLOCK,
109 CH2_BLOCK,
110 CH3_BLOCK,
111 ANALOG_TOTAL,
112 POWER_ALL
113};
114
115enum dp_irq_type {
116 DP_IRQ_TYPE_HP_CABLE_IN,
117 DP_IRQ_TYPE_HP_CABLE_OUT,
118 DP_IRQ_TYPE_HP_CHANGE,
119 DP_IRQ_TYPE_UNKNOWN,
120};
121
122struct video_info {
123 char *name;
124
125 bool h_sync_polarity;
126 bool v_sync_polarity;
127 bool interlaced;
128
129 enum color_space color_space;
130 enum dynamic_range dynamic_range;
131 enum color_coefficient ycbcr_coeff;
132 enum color_depth color_depth;
133
134 enum link_rate_type link_rate;
135 enum link_lane_count_type lane_count;
136};
137
138struct link_train {
139 int eq_loop;
140 int cr_loop[4];
141
142 u8 link_rate;
143 u8 lane_count;
144 u8 training_lane[4];
145
146 enum link_training_state lt_state;
147};
148
149struct exynos_dp_device {
150 struct drm_encoder encoder;
151 struct device *dev;
152 struct drm_device *drm_dev;
153 struct drm_connector connector;
154 struct drm_panel *panel;
155 struct drm_bridge *bridge;
156 struct clk *clock;
157 unsigned int irq;
158 void __iomem *reg_base;
159
160 struct video_info *video_info;
161 struct link_train link_train;
162 struct work_struct hotplug_work;
163 struct phy *phy;
164 int dpms_mode;
165 int hpd_gpio;
166
167 struct exynos_drm_panel_info priv;
168};
169
170/* exynos_dp_reg.c */
171void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
172void exynos_dp_stop_video(struct exynos_dp_device *dp);
173void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
174void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
175void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
176void exynos_dp_reset(struct exynos_dp_device *dp);
177void exynos_dp_swreset(struct exynos_dp_device *dp);
178void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
179enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
180void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
181void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
182 enum analog_power_block block,
183 bool enable);
184void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
185void exynos_dp_init_hpd(struct exynos_dp_device *dp);
186enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
187void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
188void exynos_dp_reset_aux(struct exynos_dp_device *dp);
189void exynos_dp_init_aux(struct exynos_dp_device *dp);
190int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
191void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
192int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
193int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
194 unsigned int reg_addr,
195 unsigned char data);
196int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
197 unsigned int reg_addr,
198 unsigned char *data);
199int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
200 unsigned int reg_addr,
201 unsigned int count,
202 unsigned char data[]);
203int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
204 unsigned int reg_addr,
205 unsigned int count,
206 unsigned char data[]);
207int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
208 unsigned int device_addr,
209 unsigned int reg_addr);
210int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
211 unsigned int device_addr,
212 unsigned int reg_addr,
213 unsigned int *data);
214int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
215 unsigned int device_addr,
216 unsigned int reg_addr,
217 unsigned int count,
218 unsigned char edid[]);
219void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
220void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
221void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
222void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
223void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
224void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
225 enum pattern_set pattern);
226void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
227void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
228void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
229void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
230void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
231 u32 training_lane);
232void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
233 u32 training_lane);
234void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
235 u32 training_lane);
236void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
237 u32 training_lane);
238u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
239u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
240u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
241u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
242void exynos_dp_reset_macro(struct exynos_dp_device *dp);
243void exynos_dp_init_video(struct exynos_dp_device *dp);
244
245void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
246int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
247void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
248 enum clock_recovery_m_value_type type,
249 u32 m_value,
250 u32 n_value);
251void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
252void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
253void exynos_dp_start_video(struct exynos_dp_device *dp);
254int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
255void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
256void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
257void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
258
259/* I2C EDID Chip ID, Slave Address */
260#define I2C_EDID_DEVICE_ADDR 0x50
261#define I2C_E_EDID_DEVICE_ADDR 0x30
262
263#define EDID_BLOCK_LENGTH 0x80
264#define EDID_HEADER_PATTERN 0x00
265#define EDID_EXTENSION_FLAG 0x7e
266#define EDID_CHECKSUM 0x7f
267
268/* DP_MAX_LANE_COUNT */
269#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
270#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
271
272/* DP_LANE_COUNT_SET */
273#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
274
275/* DP_TRAINING_LANE0_SET */
276#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
277#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
278#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
279#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
280
281#endif /* _EXYNOS_DP_CORE_H */