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1* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
4and several fixed ratio dividers.
5The CPG also provides a Clock Domain for SoC devices, in combination with the
6CPG Module Stop (MSTP) Clocks.
7
8Required Properties:
9
10 - compatible: Must be one of
11 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
12 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
13 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
14 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
15 and "renesas,rcar-gen2-cpg-clocks" as a fallback.
16
17 - reg: Base address and length of the memory resource used by the CPG
18
19 - clocks: References to the parent clocks: first to the EXTAL clock, second
20 to the USB_EXTAL clock
21 - #clock-cells: Must be 1
22 - clock-output-names: The names of the clocks. Supported clocks are "main",
23 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
24 "adsp"
25 - #power-domain-cells: Must be 0
26
27SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
28through an MSTP clock should refer to the CPG device node in their
29"power-domains" property, as documented by the generic PM domain bindings in
30Documentation/devicetree/bindings/power/power_domain.txt.
31
32
33Examples
34--------
35
36 - CPG device node:
37
38 cpg_clocks: cpg_clocks@e6150000 {
39 compatible = "renesas,r8a7790-cpg-clocks",
40 "renesas,rcar-gen2-cpg-clocks";
41 reg = <0 0xe6150000 0 0x1000>;
42 clocks = <&extal_clk &usb_extal_clk>;
43 #clock-cells = <1>;
44 clock-output-names = "main", "pll0, "pll1", "pll3",
45 "lb", "qspi", "sdh", "sd0", "sd1", "z",
46 "rcan", "adsp";
47 #power-domain-cells = <0>;
48 };
49
50
51 - CPG/MSTP Clock Domain member device node:
52
53 thermal@e61f0000 {
54 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
55 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
56 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
57 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
58 power-domains = <&cpg_clocks>;
59 };