tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * pxa910 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/spinlock.h>
16#include <linux/io.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19
20#include <mach/addr-map.h>
21
22#include "clk.h"
23
24#define APBC_RTC 0x28
25#define APBC_TWSI0 0x2c
26#define APBC_KPC 0x18
27#define APBC_UART0 0x0
28#define APBC_UART1 0x4
29#define APBC_GPIO 0x8
30#define APBC_PWM0 0xc
31#define APBC_PWM1 0x10
32#define APBC_PWM2 0x14
33#define APBC_PWM3 0x18
34#define APBC_SSP0 0x1c
35#define APBC_SSP1 0x20
36#define APBC_SSP2 0x4c
37#define APBCP_TWSI1 0x28
38#define APBCP_UART2 0x1c
39#define APMU_SDH0 0x54
40#define APMU_SDH1 0x58
41#define APMU_USB 0x5c
42#define APMU_DISP0 0x4c
43#define APMU_CCIC0 0x50
44#define APMU_DFC 0x60
45#define MPMU_UART_PLL 0x14
46
47static DEFINE_SPINLOCK(clk_lock);
48
49static struct mmp_clk_factor_masks uart_factor_masks = {
50 .factor = 2,
51 .num_mask = 0x1fff,
52 .den_mask = 0x1fff,
53 .num_shift = 16,
54 .den_shift = 0,
55};
56
57static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
58 {.num = 8125, .den = 1536}, /*14.745MHZ */
59};
60
61static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
62static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
63static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
64static const char *disp_parent[] = {"pll1_2", "pll1_12"};
65static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
66static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
67
68void __init pxa910_clk_init(void)
69{
70 struct clk *clk;
71 struct clk *uart_pll;
72 void __iomem *mpmu_base;
73 void __iomem *apmu_base;
74 void __iomem *apbcp_base;
75 void __iomem *apbc_base;
76
77 mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
78 if (mpmu_base == NULL) {
79 pr_err("error to ioremap MPMU base\n");
80 return;
81 }
82
83 apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
84 if (apmu_base == NULL) {
85 pr_err("error to ioremap APMU base\n");
86 return;
87 }
88
89 apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K);
90 if (apbcp_base == NULL) {
91 pr_err("error to ioremap APBC extension base\n");
92 return;
93 }
94
95 apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
96 if (apbc_base == NULL) {
97 pr_err("error to ioremap APBC base\n");
98 return;
99 }
100
101 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
102 clk_register_clkdev(clk, "clk32", NULL);
103
104 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
105 26000000);
106 clk_register_clkdev(clk, "vctcxo", NULL);
107
108 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
109 624000000);
110 clk_register_clkdev(clk, "pll1", NULL);
111
112 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
113 CLK_SET_RATE_PARENT, 1, 2);
114 clk_register_clkdev(clk, "pll1_2", NULL);
115
116 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
117 CLK_SET_RATE_PARENT, 1, 2);
118 clk_register_clkdev(clk, "pll1_4", NULL);
119
120 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
121 CLK_SET_RATE_PARENT, 1, 2);
122 clk_register_clkdev(clk, "pll1_8", NULL);
123
124 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
125 CLK_SET_RATE_PARENT, 1, 2);
126 clk_register_clkdev(clk, "pll1_16", NULL);
127
128 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
129 CLK_SET_RATE_PARENT, 1, 3);
130 clk_register_clkdev(clk, "pll1_6", NULL);
131
132 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
133 CLK_SET_RATE_PARENT, 1, 2);
134 clk_register_clkdev(clk, "pll1_12", NULL);
135
136 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
137 CLK_SET_RATE_PARENT, 1, 2);
138 clk_register_clkdev(clk, "pll1_24", NULL);
139
140 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
141 CLK_SET_RATE_PARENT, 1, 2);
142 clk_register_clkdev(clk, "pll1_48", NULL);
143
144 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
145 CLK_SET_RATE_PARENT, 1, 2);
146 clk_register_clkdev(clk, "pll1_96", NULL);
147
148 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
149 CLK_SET_RATE_PARENT, 1, 13);
150 clk_register_clkdev(clk, "pll1_13", NULL);
151
152 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
153 CLK_SET_RATE_PARENT, 2, 3);
154 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
155
156 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
157 CLK_SET_RATE_PARENT, 2, 3);
158 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
159
160 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
161 CLK_SET_RATE_PARENT, 3, 16);
162 clk_register_clkdev(clk, "pll1_3_16", NULL);
163
164 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
165 mpmu_base + MPMU_UART_PLL,
166 &uart_factor_masks, uart_factor_tbl,
167 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
168 clk_set_rate(uart_pll, 14745600);
169 clk_register_clkdev(uart_pll, "uart_pll", NULL);
170
171 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
172 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
173 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
174
175 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
176 apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
177 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
178
179 clk = mmp_clk_register_apbc("gpio", "vctcxo",
180 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
181 clk_register_clkdev(clk, NULL, "mmp-gpio");
182
183 clk = mmp_clk_register_apbc("kpc", "clk32",
184 apbc_base + APBC_KPC, 10, 0, &clk_lock);
185 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
186
187 clk = mmp_clk_register_apbc("rtc", "clk32",
188 apbc_base + APBC_RTC, 10, 0, &clk_lock);
189 clk_register_clkdev(clk, NULL, "sa1100-rtc");
190
191 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
192 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
193 clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
194
195 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
196 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
197 clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
198
199 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
200 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
201 clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
202
203 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
204 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
205 clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
206
207 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
208 ARRAY_SIZE(uart_parent),
209 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
210 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
211 clk_set_parent(clk, uart_pll);
212 clk_register_clkdev(clk, "uart_mux.0", NULL);
213
214 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
215 apbc_base + APBC_UART0, 10, 0, &clk_lock);
216 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
217
218 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
219 ARRAY_SIZE(uart_parent),
220 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
221 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
222 clk_set_parent(clk, uart_pll);
223 clk_register_clkdev(clk, "uart_mux.1", NULL);
224
225 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
226 apbc_base + APBC_UART1, 10, 0, &clk_lock);
227 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
228
229 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
230 ARRAY_SIZE(uart_parent),
231 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
232 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
233 clk_set_parent(clk, uart_pll);
234 clk_register_clkdev(clk, "uart_mux.2", NULL);
235
236 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
237 apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
238 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
239
240 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
241 ARRAY_SIZE(ssp_parent),
242 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
243 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
244 clk_register_clkdev(clk, "uart_mux.0", NULL);
245
246 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
247 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
248 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
249
250 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
251 ARRAY_SIZE(ssp_parent),
252 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
253 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
254 clk_register_clkdev(clk, "ssp_mux.1", NULL);
255
256 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
257 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
258 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
259
260 clk = mmp_clk_register_apmu("dfc", "pll1_4",
261 apmu_base + APMU_DFC, 0x19b, &clk_lock);
262 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
263
264 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
265 ARRAY_SIZE(sdh_parent),
266 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
267 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
268 clk_register_clkdev(clk, "sdh0_mux", NULL);
269
270 clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
271 apmu_base + APMU_SDH0, 0x1b, &clk_lock);
272 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
273
274 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
275 ARRAY_SIZE(sdh_parent),
276 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
277 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
278 clk_register_clkdev(clk, "sdh1_mux", NULL);
279
280 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
281 apmu_base + APMU_SDH1, 0x1b, &clk_lock);
282 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
283
284 clk = mmp_clk_register_apmu("usb", "usb_pll",
285 apmu_base + APMU_USB, 0x9, &clk_lock);
286 clk_register_clkdev(clk, "usb_clk", NULL);
287
288 clk = mmp_clk_register_apmu("sph", "usb_pll",
289 apmu_base + APMU_USB, 0x12, &clk_lock);
290 clk_register_clkdev(clk, "sph_clk", NULL);
291
292 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
293 ARRAY_SIZE(disp_parent),
294 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
295 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
296 clk_register_clkdev(clk, "disp_mux.0", NULL);
297
298 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
299 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
300 clk_register_clkdev(clk, NULL, "mmp-disp.0");
301
302 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
303 ARRAY_SIZE(ccic_parent),
304 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
305 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
306 clk_register_clkdev(clk, "ccic_mux.0", NULL);
307
308 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
309 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
310 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
311
312 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
313 ARRAY_SIZE(ccic_phy_parent),
314 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
315 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
316 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
317
318 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
319 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
320 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
321
322 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
323 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
324 10, 5, 0, &clk_lock);
325 clk_register_clkdev(clk, "sphyclk_div", NULL);
326
327 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
328 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
329 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
330}