tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/ethtool.h>
17#include <linux/kernel.h>
18#include <linux/mii.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/phy.h>
22
23#include <dt-bindings/net/ti-dp83867.h>
24
25#define DP83867_PHY_ID 0x2000a231
26#define DP83867_DEVADDR 0x1f
27
28#define MII_DP83867_PHYCTRL 0x10
29#define MII_DP83867_MICR 0x12
30#define MII_DP83867_ISR 0x13
31#define DP83867_CTRL 0x1f
32
33/* Extended Registers */
34#define DP83867_RGMIICTL 0x0032
35#define DP83867_RGMIIDCTL 0x0086
36
37#define DP83867_SW_RESET BIT(15)
38#define DP83867_SW_RESTART BIT(14)
39
40/* MICR Interrupt bits */
41#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
42#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
43#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
44#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
45#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
46#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
47#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
48#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
49#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
50#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
51#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
52#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
53
54/* RGMIICTL bits */
55#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
56#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
57
58/* PHY CTRL bits */
59#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
60
61/* RGMIIDCTL bits */
62#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
63
64struct dp83867_private {
65 int rx_id_delay;
66 int tx_id_delay;
67 int fifo_depth;
68};
69
70static int dp83867_ack_interrupt(struct phy_device *phydev)
71{
72 int err = phy_read(phydev, MII_DP83867_ISR);
73
74 if (err < 0)
75 return err;
76
77 return 0;
78}
79
80static int dp83867_config_intr(struct phy_device *phydev)
81{
82 int micr_status;
83
84 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
85 micr_status = phy_read(phydev, MII_DP83867_MICR);
86 if (micr_status < 0)
87 return micr_status;
88
89 micr_status |=
90 (MII_DP83867_MICR_AN_ERR_INT_EN |
91 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
92 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
93 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
94
95 return phy_write(phydev, MII_DP83867_MICR, micr_status);
96 }
97
98 micr_status = 0x0;
99 return phy_write(phydev, MII_DP83867_MICR, micr_status);
100}
101
102#ifdef CONFIG_OF_MDIO
103static int dp83867_of_init(struct phy_device *phydev)
104{
105 struct dp83867_private *dp83867 = phydev->priv;
106 struct device *dev = &phydev->dev;
107 struct device_node *of_node = dev->of_node;
108 int ret;
109
110 if (!of_node && dev->parent->of_node)
111 of_node = dev->parent->of_node;
112
113 if (!phydev->dev.of_node)
114 return -ENODEV;
115
116 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
117 &dp83867->rx_id_delay);
118 if (ret)
119 return ret;
120
121 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
122 &dp83867->tx_id_delay);
123 if (ret)
124 return ret;
125
126 return of_property_read_u32(of_node, "ti,fifo-depth",
127 &dp83867->fifo_depth);
128}
129#else
130static int dp83867_of_init(struct phy_device *phydev)
131{
132 return 0;
133}
134#endif /* CONFIG_OF_MDIO */
135
136static int dp83867_config_init(struct phy_device *phydev)
137{
138 struct dp83867_private *dp83867;
139 int ret;
140 u16 val, delay;
141
142 if (!phydev->priv) {
143 dp83867 = devm_kzalloc(&phydev->dev, sizeof(*dp83867),
144 GFP_KERNEL);
145 if (!dp83867)
146 return -ENOMEM;
147
148 phydev->priv = dp83867;
149 ret = dp83867_of_init(phydev);
150 if (ret)
151 return ret;
152 } else {
153 dp83867 = (struct dp83867_private *)phydev->priv;
154 }
155
156 if (phy_interface_is_rgmii(phydev)) {
157 ret = phy_write(phydev, MII_DP83867_PHYCTRL,
158 (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
159 if (ret)
160 return ret;
161 }
162
163 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
164 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
165 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
166 DP83867_DEVADDR, phydev->addr);
167
168 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
169 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
170
171 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
172 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
173
174 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
175 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
176
177 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
178 DP83867_DEVADDR, phydev->addr, val);
179
180 delay = (dp83867->rx_id_delay |
181 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
182
183 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
184 DP83867_DEVADDR, phydev->addr, delay);
185 }
186
187 return 0;
188}
189
190static int dp83867_phy_reset(struct phy_device *phydev)
191{
192 int err;
193
194 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
195 if (err < 0)
196 return err;
197
198 return dp83867_config_init(phydev);
199}
200
201static struct phy_driver dp83867_driver[] = {
202 {
203 .phy_id = DP83867_PHY_ID,
204 .phy_id_mask = 0xfffffff0,
205 .name = "TI DP83867",
206 .features = PHY_GBIT_FEATURES,
207 .flags = PHY_HAS_INTERRUPT,
208
209 .config_init = dp83867_config_init,
210 .soft_reset = dp83867_phy_reset,
211
212 /* IRQ related */
213 .ack_interrupt = dp83867_ack_interrupt,
214 .config_intr = dp83867_config_intr,
215
216 .config_aneg = genphy_config_aneg,
217 .read_status = genphy_read_status,
218 .suspend = genphy_suspend,
219 .resume = genphy_resume,
220
221 .driver = {.owner = THIS_MODULE,}
222 },
223};
224module_phy_driver(dp83867_driver);
225
226static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
227 { DP83867_PHY_ID, 0xfffffff0 },
228 { }
229};
230
231MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
232
233MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
234MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
235MODULE_LICENSE("GPL");