tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
25#include <linux/component.h>
26#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31#include <linux/iommu.h>
32#include <linux/types.h>
33#include <linux/of_graph.h>
34#include <asm/sizes.h>
35
36#ifndef CONFIG_OF
37#include <mach/board.h>
38#include <mach/socinfo.h>
39#include <mach/iommu_domains.h>
40#endif
41
42#include <drm/drmP.h>
43#include <drm/drm_atomic.h>
44#include <drm/drm_atomic_helper.h>
45#include <drm/drm_crtc_helper.h>
46#include <drm/drm_plane_helper.h>
47#include <drm/drm_fb_helper.h>
48#include <drm/msm_drm.h>
49#include <drm/drm_gem.h>
50
51struct msm_kms;
52struct msm_gpu;
53struct msm_mmu;
54struct msm_rd_state;
55struct msm_perf_state;
56struct msm_gem_submit;
57
58#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
59
60struct msm_file_private {
61 /* currently we don't do anything useful with this.. but when
62 * per-context address spaces are supported we'd keep track of
63 * the context's page-tables here.
64 */
65 int dummy;
66};
67
68enum msm_mdp_plane_property {
69 PLANE_PROP_ZPOS,
70 PLANE_PROP_ALPHA,
71 PLANE_PROP_PREMULTIPLIED,
72 PLANE_PROP_MAX_NUM
73};
74
75struct msm_vblank_ctrl {
76 struct work_struct work;
77 struct list_head event_list;
78 spinlock_t lock;
79};
80
81struct msm_drm_private {
82
83 struct msm_kms *kms;
84
85 /* subordinate devices, if present: */
86 struct platform_device *gpu_pdev;
87
88 /* possibly this should be in the kms component, but it is
89 * shared by both mdp4 and mdp5..
90 */
91 struct hdmi *hdmi;
92
93 /* eDP is for mdp5 only, but kms has not been created
94 * when edp_bind() and edp_init() are called. Here is the only
95 * place to keep the edp instance.
96 */
97 struct msm_edp *edp;
98
99 /* DSI is shared by mdp4 and mdp5 */
100 struct msm_dsi *dsi[2];
101
102 /* when we have more than one 'msm_gpu' these need to be an array: */
103 struct msm_gpu *gpu;
104 struct msm_file_private *lastctx;
105
106 struct drm_fb_helper *fbdev;
107
108 uint32_t next_fence, completed_fence;
109 wait_queue_head_t fence_event;
110
111 struct msm_rd_state *rd;
112 struct msm_perf_state *perf;
113
114 /* list of GEM objects: */
115 struct list_head inactive_list;
116
117 struct workqueue_struct *wq;
118
119 /* callbacks deferred until bo is inactive: */
120 struct list_head fence_cbs;
121
122 /* crtcs pending async atomic updates: */
123 uint32_t pending_crtcs;
124 wait_queue_head_t pending_crtcs_event;
125
126 /* registered MMUs: */
127 unsigned int num_mmus;
128 struct msm_mmu *mmus[NUM_DOMAINS];
129
130 unsigned int num_planes;
131 struct drm_plane *planes[8];
132
133 unsigned int num_crtcs;
134 struct drm_crtc *crtcs[8];
135
136 unsigned int num_encoders;
137 struct drm_encoder *encoders[8];
138
139 unsigned int num_bridges;
140 struct drm_bridge *bridges[8];
141
142 unsigned int num_connectors;
143 struct drm_connector *connectors[8];
144
145 /* Properties */
146 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
147
148 /* VRAM carveout, used when no IOMMU: */
149 struct {
150 unsigned long size;
151 dma_addr_t paddr;
152 /* NOTE: mm managed at the page level, size is in # of pages
153 * and position mm_node->start is in # of pages:
154 */
155 struct drm_mm mm;
156 } vram;
157
158 struct msm_vblank_ctrl vblank_ctrl;
159};
160
161struct msm_format {
162 uint32_t pixel_format;
163};
164
165/* callback from wq once fence has passed: */
166struct msm_fence_cb {
167 struct work_struct work;
168 uint32_t fence;
169 void (*func)(struct msm_fence_cb *cb);
170};
171
172void __msm_fence_worker(struct work_struct *work);
173
174#define INIT_FENCE_CB(_cb, _func) do { \
175 INIT_WORK(&(_cb)->work, __msm_fence_worker); \
176 (_cb)->func = _func; \
177 } while (0)
178
179int msm_atomic_check(struct drm_device *dev,
180 struct drm_atomic_state *state);
181int msm_atomic_commit(struct drm_device *dev,
182 struct drm_atomic_state *state, bool async);
183
184int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
185
186int msm_wait_fence(struct drm_device *dev, uint32_t fence,
187 ktime_t *timeout, bool interruptible);
188int msm_queue_fence_cb(struct drm_device *dev,
189 struct msm_fence_cb *cb, uint32_t fence);
190void msm_update_fence(struct drm_device *dev, uint32_t fence);
191
192int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
193 struct drm_file *file);
194
195int msm_gem_mmap_obj(struct drm_gem_object *obj,
196 struct vm_area_struct *vma);
197int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
198int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
199uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
200int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
201 uint32_t *iova);
202int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
203uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
204struct page **msm_gem_get_pages(struct drm_gem_object *obj);
205void msm_gem_put_pages(struct drm_gem_object *obj);
206void msm_gem_put_iova(struct drm_gem_object *obj, int id);
207int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
208 struct drm_mode_create_dumb *args);
209int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
210 uint32_t handle, uint64_t *offset);
211struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
212void *msm_gem_prime_vmap(struct drm_gem_object *obj);
213void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
214int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
215struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
216 struct dma_buf_attachment *attach, struct sg_table *sg);
217int msm_gem_prime_pin(struct drm_gem_object *obj);
218void msm_gem_prime_unpin(struct drm_gem_object *obj);
219void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
220void *msm_gem_vaddr(struct drm_gem_object *obj);
221int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
222 struct msm_fence_cb *cb);
223void msm_gem_move_to_active(struct drm_gem_object *obj,
224 struct msm_gpu *gpu, bool write, uint32_t fence);
225void msm_gem_move_to_inactive(struct drm_gem_object *obj);
226int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
227 ktime_t *timeout);
228int msm_gem_cpu_fini(struct drm_gem_object *obj);
229void msm_gem_free_object(struct drm_gem_object *obj);
230int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
231 uint32_t size, uint32_t flags, uint32_t *handle);
232struct drm_gem_object *msm_gem_new(struct drm_device *dev,
233 uint32_t size, uint32_t flags);
234struct drm_gem_object *msm_gem_import(struct drm_device *dev,
235 uint32_t size, struct sg_table *sgt);
236
237int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
238void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
239uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
240struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
241const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
242struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
243 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
244struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
245 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
246
247struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
248
249struct hdmi;
250int hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
251 struct drm_encoder *encoder);
252void __init hdmi_register(void);
253void __exit hdmi_unregister(void);
254
255struct msm_edp;
256void __init msm_edp_register(void);
257void __exit msm_edp_unregister(void);
258int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
259 struct drm_encoder *encoder);
260
261struct msm_dsi;
262enum msm_dsi_encoder_id {
263 MSM_DSI_VIDEO_ENCODER_ID = 0,
264 MSM_DSI_CMD_ENCODER_ID = 1,
265 MSM_DSI_ENCODER_NUM = 2
266};
267#ifdef CONFIG_DRM_MSM_DSI
268void __init msm_dsi_register(void);
269void __exit msm_dsi_unregister(void);
270int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
271 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
272#else
273static inline void __init msm_dsi_register(void)
274{
275}
276static inline void __exit msm_dsi_unregister(void)
277{
278}
279static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
280 struct drm_device *dev,
281 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
282{
283 return -EINVAL;
284}
285#endif
286
287#ifdef CONFIG_DEBUG_FS
288void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
289void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
290void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
291int msm_debugfs_late_init(struct drm_device *dev);
292int msm_rd_debugfs_init(struct drm_minor *minor);
293void msm_rd_debugfs_cleanup(struct drm_minor *minor);
294void msm_rd_dump_submit(struct msm_gem_submit *submit);
295int msm_perf_debugfs_init(struct drm_minor *minor);
296void msm_perf_debugfs_cleanup(struct drm_minor *minor);
297#else
298static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
299static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
300#endif
301
302void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
303 const char *dbgname);
304void msm_writel(u32 data, void __iomem *addr);
305u32 msm_readl(const void __iomem *addr);
306
307#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
308#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
309
310static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
311{
312 struct msm_drm_private *priv = dev->dev_private;
313 return priv->completed_fence >= fence;
314}
315
316static inline int align_pitch(int width, int bpp)
317{
318 int bytespp = (bpp + 7) / 8;
319 /* adreno needs pitch aligned to 32 pixels: */
320 return bytespp * ALIGN(width, 32);
321}
322
323/* for the generated headers: */
324#define INVALID_IDX(idx) ({BUG(); 0;})
325#define fui(x) ({BUG(); 0;})
326#define util_float_to_half(x) ({BUG(); 0;})
327
328
329#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
330
331/* for conditionally setting boolean flag(s): */
332#define COND(bool, val) ((bool) ? (val) : 0)
333
334
335#endif /* __MSM_DRV_H__ */