Linux kernel mirror (for testing)
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1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
41#include <linux/slab.h>
42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
44
45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
87 MLX5_MAX_IRQ_NAME = 32
88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
101enum {
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
106 MLX5_REG_PFCC = 0x5007,
107 MLX5_REG_PPCNT = 0x5008,
108 MLX5_REG_PMAOS = 0x5012,
109 MLX5_REG_PUDE = 0x5009,
110 MLX5_REG_PMPE = 0x5010,
111 MLX5_REG_PELC = 0x500e,
112 MLX5_REG_PVLC = 0x500f,
113 MLX5_REG_PMLP = 0, /* TBD */
114 MLX5_REG_NODE_DESC = 0x6001,
115 MLX5_REG_HOST_ENDIANNESS = 0x7004,
116};
117
118enum mlx5_page_fault_resume_flags {
119 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
120 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
121 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
122 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
123};
124
125enum dbg_rsc_type {
126 MLX5_DBG_RSC_QP,
127 MLX5_DBG_RSC_EQ,
128 MLX5_DBG_RSC_CQ,
129};
130
131struct mlx5_field_desc {
132 struct dentry *dent;
133 int i;
134};
135
136struct mlx5_rsc_debug {
137 struct mlx5_core_dev *dev;
138 void *object;
139 enum dbg_rsc_type type;
140 struct dentry *root;
141 struct mlx5_field_desc fields[0];
142};
143
144enum mlx5_dev_event {
145 MLX5_DEV_EVENT_SYS_ERROR,
146 MLX5_DEV_EVENT_PORT_UP,
147 MLX5_DEV_EVENT_PORT_DOWN,
148 MLX5_DEV_EVENT_PORT_INITIALIZED,
149 MLX5_DEV_EVENT_LID_CHANGE,
150 MLX5_DEV_EVENT_PKEY_CHANGE,
151 MLX5_DEV_EVENT_GUID_CHANGE,
152 MLX5_DEV_EVENT_CLIENT_REREG,
153};
154
155enum mlx5_port_status {
156 MLX5_PORT_UP = 1,
157 MLX5_PORT_DOWN = 2,
158};
159
160struct mlx5_uuar_info {
161 struct mlx5_uar *uars;
162 int num_uars;
163 int num_low_latency_uuars;
164 unsigned long *bitmap;
165 unsigned int *count;
166 struct mlx5_bf *bfs;
167
168 /*
169 * protect uuar allocation data structs
170 */
171 struct mutex lock;
172 u32 ver;
173};
174
175struct mlx5_bf {
176 void __iomem *reg;
177 void __iomem *regreg;
178 int buf_size;
179 struct mlx5_uar *uar;
180 unsigned long offset;
181 int need_lock;
182 /* protect blue flame buffer selection when needed
183 */
184 spinlock_t lock;
185
186 /* serialize 64 bit writes when done as two 32 bit accesses
187 */
188 spinlock_t lock32;
189 int uuarn;
190};
191
192struct mlx5_cmd_first {
193 __be32 data[4];
194};
195
196struct mlx5_cmd_msg {
197 struct list_head list;
198 struct cache_ent *cache;
199 u32 len;
200 struct mlx5_cmd_first first;
201 struct mlx5_cmd_mailbox *next;
202};
203
204struct mlx5_cmd_debug {
205 struct dentry *dbg_root;
206 struct dentry *dbg_in;
207 struct dentry *dbg_out;
208 struct dentry *dbg_outlen;
209 struct dentry *dbg_status;
210 struct dentry *dbg_run;
211 void *in_msg;
212 void *out_msg;
213 u8 status;
214 u16 inlen;
215 u16 outlen;
216};
217
218struct cache_ent {
219 /* protect block chain allocations
220 */
221 spinlock_t lock;
222 struct list_head head;
223};
224
225struct cmd_msg_cache {
226 struct cache_ent large;
227 struct cache_ent med;
228
229};
230
231struct mlx5_cmd_stats {
232 u64 sum;
233 u64 n;
234 struct dentry *root;
235 struct dentry *avg;
236 struct dentry *count;
237 /* protect command average calculations */
238 spinlock_t lock;
239};
240
241struct mlx5_cmd {
242 void *cmd_alloc_buf;
243 dma_addr_t alloc_dma;
244 int alloc_size;
245 void *cmd_buf;
246 dma_addr_t dma;
247 u16 cmdif_rev;
248 u8 log_sz;
249 u8 log_stride;
250 int max_reg_cmds;
251 int events;
252 u32 __iomem *vector;
253
254 /* protect command queue allocations
255 */
256 spinlock_t alloc_lock;
257
258 /* protect token allocations
259 */
260 spinlock_t token_lock;
261 u8 token;
262 unsigned long bitmask;
263 char wq_name[MLX5_CMD_WQ_MAX_NAME];
264 struct workqueue_struct *wq;
265 struct semaphore sem;
266 struct semaphore pages_sem;
267 int mode;
268 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
269 struct pci_pool *pool;
270 struct mlx5_cmd_debug dbg;
271 struct cmd_msg_cache cache;
272 int checksum_disabled;
273 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
274};
275
276struct mlx5_port_caps {
277 int gid_table_len;
278 int pkey_table_len;
279 u8 ext_port_cap;
280};
281
282struct mlx5_cmd_mailbox {
283 void *buf;
284 dma_addr_t dma;
285 struct mlx5_cmd_mailbox *next;
286};
287
288struct mlx5_buf_list {
289 void *buf;
290 dma_addr_t map;
291};
292
293struct mlx5_buf {
294 struct mlx5_buf_list direct;
295 int npages;
296 int size;
297 u8 page_shift;
298};
299
300struct mlx5_eq {
301 struct mlx5_core_dev *dev;
302 __be32 __iomem *doorbell;
303 u32 cons_index;
304 struct mlx5_buf buf;
305 int size;
306 u8 irqn;
307 u8 eqn;
308 int nent;
309 u64 mask;
310 struct list_head list;
311 int index;
312 struct mlx5_rsc_debug *dbg;
313};
314
315struct mlx5_core_psv {
316 u32 psv_idx;
317 struct psv_layout {
318 u32 pd;
319 u16 syndrome;
320 u16 reserved;
321 u16 bg;
322 u16 app_tag;
323 u32 ref_tag;
324 } psv;
325};
326
327struct mlx5_core_sig_ctx {
328 struct mlx5_core_psv psv_memory;
329 struct mlx5_core_psv psv_wire;
330 struct ib_sig_err err_item;
331 bool sig_status_checked;
332 bool sig_err_exists;
333 u32 sigerr_count;
334};
335
336struct mlx5_core_mr {
337 u64 iova;
338 u64 size;
339 u32 key;
340 u32 pd;
341};
342
343enum mlx5_res_type {
344 MLX5_RES_QP,
345 MLX5_RES_SRQ,
346 MLX5_RES_XSRQ,
347};
348
349struct mlx5_core_rsc_common {
350 enum mlx5_res_type res;
351 atomic_t refcount;
352 struct completion free;
353};
354
355struct mlx5_core_srq {
356 struct mlx5_core_rsc_common common; /* must be first */
357 u32 srqn;
358 int max;
359 int max_gs;
360 int max_avail_gather;
361 int wqe_shift;
362 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
363
364 atomic_t refcount;
365 struct completion free;
366};
367
368struct mlx5_eq_table {
369 void __iomem *update_ci;
370 void __iomem *update_arm_ci;
371 struct list_head comp_eqs_list;
372 struct mlx5_eq pages_eq;
373 struct mlx5_eq async_eq;
374 struct mlx5_eq cmd_eq;
375 int num_comp_vectors;
376 /* protect EQs list
377 */
378 spinlock_t lock;
379};
380
381struct mlx5_uar {
382 u32 index;
383 struct list_head bf_list;
384 unsigned free_bf_bmap;
385 void __iomem *bf_map;
386 void __iomem *map;
387};
388
389
390struct mlx5_core_health {
391 struct health_buffer __iomem *health;
392 __be32 __iomem *health_counter;
393 struct timer_list timer;
394 struct list_head list;
395 u32 prev;
396 int miss_counter;
397};
398
399struct mlx5_cq_table {
400 /* protect radix tree
401 */
402 spinlock_t lock;
403 struct radix_tree_root tree;
404};
405
406struct mlx5_qp_table {
407 /* protect radix tree
408 */
409 spinlock_t lock;
410 struct radix_tree_root tree;
411};
412
413struct mlx5_srq_table {
414 /* protect radix tree
415 */
416 spinlock_t lock;
417 struct radix_tree_root tree;
418};
419
420struct mlx5_mr_table {
421 /* protect radix tree
422 */
423 rwlock_t lock;
424 struct radix_tree_root tree;
425};
426
427struct mlx5_irq_info {
428 cpumask_var_t mask;
429 char name[MLX5_MAX_IRQ_NAME];
430};
431
432struct mlx5_priv {
433 char name[MLX5_MAX_NAME_LEN];
434 struct mlx5_eq_table eq_table;
435 struct msix_entry *msix_arr;
436 struct mlx5_irq_info *irq_info;
437 struct mlx5_uuar_info uuari;
438 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
439
440 struct io_mapping *bf_mapping;
441
442 /* pages stuff */
443 struct workqueue_struct *pg_wq;
444 struct rb_root page_root;
445 int fw_pages;
446 atomic_t reg_pages;
447 struct list_head free_list;
448
449 struct mlx5_core_health health;
450
451 struct mlx5_srq_table srq_table;
452
453 /* start: qp staff */
454 struct mlx5_qp_table qp_table;
455 struct dentry *qp_debugfs;
456 struct dentry *eq_debugfs;
457 struct dentry *cq_debugfs;
458 struct dentry *cmdif_debugfs;
459 /* end: qp staff */
460
461 /* start: cq staff */
462 struct mlx5_cq_table cq_table;
463 /* end: cq staff */
464
465 /* start: mr staff */
466 struct mlx5_mr_table mr_table;
467 /* end: mr staff */
468
469 /* start: alloc staff */
470 /* protect buffer alocation according to numa node */
471 struct mutex alloc_mutex;
472 int numa_node;
473
474 struct mutex pgdir_mutex;
475 struct list_head pgdir_list;
476 /* end: alloc staff */
477 struct dentry *dbg_root;
478
479 /* protect mkey key part */
480 spinlock_t mkey_lock;
481 u8 mkey_key;
482
483 struct list_head dev_list;
484 struct list_head ctx_list;
485 spinlock_t ctx_lock;
486};
487
488struct mlx5_core_dev {
489 struct pci_dev *pdev;
490 u8 rev_id;
491 char board_id[MLX5_BOARD_ID_LEN];
492 struct mlx5_cmd cmd;
493 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
494 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
495 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
496 phys_addr_t iseg_base;
497 struct mlx5_init_seg __iomem *iseg;
498 void (*event) (struct mlx5_core_dev *dev,
499 enum mlx5_dev_event event,
500 unsigned long param);
501 struct mlx5_priv priv;
502 struct mlx5_profile *profile;
503 atomic_t num_qps;
504 u32 issi;
505};
506
507struct mlx5_db {
508 __be32 *db;
509 union {
510 struct mlx5_db_pgdir *pgdir;
511 struct mlx5_ib_user_db_page *user_page;
512 } u;
513 dma_addr_t dma;
514 int index;
515};
516
517enum {
518 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
519};
520
521enum {
522 MLX5_COMP_EQ_SIZE = 1024,
523};
524
525enum {
526 MLX5_PTYS_IB = 1 << 0,
527 MLX5_PTYS_EN = 1 << 2,
528};
529
530struct mlx5_db_pgdir {
531 struct list_head list;
532 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
533 __be32 *db_page;
534 dma_addr_t db_dma;
535};
536
537typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
538
539struct mlx5_cmd_work_ent {
540 struct mlx5_cmd_msg *in;
541 struct mlx5_cmd_msg *out;
542 void *uout;
543 int uout_size;
544 mlx5_cmd_cbk_t callback;
545 void *context;
546 int idx;
547 struct completion done;
548 struct mlx5_cmd *cmd;
549 struct work_struct work;
550 struct mlx5_cmd_layout *lay;
551 int ret;
552 int page_queue;
553 u8 status;
554 u8 token;
555 u64 ts1;
556 u64 ts2;
557 u16 op;
558};
559
560struct mlx5_pas {
561 u64 pa;
562 u8 log_sz;
563};
564
565enum port_state_policy {
566 MLX5_AAA_000
567};
568
569enum phy_port_state {
570 MLX5_AAA_111
571};
572
573struct mlx5_hca_vport_context {
574 u32 field_select;
575 bool sm_virt_aware;
576 bool has_smi;
577 bool has_raw;
578 enum port_state_policy policy;
579 enum phy_port_state phys_state;
580 enum ib_port_state vport_state;
581 u8 port_physical_state;
582 u64 sys_image_guid;
583 u64 port_guid;
584 u64 node_guid;
585 u32 cap_mask1;
586 u32 cap_mask1_perm;
587 u32 cap_mask2;
588 u32 cap_mask2_perm;
589 u16 lid;
590 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
591 u8 lmc;
592 u8 subnet_timeout;
593 u16 sm_lid;
594 u8 sm_sl;
595 u16 qkey_violation_counter;
596 u16 pkey_violation_counter;
597 bool grh_required;
598};
599
600static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
601{
602 return buf->direct.buf + offset;
603}
604
605extern struct workqueue_struct *mlx5_core_wq;
606
607#define STRUCT_FIELD(header, field) \
608 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
609 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
610
611struct ib_field {
612 size_t struct_offset_bytes;
613 size_t struct_size_bytes;
614 int offset_bits;
615 int size_bits;
616};
617
618static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
619{
620 return pci_get_drvdata(pdev);
621}
622
623extern struct dentry *mlx5_debugfs_root;
624
625static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
626{
627 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
628}
629
630static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
631{
632 return ioread32be(&dev->iseg->fw_rev) >> 16;
633}
634
635static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
636{
637 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
638}
639
640static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
641{
642 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
643}
644
645static inline void *mlx5_vzalloc(unsigned long size)
646{
647 void *rtn;
648
649 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
650 if (!rtn)
651 rtn = vzalloc(size);
652 return rtn;
653}
654
655static inline u32 mlx5_base_mkey(const u32 key)
656{
657 return key & 0xffffff00u;
658}
659
660int mlx5_cmd_init(struct mlx5_core_dev *dev);
661void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
662void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
663void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
664int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
665int mlx5_cmd_status_to_err_v2(void *ptr);
666int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
667 enum mlx5_cap_mode cap_mode);
668int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
669 int out_size);
670int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
671 void *out, int out_size, mlx5_cmd_cbk_t callback,
672 void *context);
673int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
674int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
675int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
676int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
677int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
678void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
679void mlx5_health_cleanup(void);
680void __init mlx5_health_init(void);
681void mlx5_start_health_poll(struct mlx5_core_dev *dev);
682void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
683int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
684 struct mlx5_buf *buf, int node);
685int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
686void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
687struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
688 gfp_t flags, int npages);
689void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
690 struct mlx5_cmd_mailbox *head);
691int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
692 struct mlx5_create_srq_mbox_in *in, int inlen,
693 int is_xrc);
694int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
695int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
696 struct mlx5_query_srq_mbox_out *out);
697int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
698 u16 lwm, int is_srq);
699void mlx5_init_mr_table(struct mlx5_core_dev *dev);
700void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
701int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
702 struct mlx5_create_mkey_mbox_in *in, int inlen,
703 mlx5_cmd_cbk_t callback, void *context,
704 struct mlx5_create_mkey_mbox_out *out);
705int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
706int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
707 struct mlx5_query_mkey_mbox_out *out, int outlen);
708int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
709 u32 *mkey);
710int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
711int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
712int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
713 u16 opmod, u8 port);
714void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
715void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
716int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
717void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
718void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
719 s32 npages);
720int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
721int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
722void mlx5_register_debugfs(void);
723void mlx5_unregister_debugfs(void);
724int mlx5_eq_init(struct mlx5_core_dev *dev);
725void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
726void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
727void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
728void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
729#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
730void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
731#endif
732void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
733struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
734void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
735void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
736int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
737 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
738int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
739int mlx5_start_eqs(struct mlx5_core_dev *dev);
740int mlx5_stop_eqs(struct mlx5_core_dev *dev);
741int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
742int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
743int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
744
745int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
746void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
747int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
748 int size_in, void *data_out, int size_out,
749 u16 reg_num, int arg, int write);
750
751int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
752int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
753 int ptys_size, int proto_mask, u8 local_port);
754int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
755 u32 *proto_cap, int proto_mask);
756int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
757 u32 *proto_admin, int proto_mask);
758int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
759 u8 *link_width_oper, u8 local_port);
760int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
761 u8 *proto_oper, int proto_mask,
762 u8 local_port);
763int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
764 int proto_mask);
765int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
766 enum mlx5_port_status status);
767int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
768 enum mlx5_port_status *status);
769
770int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
771void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
772void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
773 u8 port);
774
775int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
776 u8 *vl_hw_cap, u8 local_port);
777
778int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
779int mlx5_query_port_pause(struct mlx5_core_dev *dev,
780 u32 *rx_pause, u32 *tx_pause);
781
782int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
783void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
784int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
785 struct mlx5_query_eq_mbox_out *out, int outlen);
786int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
787void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
788int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
789void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
790int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
791int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
792 int node);
793void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
794
795const char *mlx5_command_str(int command);
796int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
797void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
798int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
799 int npsvs, u32 *sig_index);
800int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
801void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
802int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
803 struct mlx5_odp_caps *odp_caps);
804
805static inline u32 mlx5_mkey_to_idx(u32 mkey)
806{
807 return mkey >> 8;
808}
809
810static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
811{
812 return mkey_idx << 8;
813}
814
815static inline u8 mlx5_mkey_variant(u32 mkey)
816{
817 return mkey & 0xff;
818}
819
820enum {
821 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
822 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
823};
824
825enum {
826 MAX_MR_CACHE_ENTRIES = 16,
827};
828
829enum {
830 MLX5_INTERFACE_PROTOCOL_IB = 0,
831 MLX5_INTERFACE_PROTOCOL_ETH = 1,
832};
833
834struct mlx5_interface {
835 void * (*add)(struct mlx5_core_dev *dev);
836 void (*remove)(struct mlx5_core_dev *dev, void *context);
837 void (*event)(struct mlx5_core_dev *dev, void *context,
838 enum mlx5_dev_event event, unsigned long param);
839 void * (*get_dev)(void *context);
840 int protocol;
841 struct list_head list;
842};
843
844void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
845int mlx5_register_interface(struct mlx5_interface *intf);
846void mlx5_unregister_interface(struct mlx5_interface *intf);
847int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
848
849struct mlx5_profile {
850 u64 mask;
851 u8 log_max_qp;
852 struct {
853 int size;
854 int limit;
855 } mr_cache[MAX_MR_CACHE_ENTRIES];
856};
857
858static inline int mlx5_get_gid_table_len(u16 param)
859{
860 if (param > 4) {
861 pr_warn("gid table length is zero\n");
862 return 0;
863 }
864
865 return 8 * (1 << param);
866}
867
868#endif /* MLX5_DRIVER_H */