tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/firmware.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/reset.h>
13
14#include <drm/drmP.h>
15#include <drm/drm_fb_cma_helper.h>
16#include <drm/drm_gem_cma_helper.h>
17
18#include "sti_compositor.h"
19#include "sti_hqvdp_lut.h"
20#include "sti_plane.h"
21#include "sti_vtg.h"
22
23/* Firmware name */
24#define HQVDP_FMW_NAME "hqvdp-stih407.bin"
25
26/* Regs address */
27#define HQVDP_DMEM 0x00000000 /* 0x00000000 */
28#define HQVDP_PMEM 0x00040000 /* 0x00040000 */
29#define HQVDP_RD_PLUG 0x000E0000 /* 0x000E0000 */
30#define HQVDP_RD_PLUG_CONTROL (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */
31#define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */
32#define HQVDP_RD_PLUG_MIN_OPC (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */
33#define HQVDP_RD_PLUG_MAX_OPC (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */
34#define HQVDP_RD_PLUG_MAX_CHK (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */
35#define HQVDP_RD_PLUG_MAX_MSG (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */
36#define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */
37#define HQVDP_WR_PLUG 0x000E2000 /* 0x000E2000 */
38#define HQVDP_WR_PLUG_CONTROL (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */
39#define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */
40#define HQVDP_WR_PLUG_MIN_OPC (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */
41#define HQVDP_WR_PLUG_MAX_OPC (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */
42#define HQVDP_WR_PLUG_MAX_CHK (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */
43#define HQVDP_WR_PLUG_MAX_MSG (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */
44#define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */
45#define HQVDP_MBX 0x000E4000 /* 0x000E4000 */
46#define HQVDP_MBX_IRQ_TO_XP70 (HQVDP_MBX + 0x0000) /* 0x000E4000 */
47#define HQVDP_MBX_INFO_HOST (HQVDP_MBX + 0x0004) /* 0x000E4004 */
48#define HQVDP_MBX_IRQ_TO_HOST (HQVDP_MBX + 0x0008) /* 0x000E4008 */
49#define HQVDP_MBX_INFO_XP70 (HQVDP_MBX + 0x000C) /* 0x000E400C */
50#define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010) /* 0x000E4010 */
51#define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014) /* 0x000E4014 */
52#define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018) /* 0x000E4018 */
53#define HQVDP_MBX_GP_STATUS (HQVDP_MBX + 0x001C) /* 0x000E401C */
54#define HQVDP_MBX_NEXT_CMD (HQVDP_MBX + 0x0020) /* 0x000E4020 */
55#define HQVDP_MBX_CURRENT_CMD (HQVDP_MBX + 0x0024) /* 0x000E4024 */
56#define HQVDP_MBX_SOFT_VSYNC (HQVDP_MBX + 0x0028) /* 0x000E4028 */
57
58/* Plugs config */
59#define PLUG_CONTROL_ENABLE 0x00000001
60#define PLUG_PAGE_SIZE_256 0x00000002
61#define PLUG_MIN_OPC_8 0x00000003
62#define PLUG_MAX_OPC_64 0x00000006
63#define PLUG_MAX_CHK_2X 0x00000001
64#define PLUG_MAX_MSG_1X 0x00000000
65#define PLUG_MIN_SPACE_1 0x00000000
66
67/* SW reset CTRL */
68#define SW_RESET_CTRL_FULL BIT(0)
69#define SW_RESET_CTRL_CORE BIT(1)
70
71/* Startup ctrl 1 */
72#define STARTUP_CTRL1_RST_DONE BIT(0)
73#define STARTUP_CTRL1_AUTH_IDLE BIT(2)
74
75/* Startup ctrl 2 */
76#define STARTUP_CTRL2_FETCH_EN BIT(1)
77
78/* Info xP70 */
79#define INFO_XP70_FW_READY BIT(15)
80#define INFO_XP70_FW_PROCESSING BIT(14)
81#define INFO_XP70_FW_INITQUEUES BIT(13)
82
83/* SOFT_VSYNC */
84#define SOFT_VSYNC_HW 0x00000000
85#define SOFT_VSYNC_SW_CMD 0x00000001
86#define SOFT_VSYNC_SW_CTRL_IRQ 0x00000003
87
88/* Reset & boot poll config */
89#define POLL_MAX_ATTEMPT 50
90#define POLL_DELAY_MS 20
91
92#define SCALE_FACTOR 8192
93#define SCALE_MAX_FOR_LEG_LUT_F 4096
94#define SCALE_MAX_FOR_LEG_LUT_E 4915
95#define SCALE_MAX_FOR_LEG_LUT_D 6654
96#define SCALE_MAX_FOR_LEG_LUT_C 8192
97
98enum sti_hvsrc_orient {
99 HVSRC_HORI,
100 HVSRC_VERT
101};
102
103/* Command structures */
104struct sti_hqvdp_top {
105 u32 config;
106 u32 mem_format;
107 u32 current_luma;
108 u32 current_enh_luma;
109 u32 current_right_luma;
110 u32 current_enh_right_luma;
111 u32 current_chroma;
112 u32 current_enh_chroma;
113 u32 current_right_chroma;
114 u32 current_enh_right_chroma;
115 u32 output_luma;
116 u32 output_chroma;
117 u32 luma_src_pitch;
118 u32 luma_enh_src_pitch;
119 u32 luma_right_src_pitch;
120 u32 luma_enh_right_src_pitch;
121 u32 chroma_src_pitch;
122 u32 chroma_enh_src_pitch;
123 u32 chroma_right_src_pitch;
124 u32 chroma_enh_right_src_pitch;
125 u32 luma_processed_pitch;
126 u32 chroma_processed_pitch;
127 u32 input_frame_size;
128 u32 input_viewport_ori;
129 u32 input_viewport_ori_right;
130 u32 input_viewport_size;
131 u32 left_view_border_width;
132 u32 right_view_border_width;
133 u32 left_view_3d_offset_width;
134 u32 right_view_3d_offset_width;
135 u32 side_stripe_color;
136 u32 crc_reset_ctrl;
137};
138
139/* Configs for interlaced : no IT, no pass thru, 3 fields */
140#define TOP_CONFIG_INTER_BTM 0x00000000
141#define TOP_CONFIG_INTER_TOP 0x00000002
142
143/* Config for progressive : no IT, no pass thru, 3 fields */
144#define TOP_CONFIG_PROGRESSIVE 0x00000001
145
146/* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */
147#define TOP_MEM_FORMAT_DFLT 0x00018060
148
149/* Min/Max size */
150#define MAX_WIDTH 0x1FFF
151#define MAX_HEIGHT 0x0FFF
152#define MIN_WIDTH 0x0030
153#define MIN_HEIGHT 0x0010
154
155struct sti_hqvdp_vc1re {
156 u32 ctrl_prv_csdi;
157 u32 ctrl_cur_csdi;
158 u32 ctrl_nxt_csdi;
159 u32 ctrl_cur_fmd;
160 u32 ctrl_nxt_fmd;
161};
162
163struct sti_hqvdp_fmd {
164 u32 config;
165 u32 viewport_ori;
166 u32 viewport_size;
167 u32 next_next_luma;
168 u32 next_next_right_luma;
169 u32 next_next_next_luma;
170 u32 next_next_next_right_luma;
171 u32 threshold_scd;
172 u32 threshold_rfd;
173 u32 threshold_move;
174 u32 threshold_cfd;
175};
176
177struct sti_hqvdp_csdi {
178 u32 config;
179 u32 config2;
180 u32 dcdi_config;
181 u32 prev_luma;
182 u32 prev_enh_luma;
183 u32 prev_right_luma;
184 u32 prev_enh_right_luma;
185 u32 next_luma;
186 u32 next_enh_luma;
187 u32 next_right_luma;
188 u32 next_enh_right_luma;
189 u32 prev_chroma;
190 u32 prev_enh_chroma;
191 u32 prev_right_chroma;
192 u32 prev_enh_right_chroma;
193 u32 next_chroma;
194 u32 next_enh_chroma;
195 u32 next_right_chroma;
196 u32 next_enh_right_chroma;
197 u32 prev_motion;
198 u32 prev_right_motion;
199 u32 cur_motion;
200 u32 cur_right_motion;
201 u32 next_motion;
202 u32 next_right_motion;
203};
204
205/* Config for progressive: by pass */
206#define CSDI_CONFIG_PROG 0x00000000
207/* Config for directional deinterlacing without motion */
208#define CSDI_CONFIG_INTER_DIR 0x00000016
209/* Additional configs for fader, blender, motion,... deinterlace algorithms */
210#define CSDI_CONFIG2_DFLT 0x000001B3
211#define CSDI_DCDI_CONFIG_DFLT 0x00203803
212
213struct sti_hqvdp_hvsrc {
214 u32 hor_panoramic_ctrl;
215 u32 output_picture_size;
216 u32 init_horizontal;
217 u32 init_vertical;
218 u32 param_ctrl;
219 u32 yh_coef[NB_COEF];
220 u32 ch_coef[NB_COEF];
221 u32 yv_coef[NB_COEF];
222 u32 cv_coef[NB_COEF];
223 u32 hori_shift;
224 u32 vert_shift;
225};
226
227/* Default ParamCtrl: all controls enabled */
228#define HVSRC_PARAM_CTRL_DFLT 0xFFFFFFFF
229
230struct sti_hqvdp_iqi {
231 u32 config;
232 u32 demo_wind_size;
233 u32 pk_config;
234 u32 coeff0_coeff1;
235 u32 coeff2_coeff3;
236 u32 coeff4;
237 u32 pk_lut;
238 u32 pk_gain;
239 u32 pk_coring_level;
240 u32 cti_config;
241 u32 le_config;
242 u32 le_lut[64];
243 u32 con_bri;
244 u32 sat_gain;
245 u32 pxf_conf;
246 u32 default_color;
247};
248
249/* Default Config : IQI bypassed */
250#define IQI_CONFIG_DFLT 0x00000001
251/* Default Contrast & Brightness gain = 256 */
252#define IQI_CON_BRI_DFLT 0x00000100
253/* Default Saturation gain = 256 */
254#define IQI_SAT_GAIN_DFLT 0x00000100
255/* Default PxfConf : P2I bypassed */
256#define IQI_PXF_CONF_DFLT 0x00000001
257
258struct sti_hqvdp_top_status {
259 u32 processing_time;
260 u32 input_y_crc;
261 u32 input_uv_crc;
262};
263
264struct sti_hqvdp_fmd_status {
265 u32 fmd_repeat_move_status;
266 u32 fmd_scene_count_status;
267 u32 cfd_sum;
268 u32 field_sum;
269 u32 next_y_fmd_crc;
270 u32 next_next_y_fmd_crc;
271 u32 next_next_next_y_fmd_crc;
272};
273
274struct sti_hqvdp_csdi_status {
275 u32 prev_y_csdi_crc;
276 u32 cur_y_csdi_crc;
277 u32 next_y_csdi_crc;
278 u32 prev_uv_csdi_crc;
279 u32 cur_uv_csdi_crc;
280 u32 next_uv_csdi_crc;
281 u32 y_csdi_crc;
282 u32 uv_csdi_crc;
283 u32 uv_cup_crc;
284 u32 mot_csdi_crc;
285 u32 mot_cur_csdi_crc;
286 u32 mot_prev_csdi_crc;
287};
288
289struct sti_hqvdp_hvsrc_status {
290 u32 y_hvsrc_crc;
291 u32 u_hvsrc_crc;
292 u32 v_hvsrc_crc;
293};
294
295struct sti_hqvdp_iqi_status {
296 u32 pxf_it_status;
297 u32 y_iqi_crc;
298 u32 u_iqi_crc;
299 u32 v_iqi_crc;
300};
301
302/* Main commands. We use 2 commands one being processed by the firmware, one
303 * ready to be fetched upon next Vsync*/
304#define NB_VDP_CMD 2
305
306struct sti_hqvdp_cmd {
307 struct sti_hqvdp_top top;
308 struct sti_hqvdp_vc1re vc1re;
309 struct sti_hqvdp_fmd fmd;
310 struct sti_hqvdp_csdi csdi;
311 struct sti_hqvdp_hvsrc hvsrc;
312 struct sti_hqvdp_iqi iqi;
313 struct sti_hqvdp_top_status top_status;
314 struct sti_hqvdp_fmd_status fmd_status;
315 struct sti_hqvdp_csdi_status csdi_status;
316 struct sti_hqvdp_hvsrc_status hvsrc_status;
317 struct sti_hqvdp_iqi_status iqi_status;
318};
319
320/*
321 * STI HQVDP structure
322 *
323 * @dev: driver device
324 * @drm_dev: the drm device
325 * @regs: registers
326 * @plane: plane structure for hqvdp it self
327 * @clk: IP clock
328 * @clk_pix_main: pix main clock
329 * @reset: reset control
330 * @vtg_nb: notifier to handle VTG Vsync
331 * @btm_field_pending: is there any bottom field (interlaced frame) to display
332 * @curr_field_count: number of field updates
333 * @last_field_count: number of field updates since last fps measure
334 * @hqvdp_cmd: buffer of commands
335 * @hqvdp_cmd_paddr: physical address of hqvdp_cmd
336 * @vtg: vtg for main data path
337 * @xp70_initialized: true if xp70 is already initialized
338 */
339struct sti_hqvdp {
340 struct device *dev;
341 struct drm_device *drm_dev;
342 void __iomem *regs;
343 struct sti_plane plane;
344 struct clk *clk;
345 struct clk *clk_pix_main;
346 struct reset_control *reset;
347 struct notifier_block vtg_nb;
348 bool btm_field_pending;
349 unsigned int curr_field_count;
350 unsigned int last_field_count;
351 void *hqvdp_cmd;
352 dma_addr_t hqvdp_cmd_paddr;
353 struct sti_vtg *vtg;
354 bool xp70_initialized;
355};
356
357#define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane)
358
359static const uint32_t hqvdp_supported_formats[] = {
360 DRM_FORMAT_NV12,
361};
362
363/**
364 * sti_hqvdp_get_free_cmd
365 * @hqvdp: hqvdp structure
366 *
367 * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW.
368 *
369 * RETURNS:
370 * the offset of the command to be used.
371 * -1 in error cases
372 */
373static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp)
374{
375 int curr_cmd, next_cmd;
376 dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr;
377 int i;
378
379 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
380 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
381
382 for (i = 0; i < NB_VDP_CMD; i++) {
383 if ((cmd != curr_cmd) && (cmd != next_cmd))
384 return i * sizeof(struct sti_hqvdp_cmd);
385 cmd += sizeof(struct sti_hqvdp_cmd);
386 }
387
388 return -1;
389}
390
391/**
392 * sti_hqvdp_get_curr_cmd
393 * @hqvdp: hqvdp structure
394 *
395 * Look for the hqvdp_cmd that is being used by the FW.
396 *
397 * RETURNS:
398 * the offset of the command to be used.
399 * -1 in error cases
400 */
401static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp)
402{
403 int curr_cmd;
404 dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr;
405 unsigned int i;
406
407 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
408
409 for (i = 0; i < NB_VDP_CMD; i++) {
410 if (cmd == curr_cmd)
411 return i * sizeof(struct sti_hqvdp_cmd);
412
413 cmd += sizeof(struct sti_hqvdp_cmd);
414 }
415
416 return -1;
417}
418
419/**
420 * sti_hqvdp_update_hvsrc
421 * @orient: horizontal or vertical
422 * @scale: scaling/zoom factor
423 * @hvsrc: the structure containing the LUT coef
424 *
425 * Update the Y and C Lut coef, as well as the shift param
426 *
427 * RETURNS:
428 * None.
429 */
430static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale,
431 struct sti_hqvdp_hvsrc *hvsrc)
432{
433 const int *coef_c, *coef_y;
434 int shift_c, shift_y;
435
436 /* Get the appropriate coef tables */
437 if (scale < SCALE_MAX_FOR_LEG_LUT_F) {
438 coef_y = coef_lut_f_y_legacy;
439 coef_c = coef_lut_f_c_legacy;
440 shift_y = SHIFT_LUT_F_Y_LEGACY;
441 shift_c = SHIFT_LUT_F_C_LEGACY;
442 } else if (scale < SCALE_MAX_FOR_LEG_LUT_E) {
443 coef_y = coef_lut_e_y_legacy;
444 coef_c = coef_lut_e_c_legacy;
445 shift_y = SHIFT_LUT_E_Y_LEGACY;
446 shift_c = SHIFT_LUT_E_C_LEGACY;
447 } else if (scale < SCALE_MAX_FOR_LEG_LUT_D) {
448 coef_y = coef_lut_d_y_legacy;
449 coef_c = coef_lut_d_c_legacy;
450 shift_y = SHIFT_LUT_D_Y_LEGACY;
451 shift_c = SHIFT_LUT_D_C_LEGACY;
452 } else if (scale < SCALE_MAX_FOR_LEG_LUT_C) {
453 coef_y = coef_lut_c_y_legacy;
454 coef_c = coef_lut_c_c_legacy;
455 shift_y = SHIFT_LUT_C_Y_LEGACY;
456 shift_c = SHIFT_LUT_C_C_LEGACY;
457 } else if (scale == SCALE_MAX_FOR_LEG_LUT_C) {
458 coef_y = coef_c = coef_lut_b;
459 shift_y = shift_c = SHIFT_LUT_B;
460 } else {
461 coef_y = coef_c = coef_lut_a_legacy;
462 shift_y = shift_c = SHIFT_LUT_A_LEGACY;
463 }
464
465 if (orient == HVSRC_HORI) {
466 hvsrc->hori_shift = (shift_c << 16) | shift_y;
467 memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef));
468 memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef));
469 } else {
470 hvsrc->vert_shift = (shift_c << 16) | shift_y;
471 memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef));
472 memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef));
473 }
474}
475
476/**
477 * sti_hqvdp_check_hw_scaling
478 * @hqvdp: hqvdp pointer
479 * @mode: display mode with timing constraints
480 * @src_w: source width
481 * @src_h: source height
482 * @dst_w: destination width
483 * @dst_h: destination height
484 *
485 * Check if the HW is able to perform the scaling request
486 * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where:
487 * Zy = OutputHeight / InputHeight
488 * LFW = (Tx * IPClock) / (MaxNbCycles * Cp)
489 * Tx : Total video mode horizontal resolution
490 * IPClock : HQVDP IP clock (Mhz)
491 * MaxNbCycles: max(InputWidth, OutputWidth)
492 * Cp: Video mode pixel clock (Mhz)
493 *
494 * RETURNS:
495 * True if the HW can scale.
496 */
497static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp *hqvdp,
498 struct drm_display_mode *mode,
499 int src_w, int src_h,
500 int dst_w, int dst_h)
501{
502 unsigned long lfw;
503 unsigned int inv_zy;
504
505 lfw = mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000);
506 lfw /= max(src_w, dst_w) * mode->clock / 1000;
507
508 inv_zy = DIV_ROUND_UP(src_h, dst_h);
509
510 return (inv_zy <= lfw) ? true : false;
511}
512
513/**
514 * sti_hqvdp_disable
515 * @hqvdp: hqvdp pointer
516 *
517 * Disables the HQVDP plane
518 */
519static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp)
520{
521 int i;
522
523 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp->plane));
524
525 /* Unregister VTG Vsync callback */
526 if (sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb))
527 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
528
529 /* Set next cmd to NULL */
530 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
531
532 for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
533 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
534 & INFO_XP70_FW_READY)
535 break;
536 msleep(POLL_DELAY_MS);
537 }
538
539 /* VTG can stop now */
540 clk_disable_unprepare(hqvdp->clk_pix_main);
541
542 if (i == POLL_MAX_ATTEMPT)
543 DRM_ERROR("XP70 could not revert to idle\n");
544
545 hqvdp->plane.status = STI_PLANE_DISABLED;
546}
547
548/**
549 * sti_vdp_vtg_cb
550 * @nb: notifier block
551 * @evt: event message
552 * @data: private data
553 *
554 * Handle VTG Vsync event, display pending bottom field
555 *
556 * RETURNS:
557 * 0 on success.
558 */
559int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data)
560{
561 struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb);
562 int btm_cmd_offset, top_cmd_offest;
563 struct sti_hqvdp_cmd *btm_cmd, *top_cmd;
564
565 if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) {
566 DRM_DEBUG_DRIVER("Unknown event\n");
567 return 0;
568 }
569
570 if (hqvdp->plane.status == STI_PLANE_FLUSHING) {
571 /* disable need to be synchronize on vsync event */
572 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
573 sti_plane_to_str(&hqvdp->plane));
574
575 sti_hqvdp_disable(hqvdp);
576 }
577
578 if (hqvdp->btm_field_pending) {
579 /* Create the btm field command from the current one */
580 btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
581 top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp);
582 if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) {
583 DRM_ERROR("Cannot get cmds, skip btm field\n");
584 return -EBUSY;
585 }
586
587 btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset;
588 top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest;
589
590 memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd));
591
592 btm_cmd->top.config = TOP_CONFIG_INTER_BTM;
593 btm_cmd->top.current_luma +=
594 btm_cmd->top.luma_src_pitch / 2;
595 btm_cmd->top.current_chroma +=
596 btm_cmd->top.chroma_src_pitch / 2;
597
598 /* Post the command to mailbox */
599 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset,
600 hqvdp->regs + HQVDP_MBX_NEXT_CMD);
601
602 hqvdp->curr_field_count++;
603 hqvdp->btm_field_pending = false;
604
605 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
606 __func__, hqvdp->hqvdp_cmd_paddr);
607 }
608
609 return 0;
610}
611
612static void sti_hqvdp_init(struct sti_hqvdp *hqvdp)
613{
614 int size;
615
616 hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb;
617
618 /* Allocate memory for the VDP commands */
619 size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd);
620 hqvdp->hqvdp_cmd = dma_alloc_writecombine(hqvdp->dev, size,
621 &hqvdp->hqvdp_cmd_paddr,
622 GFP_KERNEL | GFP_DMA);
623 if (!hqvdp->hqvdp_cmd) {
624 DRM_ERROR("Failed to allocate memory for VDP cmd\n");
625 return;
626 }
627
628 memset(hqvdp->hqvdp_cmd, 0, size);
629}
630
631static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane,
632 struct drm_plane_state *oldstate)
633{
634 struct drm_plane_state *state = drm_plane->state;
635 struct sti_plane *plane = to_sti_plane(drm_plane);
636 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
637 struct drm_crtc *crtc = state->crtc;
638 struct sti_mixer *mixer = to_sti_mixer(crtc);
639 struct drm_framebuffer *fb = state->fb;
640 struct drm_display_mode *mode = &crtc->mode;
641 int dst_x = state->crtc_x;
642 int dst_y = state->crtc_y;
643 int dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
644 int dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
645 /* src_x are in 16.16 format */
646 int src_x = state->src_x >> 16;
647 int src_y = state->src_y >> 16;
648 int src_w = state->src_w >> 16;
649 int src_h = state->src_h >> 16;
650 bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false;
651 struct drm_gem_cma_object *cma_obj;
652 struct sti_hqvdp_cmd *cmd;
653 int scale_h, scale_v;
654 int cmd_offset;
655
656 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
657 crtc->base.id, sti_mixer_to_str(mixer),
658 drm_plane->base.id, sti_plane_to_str(plane));
659 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
660 sti_plane_to_str(plane),
661 dst_w, dst_h, dst_x, dst_y,
662 src_w, src_h, src_x, src_y);
663
664 cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
665 if (cmd_offset == -1) {
666 DRM_ERROR("No available hqvdp_cmd now\n");
667 return;
668 }
669 cmd = hqvdp->hqvdp_cmd + cmd_offset;
670
671 if (!sti_hqvdp_check_hw_scaling(hqvdp, mode,
672 src_w, src_h,
673 dst_w, dst_h)) {
674 DRM_ERROR("Scaling beyond HW capabilities\n");
675 return;
676 }
677
678 /* Static parameters, defaulting to progressive mode */
679 cmd->top.config = TOP_CONFIG_PROGRESSIVE;
680 cmd->top.mem_format = TOP_MEM_FORMAT_DFLT;
681 cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT;
682 cmd->csdi.config = CSDI_CONFIG_PROG;
683
684 /* VC1RE, FMD bypassed : keep everything set to 0
685 * IQI/P2I bypassed */
686 cmd->iqi.config = IQI_CONFIG_DFLT;
687 cmd->iqi.con_bri = IQI_CON_BRI_DFLT;
688 cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT;
689 cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT;
690
691 cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
692 if (!cma_obj) {
693 DRM_ERROR("Can't get CMA GEM object for fb\n");
694 return;
695 }
696
697 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
698 (char *)&fb->pixel_format,
699 (unsigned long)cma_obj->paddr);
700
701 /* Buffer planes address */
702 cmd->top.current_luma = (u32)cma_obj->paddr + fb->offsets[0];
703 cmd->top.current_chroma = (u32)cma_obj->paddr + fb->offsets[1];
704
705 /* Pitches */
706 cmd->top.luma_processed_pitch = fb->pitches[0];
707 cmd->top.luma_src_pitch = fb->pitches[0];
708 cmd->top.chroma_processed_pitch = fb->pitches[1];
709 cmd->top.chroma_src_pitch = fb->pitches[1];
710
711 /* Input / output size
712 * Align to upper even value */
713 dst_w = ALIGN(dst_w, 2);
714 dst_h = ALIGN(dst_h, 2);
715
716 if ((src_w > MAX_WIDTH) || (src_w < MIN_WIDTH) ||
717 (src_h > MAX_HEIGHT) || (src_h < MIN_HEIGHT) ||
718 (dst_w > MAX_WIDTH) || (dst_w < MIN_WIDTH) ||
719 (dst_h > MAX_HEIGHT) || (dst_h < MIN_HEIGHT)) {
720 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n",
721 src_w, src_h,
722 dst_w, dst_h);
723 return;
724 }
725
726 cmd->top.input_viewport_size = src_h << 16 | src_w;
727 cmd->top.input_frame_size = src_h << 16 | src_w;
728 cmd->hvsrc.output_picture_size = dst_h << 16 | dst_w;
729 cmd->top.input_viewport_ori = src_y << 16 | src_x;
730
731 /* Handle interlaced */
732 if (fb->flags & DRM_MODE_FB_INTERLACED) {
733 /* Top field to display */
734 cmd->top.config = TOP_CONFIG_INTER_TOP;
735
736 /* Update pitches and vert size */
737 cmd->top.input_frame_size = (src_h / 2) << 16 | src_w;
738 cmd->top.luma_processed_pitch *= 2;
739 cmd->top.luma_src_pitch *= 2;
740 cmd->top.chroma_processed_pitch *= 2;
741 cmd->top.chroma_src_pitch *= 2;
742
743 /* Enable directional deinterlacing processing */
744 cmd->csdi.config = CSDI_CONFIG_INTER_DIR;
745 cmd->csdi.config2 = CSDI_CONFIG2_DFLT;
746 cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT;
747 }
748
749 /* Update hvsrc lut coef */
750 scale_h = SCALE_FACTOR * dst_w / src_w;
751 sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc);
752
753 scale_v = SCALE_FACTOR * dst_h / src_h;
754 sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc);
755
756 if (first_prepare) {
757 /* Prevent VTG shutdown */
758 if (clk_prepare_enable(hqvdp->clk_pix_main)) {
759 DRM_ERROR("Failed to prepare/enable pix main clk\n");
760 return;
761 }
762
763 /* Register VTG Vsync callback to handle bottom fields */
764 if (sti_vtg_register_client(hqvdp->vtg,
765 &hqvdp->vtg_nb,
766 mixer->id)) {
767 DRM_ERROR("Cannot register VTG notifier\n");
768 return;
769 }
770 }
771
772 writel(hqvdp->hqvdp_cmd_paddr + cmd_offset,
773 hqvdp->regs + HQVDP_MBX_NEXT_CMD);
774
775 hqvdp->curr_field_count++;
776
777 /* Interlaced : get ready to display the bottom field at next Vsync */
778 if (fb->flags & DRM_MODE_FB_INTERLACED)
779 hqvdp->btm_field_pending = true;
780
781 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
782 __func__, hqvdp->hqvdp_cmd_paddr + cmd_offset);
783
784 plane->status = STI_PLANE_UPDATED;
785}
786
787static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane,
788 struct drm_plane_state *oldstate)
789{
790 struct sti_plane *plane = to_sti_plane(drm_plane);
791 struct sti_mixer *mixer = to_sti_mixer(drm_plane->crtc);
792
793 if (!drm_plane->crtc) {
794 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
795 drm_plane->base.id);
796 return;
797 }
798
799 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
800 drm_plane->crtc->base.id, sti_mixer_to_str(mixer),
801 drm_plane->base.id, sti_plane_to_str(plane));
802
803 plane->status = STI_PLANE_DISABLING;
804}
805
806static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs = {
807 .atomic_update = sti_hqvdp_atomic_update,
808 .atomic_disable = sti_hqvdp_atomic_disable,
809};
810
811static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev,
812 struct device *dev, int desc)
813{
814 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
815 int res;
816
817 hqvdp->plane.desc = desc;
818 hqvdp->plane.status = STI_PLANE_DISABLED;
819
820 sti_hqvdp_init(hqvdp);
821
822 res = drm_universal_plane_init(drm_dev, &hqvdp->plane.drm_plane, 1,
823 &sti_plane_helpers_funcs,
824 hqvdp_supported_formats,
825 ARRAY_SIZE(hqvdp_supported_formats),
826 DRM_PLANE_TYPE_OVERLAY);
827 if (res) {
828 DRM_ERROR("Failed to initialize universal plane\n");
829 return NULL;
830 }
831
832 drm_plane_helper_add(&hqvdp->plane.drm_plane, &sti_hqvdp_helpers_funcs);
833
834 sti_plane_init_property(&hqvdp->plane, DRM_PLANE_TYPE_OVERLAY);
835
836 return &hqvdp->plane.drm_plane;
837}
838
839static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp)
840{
841 /* Configure Plugs (same for RD & WR) */
842 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE);
843 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC);
844 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC);
845 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK);
846 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG);
847 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE);
848 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL);
849
850 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE);
851 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC);
852 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC);
853 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK);
854 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG);
855 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE);
856 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL);
857}
858
859/**
860 * sti_hqvdp_start_xp70
861 * @firmware: firmware found
862 * @ctxt: hqvdp structure
863 *
864 * Run the xP70 initialization sequence
865 */
866static void sti_hqvdp_start_xp70(const struct firmware *firmware, void *ctxt)
867{
868 struct sti_hqvdp *hqvdp = ctxt;
869 u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem;
870 u8 *data;
871 int i;
872 struct fw_header {
873 int rd_size;
874 int wr_size;
875 int pmem_size;
876 int dmem_size;
877 } *header;
878
879 DRM_DEBUG_DRIVER("\n");
880
881 if (hqvdp->xp70_initialized) {
882 DRM_INFO("HQVDP XP70 already initialized\n");
883 return;
884 }
885
886 /* Check firmware parts */
887 if (!firmware) {
888 DRM_ERROR("Firmware not available\n");
889 return;
890 }
891
892 header = (struct fw_header *) firmware->data;
893 if (firmware->size < sizeof(*header)) {
894 DRM_ERROR("Invalid firmware size (%d)\n", firmware->size);
895 goto out;
896 }
897 if ((sizeof(*header) + header->rd_size + header->wr_size +
898 header->pmem_size + header->dmem_size) != firmware->size) {
899 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n",
900 sizeof(*header), header->rd_size, header->wr_size,
901 header->pmem_size, header->dmem_size,
902 firmware->size);
903 goto out;
904 }
905
906 data = (u8 *) firmware->data;
907 data += sizeof(*header);
908 fw_rd_plug = (void *) data;
909 data += header->rd_size;
910 fw_wr_plug = (void *) data;
911 data += header->wr_size;
912 fw_pmem = (void *) data;
913 data += header->pmem_size;
914 fw_dmem = (void *) data;
915
916 /* Enable clock */
917 if (clk_prepare_enable(hqvdp->clk))
918 DRM_ERROR("Failed to prepare/enable HQVDP clk\n");
919
920 /* Reset */
921 writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL);
922
923 for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
924 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
925 & STARTUP_CTRL1_RST_DONE)
926 break;
927 msleep(POLL_DELAY_MS);
928 }
929 if (i == POLL_MAX_ATTEMPT) {
930 DRM_ERROR("Could not reset\n");
931 goto out;
932 }
933
934 /* Init Read & Write plugs */
935 for (i = 0; i < header->rd_size / 4; i++)
936 writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4);
937 for (i = 0; i < header->wr_size / 4; i++)
938 writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4);
939
940 sti_hqvdp_init_plugs(hqvdp);
941
942 /* Authorize Idle Mode */
943 writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1);
944
945 /* Prevent VTG interruption during the boot */
946 writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
947 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
948
949 /* Download PMEM & DMEM */
950 for (i = 0; i < header->pmem_size / 4; i++)
951 writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4);
952 for (i = 0; i < header->dmem_size / 4; i++)
953 writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4);
954
955 /* Enable fetch */
956 writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2);
957
958 /* Wait end of boot */
959 for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
960 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
961 & INFO_XP70_FW_READY)
962 break;
963 msleep(POLL_DELAY_MS);
964 }
965 if (i == POLL_MAX_ATTEMPT) {
966 DRM_ERROR("Could not boot\n");
967 goto out;
968 }
969
970 /* Launch Vsync */
971 writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
972
973 DRM_INFO("HQVDP XP70 initialized\n");
974
975 hqvdp->xp70_initialized = true;
976
977out:
978 release_firmware(firmware);
979}
980
981int sti_hqvdp_bind(struct device *dev, struct device *master, void *data)
982{
983 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
984 struct drm_device *drm_dev = data;
985 struct drm_plane *plane;
986 int err;
987
988 DRM_DEBUG_DRIVER("\n");
989
990 hqvdp->drm_dev = drm_dev;
991
992 /* Request for firmware */
993 err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
994 HQVDP_FMW_NAME, hqvdp->dev,
995 GFP_KERNEL, hqvdp, sti_hqvdp_start_xp70);
996 if (err) {
997 DRM_ERROR("Can't get HQVDP firmware\n");
998 return err;
999 }
1000
1001 /* Create HQVDP plane once xp70 is initialized */
1002 plane = sti_hqvdp_create(drm_dev, hqvdp->dev, STI_HQVDP_0);
1003 if (!plane)
1004 DRM_ERROR("Can't create HQVDP plane\n");
1005
1006 return 0;
1007}
1008
1009static void sti_hqvdp_unbind(struct device *dev,
1010 struct device *master, void *data)
1011{
1012 /* do nothing */
1013}
1014
1015static const struct component_ops sti_hqvdp_ops = {
1016 .bind = sti_hqvdp_bind,
1017 .unbind = sti_hqvdp_unbind,
1018};
1019
1020static int sti_hqvdp_probe(struct platform_device *pdev)
1021{
1022 struct device *dev = &pdev->dev;
1023 struct device_node *vtg_np;
1024 struct sti_hqvdp *hqvdp;
1025 struct resource *res;
1026
1027 DRM_DEBUG_DRIVER("\n");
1028
1029 hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL);
1030 if (!hqvdp) {
1031 DRM_ERROR("Failed to allocate HQVDP context\n");
1032 return -ENOMEM;
1033 }
1034
1035 hqvdp->dev = dev;
1036
1037 /* Get Memory resources */
1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1039 if (res == NULL) {
1040 DRM_ERROR("Get memory resource failed\n");
1041 return -ENXIO;
1042 }
1043 hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res));
1044 if (hqvdp->regs == NULL) {
1045 DRM_ERROR("Register mapping failed\n");
1046 return -ENXIO;
1047 }
1048
1049 /* Get clock resources */
1050 hqvdp->clk = devm_clk_get(dev, "hqvdp");
1051 hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main");
1052 if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) {
1053 DRM_ERROR("Cannot get clocks\n");
1054 return -ENXIO;
1055 }
1056
1057 /* Get reset resources */
1058 hqvdp->reset = devm_reset_control_get(dev, "hqvdp");
1059 if (!IS_ERR(hqvdp->reset))
1060 reset_control_deassert(hqvdp->reset);
1061
1062 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0);
1063 if (vtg_np)
1064 hqvdp->vtg = of_vtg_find(vtg_np);
1065
1066 platform_set_drvdata(pdev, hqvdp);
1067
1068 return component_add(&pdev->dev, &sti_hqvdp_ops);
1069}
1070
1071static int sti_hqvdp_remove(struct platform_device *pdev)
1072{
1073 component_del(&pdev->dev, &sti_hqvdp_ops);
1074 return 0;
1075}
1076
1077static struct of_device_id hqvdp_of_match[] = {
1078 { .compatible = "st,stih407-hqvdp", },
1079 { /* end node */ }
1080};
1081MODULE_DEVICE_TABLE(of, hqvdp_of_match);
1082
1083struct platform_driver sti_hqvdp_driver = {
1084 .driver = {
1085 .name = "sti-hqvdp",
1086 .owner = THIS_MODULE,
1087 .of_match_table = hqvdp_of_match,
1088 },
1089 .probe = sti_hqvdp_probe,
1090 .remove = sti_hqvdp_remove,
1091};
1092
1093module_platform_driver(sti_hqvdp_driver);
1094
1095MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1096MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1097MODULE_LICENSE("GPL");