tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for S3C2410 and following SoCs.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/syscore_ops.h>
15
16#include <dt-bindings/clock/s3c2410.h>
17
18#include "clk.h"
19#include "clk-pll.h"
20
21#define LOCKTIME 0x00
22#define MPLLCON 0x04
23#define UPLLCON 0x08
24#define CLKCON 0x0c
25#define CLKSLOW 0x10
26#define CLKDIVN 0x14
27#define CAMDIVN 0x18
28
29/* the soc types */
30enum supported_socs {
31 S3C2410,
32 S3C2440,
33 S3C2442,
34};
35
36/* list of PLLs to be registered */
37enum s3c2410_plls {
38 mpll, upll,
39};
40
41static void __iomem *reg_base;
42
43#ifdef CONFIG_PM_SLEEP
44static struct samsung_clk_reg_dump *s3c2410_save;
45
46/*
47 * list of controller registers to be saved and restored during a
48 * suspend/resume cycle.
49 */
50static unsigned long s3c2410_clk_regs[] __initdata = {
51 LOCKTIME,
52 MPLLCON,
53 UPLLCON,
54 CLKCON,
55 CLKSLOW,
56 CLKDIVN,
57 CAMDIVN,
58};
59
60static int s3c2410_clk_suspend(void)
61{
62 samsung_clk_save(reg_base, s3c2410_save,
63 ARRAY_SIZE(s3c2410_clk_regs));
64
65 return 0;
66}
67
68static void s3c2410_clk_resume(void)
69{
70 samsung_clk_restore(reg_base, s3c2410_save,
71 ARRAY_SIZE(s3c2410_clk_regs));
72}
73
74static struct syscore_ops s3c2410_clk_syscore_ops = {
75 .suspend = s3c2410_clk_suspend,
76 .resume = s3c2410_clk_resume,
77};
78
79static void s3c2410_clk_sleep_init(void)
80{
81 s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
82 ARRAY_SIZE(s3c2410_clk_regs));
83 if (!s3c2410_save) {
84 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
85 __func__);
86 return;
87 }
88
89 register_syscore_ops(&s3c2410_clk_syscore_ops);
90 return;
91}
92#else
93static void s3c2410_clk_sleep_init(void) {}
94#endif
95
96PNAME(fclk_p) = { "mpll", "div_slow" };
97
98struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
99 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
100};
101
102static struct clk_div_table divslow_d[] = {
103 { .val = 0, .div = 1 },
104 { .val = 1, .div = 2 },
105 { .val = 2, .div = 4 },
106 { .val = 3, .div = 6 },
107 { .val = 4, .div = 8 },
108 { .val = 5, .div = 10 },
109 { .val = 6, .div = 12 },
110 { .val = 7, .div = 14 },
111 { /* sentinel */ },
112};
113
114struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
115 DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
116 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
117};
118
119struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
120 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
121 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
122 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
123 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
124 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
125 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
126 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
127 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
128 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
129 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
130 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
131 GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
132 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
133 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
134 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
135};
136
137/* should be added _after_ the soc-specific clocks are created */
138struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
139 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
140 ALIAS(PCLK_ADC, NULL, "adc"),
141 ALIAS(PCLK_RTC, NULL, "rtc"),
142 ALIAS(PCLK_PWM, NULL, "timers"),
143 ALIAS(HCLK_LCD, NULL, "lcd"),
144 ALIAS(HCLK_USBD, NULL, "usb-device"),
145 ALIAS(HCLK_USBH, NULL, "usb-host"),
146 ALIAS(UCLK, NULL, "usb-bus-host"),
147 ALIAS(UCLK, NULL, "usb-bus-gadget"),
148 ALIAS(ARMCLK, NULL, "armclk"),
149 ALIAS(UCLK, NULL, "uclk"),
150 ALIAS(HCLK, NULL, "hclk"),
151 ALIAS(MPLL, NULL, "mpll"),
152 ALIAS(FCLK, NULL, "fclk"),
153 ALIAS(PCLK, NULL, "watchdog"),
154 ALIAS(PCLK_SDI, NULL, "sdi"),
155 ALIAS(HCLK_NAND, NULL, "nand"),
156 ALIAS(PCLK_I2S, NULL, "iis"),
157 ALIAS(PCLK_I2C, NULL, "i2c"),
158};
159
160/* S3C2410 specific clocks */
161
162static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
163 /* sorted in descending order */
164 /* 2410A extras */
165 PLL_35XX_RATE(270000000, 127, 1, 1),
166 PLL_35XX_RATE(268000000, 126, 1, 1),
167 PLL_35XX_RATE(266000000, 125, 1, 1),
168 PLL_35XX_RATE(226000000, 105, 1, 1),
169 PLL_35XX_RATE(210000000, 132, 2, 1),
170 /* 2410 common */
171 PLL_35XX_RATE(203000000, 161, 3, 1),
172 PLL_35XX_RATE(192000000, 88, 1, 1),
173 PLL_35XX_RATE(186000000, 85, 1, 1),
174 PLL_35XX_RATE(180000000, 82, 1, 1),
175 PLL_35XX_RATE(170000000, 77, 1, 1),
176 PLL_35XX_RATE(158000000, 71, 1, 1),
177 PLL_35XX_RATE(152000000, 68, 1, 1),
178 PLL_35XX_RATE(147000000, 90, 2, 1),
179 PLL_35XX_RATE(135000000, 82, 2, 1),
180 PLL_35XX_RATE(124000000, 116, 1, 2),
181 PLL_35XX_RATE(118000000, 150, 2, 2),
182 PLL_35XX_RATE(113000000, 105, 1, 2),
183 PLL_35XX_RATE(101000000, 127, 2, 2),
184 PLL_35XX_RATE(90000000, 112, 2, 2),
185 PLL_35XX_RATE(85000000, 105, 2, 2),
186 PLL_35XX_RATE(79000000, 71, 1, 2),
187 PLL_35XX_RATE(68000000, 82, 2, 2),
188 PLL_35XX_RATE(56000000, 142, 2, 3),
189 PLL_35XX_RATE(48000000, 120, 2, 3),
190 PLL_35XX_RATE(51000000, 161, 3, 3),
191 PLL_35XX_RATE(45000000, 82, 1, 3),
192 PLL_35XX_RATE(34000000, 82, 2, 3),
193 { /* sentinel */ },
194};
195
196static struct samsung_pll_clock s3c2410_plls[] __initdata = {
197 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
198 LOCKTIME, MPLLCON, NULL),
199 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
200 LOCKTIME, UPLLCON, NULL),
201};
202
203struct samsung_div_clock s3c2410_dividers[] __initdata = {
204 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
205};
206
207struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
208 /*
209 * armclk is directly supplied by the fclk, without
210 * switching possibility like on the s3c244x below.
211 */
212 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
213
214 /* uclk is fed from the unmodified upll */
215 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
216};
217
218struct samsung_clock_alias s3c2410_aliases[] __initdata = {
219 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
220 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
221 ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
222 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
223 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
224 ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
225 ALIAS(UCLK, NULL, "clk_uart_baud1"),
226};
227
228/* S3C244x specific clocks */
229
230static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
231 /* sorted in descending order */
232 PLL_35XX_RATE(400000000, 0x5c, 1, 1),
233 PLL_35XX_RATE(390000000, 0x7a, 2, 1),
234 PLL_35XX_RATE(380000000, 0x57, 1, 1),
235 PLL_35XX_RATE(370000000, 0xb1, 4, 1),
236 PLL_35XX_RATE(360000000, 0x70, 2, 1),
237 PLL_35XX_RATE(350000000, 0xa7, 4, 1),
238 PLL_35XX_RATE(340000000, 0x4d, 1, 1),
239 PLL_35XX_RATE(330000000, 0x66, 2, 1),
240 PLL_35XX_RATE(320000000, 0x98, 4, 1),
241 PLL_35XX_RATE(310000000, 0x93, 4, 1),
242 PLL_35XX_RATE(300000000, 0x75, 3, 1),
243 PLL_35XX_RATE(240000000, 0x70, 1, 2),
244 PLL_35XX_RATE(230000000, 0x6b, 1, 2),
245 PLL_35XX_RATE(220000000, 0x66, 1, 2),
246 PLL_35XX_RATE(210000000, 0x84, 2, 2),
247 PLL_35XX_RATE(200000000, 0x5c, 1, 2),
248 PLL_35XX_RATE(190000000, 0x57, 1, 2),
249 PLL_35XX_RATE(180000000, 0x70, 2, 2),
250 PLL_35XX_RATE(170000000, 0x4d, 1, 2),
251 PLL_35XX_RATE(160000000, 0x98, 4, 2),
252 PLL_35XX_RATE(150000000, 0x75, 3, 2),
253 PLL_35XX_RATE(120000000, 0x70, 1, 3),
254 PLL_35XX_RATE(110000000, 0x66, 1, 3),
255 PLL_35XX_RATE(100000000, 0x5c, 1, 3),
256 PLL_35XX_RATE(90000000, 0x70, 2, 3),
257 PLL_35XX_RATE(80000000, 0x98, 4, 3),
258 PLL_35XX_RATE(75000000, 0x75, 3, 3),
259 { /* sentinel */ },
260};
261
262static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
263 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
264 LOCKTIME, MPLLCON, NULL),
265 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
266 LOCKTIME, UPLLCON, NULL),
267};
268
269PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
270PNAME(armclk_p) = { "fclk", "hclk" };
271
272struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
273 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
274 MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
275};
276
277struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
278 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
279 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
280};
281
282static struct clk_div_table div_hclk_4_d[] = {
283 { .val = 0, .div = 4 },
284 { .val = 1, .div = 8 },
285 { /* sentinel */ },
286};
287
288static struct clk_div_table div_hclk_3_d[] = {
289 { .val = 0, .div = 3 },
290 { .val = 1, .div = 6 },
291 { /* sentinel */ },
292};
293
294struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
295 DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
296 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
297 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
298 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
299 DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
300};
301
302struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
303 GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
304};
305
306struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
307 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
308 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
309 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
310 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
311 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
312 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
313 ALIAS(HCLK_CAM, NULL, "camif"),
314 ALIAS(CAMIF, NULL, "camif-upll"),
315};
316
317/* S3C2440 specific clocks */
318
319PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
320
321struct samsung_mux_clock s3c2440_muxes[] __initdata = {
322 MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
323};
324
325struct samsung_gate_clock s3c2440_gates[] __initdata = {
326 GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
327};
328
329/* S3C2442 specific clocks */
330
331struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
332 FFACTOR(0, "upll_3", "upll", 1, 3, 0),
333};
334
335PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
336
337struct samsung_mux_clock s3c2442_muxes[] __initdata = {
338 MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
339};
340
341/*
342 * fixed rate clocks generated outside the soc
343 * Only necessary until the devicetree-move is complete
344 */
345#define XTI 1
346struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
347 FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0),
348};
349
350static void __init s3c2410_common_clk_register_fixed_ext(
351 struct samsung_clk_provider *ctx,
352 unsigned long xti_f)
353{
354 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
355
356 s3c2410_common_frate_clks[0].fixed_rate = xti_f;
357 samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
358 ARRAY_SIZE(s3c2410_common_frate_clks));
359
360 samsung_clk_register_alias(ctx, &xti_alias, 1);
361}
362
363void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
364 int current_soc,
365 void __iomem *base)
366{
367 struct samsung_clk_provider *ctx;
368 reg_base = base;
369
370 if (np) {
371 reg_base = of_iomap(np, 0);
372 if (!reg_base)
373 panic("%s: failed to map registers\n", __func__);
374 }
375
376 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
377 if (!ctx)
378 panic("%s: unable to allocate context.\n", __func__);
379
380 /* Register external clocks only in non-dt cases */
381 if (!np)
382 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
383
384 if (current_soc == S3C2410) {
385 if (_get_rate("xti") == 12 * MHZ) {
386 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
387 s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
388 }
389
390 /* Register PLLs. */
391 samsung_clk_register_pll(ctx, s3c2410_plls,
392 ARRAY_SIZE(s3c2410_plls), reg_base);
393
394 } else { /* S3C2440, S3C2442 */
395 if (_get_rate("xti") == 12 * MHZ) {
396 /*
397 * plls follow different calculation schemes, with the
398 * upll following the same scheme as the s3c2410 plls
399 */
400 s3c244x_common_plls[mpll].rate_table =
401 pll_s3c244x_12mhz_tbl;
402 s3c244x_common_plls[upll].rate_table =
403 pll_s3c2410_12mhz_tbl;
404 }
405
406 /* Register PLLs. */
407 samsung_clk_register_pll(ctx, s3c244x_common_plls,
408 ARRAY_SIZE(s3c244x_common_plls), reg_base);
409 }
410
411 /* Register common internal clocks. */
412 samsung_clk_register_mux(ctx, s3c2410_common_muxes,
413 ARRAY_SIZE(s3c2410_common_muxes));
414 samsung_clk_register_div(ctx, s3c2410_common_dividers,
415 ARRAY_SIZE(s3c2410_common_dividers));
416 samsung_clk_register_gate(ctx, s3c2410_common_gates,
417 ARRAY_SIZE(s3c2410_common_gates));
418
419 if (current_soc == S3C2440 || current_soc == S3C2442) {
420 samsung_clk_register_div(ctx, s3c244x_common_dividers,
421 ARRAY_SIZE(s3c244x_common_dividers));
422 samsung_clk_register_gate(ctx, s3c244x_common_gates,
423 ARRAY_SIZE(s3c244x_common_gates));
424 samsung_clk_register_mux(ctx, s3c244x_common_muxes,
425 ARRAY_SIZE(s3c244x_common_muxes));
426 samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
427 ARRAY_SIZE(s3c244x_common_ffactor));
428 }
429
430 /* Register SoC-specific clocks. */
431 switch (current_soc) {
432 case S3C2410:
433 samsung_clk_register_div(ctx, s3c2410_dividers,
434 ARRAY_SIZE(s3c2410_dividers));
435 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
436 ARRAY_SIZE(s3c2410_ffactor));
437 samsung_clk_register_alias(ctx, s3c2410_aliases,
438 ARRAY_SIZE(s3c2410_aliases));
439 break;
440 case S3C2440:
441 samsung_clk_register_mux(ctx, s3c2440_muxes,
442 ARRAY_SIZE(s3c2440_muxes));
443 samsung_clk_register_gate(ctx, s3c2440_gates,
444 ARRAY_SIZE(s3c2440_gates));
445 break;
446 case S3C2442:
447 samsung_clk_register_mux(ctx, s3c2442_muxes,
448 ARRAY_SIZE(s3c2442_muxes));
449 samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
450 ARRAY_SIZE(s3c2442_ffactor));
451 break;
452 }
453
454 /*
455 * Register common aliases at the end, as some of the aliased clocks
456 * are SoC specific.
457 */
458 samsung_clk_register_alias(ctx, s3c2410_common_aliases,
459 ARRAY_SIZE(s3c2410_common_aliases));
460
461 if (current_soc == S3C2440 || current_soc == S3C2442) {
462 samsung_clk_register_alias(ctx, s3c244x_common_aliases,
463 ARRAY_SIZE(s3c244x_common_aliases));
464 }
465
466 s3c2410_clk_sleep_init();
467
468 samsung_clk_of_add_provider(np, ctx);
469}
470
471static void __init s3c2410_clk_init(struct device_node *np)
472{
473 s3c2410_common_clk_init(np, 0, S3C2410, 0);
474}
475CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
476
477static void __init s3c2440_clk_init(struct device_node *np)
478{
479 s3c2410_common_clk_init(np, 0, S3C2440, 0);
480}
481CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
482
483static void __init s3c2442_clk_init(struct device_node *np)
484{
485 s3c2410_common_clk_init(np, 0, S3C2442, 0);
486}
487CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);