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1#ifndef _ASM_X86_MWAIT_H
2#define _ASM_X86_MWAIT_H
3
4#include <linux/sched.h>
5
6#define MWAIT_SUBSTATE_MASK 0xf
7#define MWAIT_CSTATE_MASK 0xf
8#define MWAIT_SUBSTATE_SIZE 4
9#define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
10#define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
11
12#define CPUID_MWAIT_LEAF 5
13#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
14#define CPUID5_ECX_INTERRUPT_BREAK 0x2
15
16#define MWAIT_ECX_INTERRUPT_BREAK 0x1
17#define MWAITX_ECX_TIMER_ENABLE BIT(1)
18#define MWAITX_MAX_LOOPS ((u32)-1)
19#define MWAITX_DISABLE_CSTATES 0xf
20
21static inline void __monitor(const void *eax, unsigned long ecx,
22 unsigned long edx)
23{
24 /* "monitor %eax, %ecx, %edx;" */
25 asm volatile(".byte 0x0f, 0x01, 0xc8;"
26 :: "a" (eax), "c" (ecx), "d"(edx));
27}
28
29static inline void __monitorx(const void *eax, unsigned long ecx,
30 unsigned long edx)
31{
32 /* "monitorx %eax, %ecx, %edx;" */
33 asm volatile(".byte 0x0f, 0x01, 0xfa;"
34 :: "a" (eax), "c" (ecx), "d"(edx));
35}
36
37static inline void __mwait(unsigned long eax, unsigned long ecx)
38{
39 /* "mwait %eax, %ecx;" */
40 asm volatile(".byte 0x0f, 0x01, 0xc9;"
41 :: "a" (eax), "c" (ecx));
42}
43
44/*
45 * MWAITX allows for a timer expiration to get the core out a wait state in
46 * addition to the default MWAIT exit condition of a store appearing at a
47 * monitored virtual address.
48 *
49 * Registers:
50 *
51 * MWAITX ECX[1]: enable timer if set
52 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
53 * frequency is the same as the TSC frequency.
54 *
55 * Below is a comparison between MWAIT and MWAITX on AMD processors:
56 *
57 * MWAIT MWAITX
58 * opcode 0f 01 c9 | 0f 01 fb
59 * ECX[0] value of RFLAGS.IF seen by instruction
60 * ECX[1] unused/#GP if set | enable timer if set
61 * ECX[31:2] unused/#GP if set
62 * EAX unused (reserve for hint)
63 * EBX[31:0] unused | max wait time (P0 clocks)
64 *
65 * MONITOR MONITORX
66 * opcode 0f 01 c8 | 0f 01 fa
67 * EAX (logical) address to monitor
68 * ECX #GP if not zero
69 */
70static inline void __mwaitx(unsigned long eax, unsigned long ebx,
71 unsigned long ecx)
72{
73 /* "mwaitx %eax, %ebx, %ecx;" */
74 asm volatile(".byte 0x0f, 0x01, 0xfb;"
75 :: "a" (eax), "b" (ebx), "c" (ecx));
76}
77
78static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
79{
80 trace_hardirqs_on();
81 /* "mwait %eax, %ecx;" */
82 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
83 :: "a" (eax), "c" (ecx));
84}
85
86/*
87 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
88 * which can obviate IPI to trigger checking of need_resched.
89 * We execute MONITOR against need_resched and enter optimized wait state
90 * through MWAIT. Whenever someone changes need_resched, we would be woken
91 * up from MWAIT (without an IPI).
92 *
93 * New with Core Duo processors, MWAIT can take some hints based on CPU
94 * capability.
95 */
96static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
97{
98 if (!current_set_polling_and_test()) {
99 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
100 mb();
101 clflush((void *)¤t_thread_info()->flags);
102 mb();
103 }
104
105 __monitor((void *)¤t_thread_info()->flags, 0, 0);
106 if (!need_resched())
107 __mwait(eax, ecx);
108 }
109 current_clr_polling();
110}
111
112#endif /* _ASM_X86_MWAIT_H */