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1#ifndef _ASM_X86_MCE_H
2#define _ASM_X86_MCE_H
3
4#include <uapi/asm/mce.h>
5
6/*
7 * Machine Check support for x86
8 */
9
10/* MCG_CAP register defines */
11#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
13#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
14#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
15#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16#define MCG_EXT_CNT_SHIFT 16
17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
19#define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */
20#define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */
21
22/* MCG_STATUS register defines */
23#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
24#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
25#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
26#define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */
27
28/* MCG_EXT_CTL register defines */
29#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
30
31/* MCi_STATUS register defines */
32#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
33#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
34#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
35#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
36#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
37#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
38#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
39#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
40#define MCI_STATUS_AR (1ULL<<55) /* Action required */
41
42/* AMD-specific bits */
43#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
44#define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */
45
46/*
47 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
48 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
49 * errors to indicate that errors are being filtered by hardware.
50 * We should mask out bit 12 when looking for specific signatures
51 * of uncorrected errors - so the F bit is deliberately skipped
52 * in this #define.
53 */
54#define MCACOD 0xefff /* MCA Error Code */
55
56/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
57#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
58#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
59#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
60#define MCACOD_DATA 0x0134 /* Data Load */
61#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
62
63/* MCi_MISC register defines */
64#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
65#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
66#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
67#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
68#define MCI_MISC_ADDR_PHYS 2 /* physical address */
69#define MCI_MISC_ADDR_MEM 3 /* memory address */
70#define MCI_MISC_ADDR_GENERIC 7 /* generic */
71
72/* CTL2 register defines */
73#define MCI_CTL2_CMCI_EN (1ULL << 30)
74#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
75
76#define MCJ_CTX_MASK 3
77#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
78#define MCJ_CTX_RANDOM 0 /* inject context: random */
79#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
80#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
81#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
82#define MCJ_EXCEPTION 0x8 /* raise as exception */
83#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
84
85#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
86
87/* Software defined banks */
88#define MCE_EXTENDED_BANK 128
89#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
90
91#define MCE_LOG_LEN 32
92#define MCE_LOG_SIGNATURE "MACHINECHECK"
93
94/*
95 * This structure contains all data related to the MCE log. Also
96 * carries a signature to make it easier to find from external
97 * debugging tools. Each entry is only valid when its finished flag
98 * is set.
99 */
100struct mce_log {
101 char signature[12]; /* "MACHINECHECK" */
102 unsigned len; /* = MCE_LOG_LEN */
103 unsigned next;
104 unsigned flags;
105 unsigned recordlen; /* length of struct mce */
106 struct mce entry[MCE_LOG_LEN];
107};
108
109struct mca_config {
110 bool dont_log_ce;
111 bool cmci_disabled;
112 bool lmce_disabled;
113 bool ignore_ce;
114 bool disabled;
115 bool ser;
116 bool bios_cmci_threshold;
117 u8 banks;
118 s8 bootlog;
119 int tolerant;
120 int monarch_timeout;
121 int panic_timeout;
122 u32 rip_msr;
123};
124
125struct mce_vendor_flags {
126 /*
127 * overflow recovery cpuid bit indicates that overflow
128 * conditions are not fatal
129 */
130 __u64 overflow_recov : 1,
131
132 /*
133 * SUCCOR stands for S/W UnCorrectable error COntainment
134 * and Recovery. It indicates support for data poisoning
135 * in HW and deferred error interrupts.
136 */
137 succor : 1,
138 __reserved_0 : 62;
139};
140extern struct mce_vendor_flags mce_flags;
141
142extern struct mca_config mca_cfg;
143extern void mce_register_decode_chain(struct notifier_block *nb);
144extern void mce_unregister_decode_chain(struct notifier_block *nb);
145
146#include <linux/percpu.h>
147#include <linux/atomic.h>
148
149extern int mce_p5_enabled;
150
151#ifdef CONFIG_X86_MCE
152int mcheck_init(void);
153void mcheck_cpu_init(struct cpuinfo_x86 *c);
154void mcheck_cpu_clear(struct cpuinfo_x86 *c);
155void mcheck_vendor_init_severity(void);
156#else
157static inline int mcheck_init(void) { return 0; }
158static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
159static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
160static inline void mcheck_vendor_init_severity(void) {}
161#endif
162
163#ifdef CONFIG_X86_ANCIENT_MCE
164void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
165void winchip_mcheck_init(struct cpuinfo_x86 *c);
166static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
167#else
168static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
169static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
170static inline void enable_p5_mce(void) {}
171#endif
172
173void mce_setup(struct mce *m);
174void mce_log(struct mce *m);
175DECLARE_PER_CPU(struct device *, mce_device);
176
177/*
178 * Maximum banks number.
179 * This is the limit of the current register layout on
180 * Intel CPUs.
181 */
182#define MAX_NR_BANKS 32
183
184#ifdef CONFIG_X86_MCE_INTEL
185void mce_intel_feature_init(struct cpuinfo_x86 *c);
186void mce_intel_feature_clear(struct cpuinfo_x86 *c);
187void cmci_clear(void);
188void cmci_reenable(void);
189void cmci_rediscover(void);
190void cmci_recheck(void);
191#else
192static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
193static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
194static inline void cmci_clear(void) {}
195static inline void cmci_reenable(void) {}
196static inline void cmci_rediscover(void) {}
197static inline void cmci_recheck(void) {}
198#endif
199
200#ifdef CONFIG_X86_MCE_AMD
201void mce_amd_feature_init(struct cpuinfo_x86 *c);
202#else
203static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
204#endif
205
206int mce_available(struct cpuinfo_x86 *c);
207
208DECLARE_PER_CPU(unsigned, mce_exception_count);
209DECLARE_PER_CPU(unsigned, mce_poll_count);
210
211typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
212DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
213
214enum mcp_flags {
215 MCP_TIMESTAMP = BIT(0), /* log time stamp */
216 MCP_UC = BIT(1), /* log uncorrected errors */
217 MCP_DONTLOG = BIT(2), /* only clear, don't log */
218};
219bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
220
221int mce_notify_irq(void);
222
223DECLARE_PER_CPU(struct mce, injectm);
224
225extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
226 const char __user *ubuf,
227 size_t usize, loff_t *off));
228
229/* Disable CMCI/polling for MCA bank claimed by firmware */
230extern void mce_disable_bank(int bank);
231
232/*
233 * Exception handler
234 */
235
236/* Call the installed machine check handler for this CPU setup. */
237extern void (*machine_check_vector)(struct pt_regs *, long error_code);
238void do_machine_check(struct pt_regs *, long);
239
240/*
241 * Threshold handler
242 */
243
244extern void (*mce_threshold_vector)(void);
245extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
246
247/* Deferred error interrupt handler */
248extern void (*deferred_error_int_vector)(void);
249
250/*
251 * Thermal handler
252 */
253
254void intel_init_thermal(struct cpuinfo_x86 *c);
255
256void mce_log_therm_throt_event(__u64 status);
257
258/* Interrupt Handler for core thermal thresholds */
259extern int (*platform_thermal_notify)(__u64 msr_val);
260
261/* Interrupt Handler for package thermal thresholds */
262extern int (*platform_thermal_package_notify)(__u64 msr_val);
263
264/* Callback support of rate control, return true, if
265 * callback has rate control */
266extern bool (*platform_thermal_package_rate_control)(void);
267
268#ifdef CONFIG_X86_THERMAL_VECTOR
269extern void mcheck_intel_therm_init(void);
270#else
271static inline void mcheck_intel_therm_init(void) { }
272#endif
273
274/*
275 * Used by APEI to report memory error via /dev/mcelog
276 */
277
278struct cper_sec_mem_err;
279extern void apei_mce_report_mem_error(int corrected,
280 struct cper_sec_mem_err *mem_err);
281
282#endif /* _ASM_X86_MCE_H */