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1#ifndef _ASM_POWERPC_PROCESSOR_H
2#define _ASM_POWERPC_PROCESSOR_H
3
4/*
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/reg.h>
14
15#ifdef CONFIG_VSX
16#define TS_FPRWIDTH 2
17
18#ifdef __BIG_ENDIAN__
19#define TS_FPROFFSET 0
20#define TS_VSRLOWOFFSET 1
21#else
22#define TS_FPROFFSET 1
23#define TS_VSRLOWOFFSET 0
24#endif
25
26#else
27#define TS_FPRWIDTH 1
28#define TS_FPROFFSET 0
29#endif
30
31#ifdef CONFIG_PPC64
32/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
33#define PPR_PRIORITY 3
34#ifdef __ASSEMBLY__
35#define INIT_PPR (PPR_PRIORITY << 50)
36#else
37#define INIT_PPR ((u64)PPR_PRIORITY << 50)
38#endif /* __ASSEMBLY__ */
39#endif /* CONFIG_PPC64 */
40
41#ifndef __ASSEMBLY__
42#include <linux/compiler.h>
43#include <linux/cache.h>
44#include <asm/ptrace.h>
45#include <asm/types.h>
46#include <asm/hw_breakpoint.h>
47
48/* We do _not_ want to define new machine types at all, those must die
49 * in favor of using the device-tree
50 * -- BenH.
51 */
52
53/* PREP sub-platform types. Unused */
54#define _PREP_Motorola 0x01 /* motorola prep */
55#define _PREP_Firm 0x02 /* firmworks prep */
56#define _PREP_IBM 0x00 /* ibm prep */
57#define _PREP_Bull 0x03 /* bull prep */
58
59/* CHRP sub-platform types. These are arbitrary */
60#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
61#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
62#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
63#define _CHRP_briq 0x07 /* TotalImpact's briQ */
64
65#if defined(__KERNEL__) && defined(CONFIG_PPC32)
66
67extern int _chrp_type;
68
69#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
70
71/*
72 * Default implementation of macro that returns current
73 * instruction pointer ("program counter").
74 */
75#define current_text_addr() ({ __label__ _l; _l: &&_l;})
76
77/* Macros for adjusting thread priority (hardware multi-threading) */
78#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
79#define HMT_low() asm volatile("or 1,1,1 # low priority")
80#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
81#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
82#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
83#define HMT_high() asm volatile("or 3,3,3 # high priority")
84
85#ifdef __KERNEL__
86
87struct task_struct;
88void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
89void release_thread(struct task_struct *);
90
91/* Lazy FPU handling on uni-processor */
92extern struct task_struct *last_task_used_math;
93extern struct task_struct *last_task_used_altivec;
94extern struct task_struct *last_task_used_vsx;
95extern struct task_struct *last_task_used_spe;
96
97#ifdef CONFIG_PPC32
98
99#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
100#error User TASK_SIZE overlaps with KERNEL_START address
101#endif
102#define TASK_SIZE (CONFIG_TASK_SIZE)
103
104/* This decides where the kernel will search for a free chunk of vm
105 * space during mmap's.
106 */
107#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
108#endif
109
110#ifdef CONFIG_PPC64
111/* 64-bit user address space is 46-bits (64TB user VM) */
112#define TASK_SIZE_USER64 (0x0000400000000000UL)
113
114/*
115 * 32-bit user address space is 4GB - 1 page
116 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
117 */
118#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
119
120#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
121 TASK_SIZE_USER32 : TASK_SIZE_USER64)
122#define TASK_SIZE TASK_SIZE_OF(current)
123
124/* This decides where the kernel will search for a free chunk of vm
125 * space during mmap's.
126 */
127#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
128#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
129
130#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
131 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
132#endif
133
134#ifdef __powerpc64__
135
136#define STACK_TOP_USER64 TASK_SIZE_USER64
137#define STACK_TOP_USER32 TASK_SIZE_USER32
138
139#define STACK_TOP (is_32bit_task() ? \
140 STACK_TOP_USER32 : STACK_TOP_USER64)
141
142#define STACK_TOP_MAX STACK_TOP_USER64
143
144#else /* __powerpc64__ */
145
146#define STACK_TOP TASK_SIZE
147#define STACK_TOP_MAX STACK_TOP
148
149#endif /* __powerpc64__ */
150
151typedef struct {
152 unsigned long seg;
153} mm_segment_t;
154
155#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
156#define TS_TRANS_FPR(i) transact_fp.fpr[i][TS_FPROFFSET]
157
158/* FP and VSX 0-31 register set */
159struct thread_fp_state {
160 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
161 u64 fpscr; /* Floating point status */
162};
163
164/* Complete AltiVec register set including VSCR */
165struct thread_vr_state {
166 vector128 vr[32] __attribute__((aligned(16)));
167 vector128 vscr __attribute__((aligned(16)));
168};
169
170struct debug_reg {
171#ifdef CONFIG_PPC_ADV_DEBUG_REGS
172 /*
173 * The following help to manage the use of Debug Control Registers
174 * om the BookE platforms.
175 */
176 uint32_t dbcr0;
177 uint32_t dbcr1;
178#ifdef CONFIG_BOOKE
179 uint32_t dbcr2;
180#endif
181 /*
182 * The stored value of the DBSR register will be the value at the
183 * last debug interrupt. This register can only be read from the
184 * user (will never be written to) and has value while helping to
185 * describe the reason for the last debug trap. Torez
186 */
187 uint32_t dbsr;
188 /*
189 * The following will contain addresses used by debug applications
190 * to help trace and trap on particular address locations.
191 * The bits in the Debug Control Registers above help define which
192 * of the following registers will contain valid data and/or addresses.
193 */
194 unsigned long iac1;
195 unsigned long iac2;
196#if CONFIG_PPC_ADV_DEBUG_IACS > 2
197 unsigned long iac3;
198 unsigned long iac4;
199#endif
200 unsigned long dac1;
201 unsigned long dac2;
202#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
203 unsigned long dvc1;
204 unsigned long dvc2;
205#endif
206#endif
207};
208
209struct thread_struct {
210 unsigned long ksp; /* Kernel stack pointer */
211
212#ifdef CONFIG_PPC64
213 unsigned long ksp_vsid;
214#endif
215 struct pt_regs *regs; /* Pointer to saved register state */
216 mm_segment_t fs; /* for get_fs() validation */
217#ifdef CONFIG_BOOKE
218 /* BookE base exception scratch space; align on cacheline */
219 unsigned long normsave[8] ____cacheline_aligned;
220#endif
221#ifdef CONFIG_PPC32
222 void *pgdir; /* root of page-table tree */
223 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
224#endif
225 /* Debug Registers */
226 struct debug_reg debug;
227 struct thread_fp_state fp_state;
228 struct thread_fp_state *fp_save_area;
229 int fpexc_mode; /* floating-point exception mode */
230 unsigned int align_ctl; /* alignment handling control */
231#ifdef CONFIG_PPC64
232 unsigned long start_tb; /* Start purr when proc switched in */
233 unsigned long accum_tb; /* Total accumilated purr for process */
234#ifdef CONFIG_HAVE_HW_BREAKPOINT
235 struct perf_event *ptrace_bps[HBP_NUM];
236 /*
237 * Helps identify source of single-step exception and subsequent
238 * hw-breakpoint enablement
239 */
240 struct perf_event *last_hit_ubp;
241#endif /* CONFIG_HAVE_HW_BREAKPOINT */
242#endif
243 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
244 unsigned long trap_nr; /* last trap # on this thread */
245#ifdef CONFIG_ALTIVEC
246 struct thread_vr_state vr_state;
247 struct thread_vr_state *vr_save_area;
248 unsigned long vrsave;
249 int used_vr; /* set if process has used altivec */
250#endif /* CONFIG_ALTIVEC */
251#ifdef CONFIG_VSX
252 /* VSR status */
253 int used_vsr; /* set if process has used altivec */
254#endif /* CONFIG_VSX */
255#ifdef CONFIG_SPE
256 unsigned long evr[32]; /* upper 32-bits of SPE regs */
257 u64 acc; /* Accumulator */
258 unsigned long spefscr; /* SPE & eFP status */
259 unsigned long spefscr_last; /* SPEFSCR value on last prctl
260 call or trap return */
261 int used_spe; /* set if process has used spe */
262#endif /* CONFIG_SPE */
263#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
264 u64 tm_tfhar; /* Transaction fail handler addr */
265 u64 tm_texasr; /* Transaction exception & summary */
266 u64 tm_tfiar; /* Transaction fail instr address reg */
267 struct pt_regs ckpt_regs; /* Checkpointed registers */
268
269 unsigned long tm_tar;
270 unsigned long tm_ppr;
271 unsigned long tm_dscr;
272
273 /*
274 * Transactional FP and VSX 0-31 register set.
275 * NOTE: the sense of these is the opposite of the integer ckpt_regs!
276 *
277 * When a transaction is active/signalled/scheduled etc., *regs is the
278 * most recent set of/speculated GPRs with ckpt_regs being the older
279 * checkpointed regs to which we roll back if transaction aborts.
280 *
281 * However, fpr[] is the checkpointed 'base state' of FP regs, and
282 * transact_fpr[] is the new set of transactional values.
283 * VRs work the same way.
284 */
285 struct thread_fp_state transact_fp;
286 struct thread_vr_state transact_vr;
287 unsigned long transact_vrsave;
288#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
289#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
290 void* kvm_shadow_vcpu; /* KVM internal data */
291#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
292#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
293 struct kvm_vcpu *kvm_vcpu;
294#endif
295#ifdef CONFIG_PPC64
296 unsigned long dscr;
297 /*
298 * This member element dscr_inherit indicates that the process
299 * has explicitly attempted and changed the DSCR register value
300 * for itself. Hence kernel wont use the default CPU DSCR value
301 * contained in the PACA structure anymore during process context
302 * switch. Once this variable is set, this behaviour will also be
303 * inherited to all the children of this process from that point
304 * onwards.
305 */
306 int dscr_inherit;
307 unsigned long ppr; /* used to save/restore SMT priority */
308#endif
309#ifdef CONFIG_PPC_BOOK3S_64
310 unsigned long tar;
311 unsigned long ebbrr;
312 unsigned long ebbhr;
313 unsigned long bescr;
314 unsigned long siar;
315 unsigned long sdar;
316 unsigned long sier;
317 unsigned long mmcr2;
318 unsigned mmcr0;
319 unsigned used_ebb;
320#endif
321};
322
323#define ARCH_MIN_TASKALIGN 16
324
325#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
326#define INIT_SP_LIMIT \
327 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
328
329#ifdef CONFIG_SPE
330#define SPEFSCR_INIT \
331 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
332 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
333#else
334#define SPEFSCR_INIT
335#endif
336
337#ifdef CONFIG_PPC32
338#define INIT_THREAD { \
339 .ksp = INIT_SP, \
340 .ksp_limit = INIT_SP_LIMIT, \
341 .fs = KERNEL_DS, \
342 .pgdir = swapper_pg_dir, \
343 .fpexc_mode = MSR_FE0 | MSR_FE1, \
344 SPEFSCR_INIT \
345}
346#else
347#define INIT_THREAD { \
348 .ksp = INIT_SP, \
349 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
350 .fs = KERNEL_DS, \
351 .fpexc_mode = 0, \
352 .ppr = INIT_PPR, \
353}
354#endif
355
356/*
357 * Return saved PC of a blocked thread. For now, this is the "user" PC
358 */
359#define thread_saved_pc(tsk) \
360 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
361
362#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
363
364unsigned long get_wchan(struct task_struct *p);
365
366#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
367#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
368
369/* Get/set floating-point exception mode */
370#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
371#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
372
373extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
374extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
375
376#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
377#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
378
379extern int get_endian(struct task_struct *tsk, unsigned long adr);
380extern int set_endian(struct task_struct *tsk, unsigned int val);
381
382#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
383#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
384
385extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
386extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
387
388extern void fp_enable(void);
389extern void vec_enable(void);
390extern void load_fp_state(struct thread_fp_state *fp);
391extern void store_fp_state(struct thread_fp_state *fp);
392extern void load_vr_state(struct thread_vr_state *vr);
393extern void store_vr_state(struct thread_vr_state *vr);
394
395static inline unsigned int __unpack_fe01(unsigned long msr_bits)
396{
397 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
398}
399
400static inline unsigned long __pack_fe01(unsigned int fpmode)
401{
402 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
403}
404
405#ifdef CONFIG_PPC64
406#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
407#else
408#define cpu_relax() barrier()
409#endif
410
411#define cpu_relax_lowlatency() cpu_relax()
412
413/* Check that a certain kernel stack pointer is valid in task_struct p */
414int validate_sp(unsigned long sp, struct task_struct *p,
415 unsigned long nbytes);
416
417/*
418 * Prefetch macros.
419 */
420#define ARCH_HAS_PREFETCH
421#define ARCH_HAS_PREFETCHW
422#define ARCH_HAS_SPINLOCK_PREFETCH
423
424static inline void prefetch(const void *x)
425{
426 if (unlikely(!x))
427 return;
428
429 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
430}
431
432static inline void prefetchw(const void *x)
433{
434 if (unlikely(!x))
435 return;
436
437 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
438}
439
440#define spin_lock_prefetch(x) prefetchw(x)
441
442#define HAVE_ARCH_PICK_MMAP_LAYOUT
443
444#ifdef CONFIG_PPC64
445static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
446{
447 if (is_32)
448 return sp & 0x0ffffffffUL;
449 return sp;
450}
451#else
452static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
453{
454 return sp;
455}
456#endif
457
458extern unsigned long cpuidle_disable;
459enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
460
461extern int powersave_nap; /* set if nap mode can be used in idle loop */
462extern unsigned long power7_nap(int check_irq);
463extern unsigned long power7_sleep(void);
464extern unsigned long power7_winkle(void);
465extern void flush_instruction_cache(void);
466extern void hard_reset_now(void);
467extern void poweroff_now(void);
468extern int fix_alignment(struct pt_regs *);
469extern void cvt_fd(float *from, double *to);
470extern void cvt_df(double *from, float *to);
471extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
472
473#ifdef CONFIG_PPC64
474/*
475 * We handle most unaligned accesses in hardware. On the other hand
476 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
477 * powers of 2 writes until it reaches sufficient alignment).
478 *
479 * Based on this we disable the IP header alignment in network drivers.
480 */
481#define NET_IP_ALIGN 0
482#endif
483
484#endif /* __KERNEL__ */
485#endif /* __ASSEMBLY__ */
486#endif /* _ASM_POWERPC_PROCESSOR_H */