tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * TLB Exception Handling for ARC
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Vineetg: April 2011 :
11 * -MMU v1: moved out legacy code into a seperate file
12 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * helps avoid a shift when preparing PD0 from PTE
14 *
15 * Vineetg: July 2009
16 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
17 * entry, so that it doesn't knock out it's I-TLB entry
18 * -Some more fine tuning:
19 * bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
20 *
21 * Vineetg: July 2009
22 * -Practically rewrote the I/D TLB Miss handlers
23 * Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
24 * Hence Leaner by 1.5 K
25 * Used Conditional arithmetic to replace excessive branching
26 * Also used short instructions wherever possible
27 *
28 * Vineetg: Aug 13th 2008
29 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
30 * more information in case of a Fatality
31 *
32 * Vineetg: March 25th Bug #92690
33 * -Added Debug Code to check if sw-ASID == hw-ASID
34
35 * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
36 */
37
38#include <linux/linkage.h>
39#include <asm/entry.h>
40#include <asm/mmu.h>
41#include <asm/pgtable.h>
42#include <asm/arcregs.h>
43#include <asm/cache.h>
44#include <asm/processor.h>
45#include <asm/tlb-mmu1.h>
46
47#ifdef CONFIG_ISA_ARCOMPACT
48;-----------------------------------------------------------------
49; ARC700 Exception Handling doesn't auto-switch stack and it only provides
50; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
51;
52; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
53; "global" is used to free-up FIRST core reg to be able to code the rest of
54; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
55; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
56; need to be saved as well by extending the "global" to be 4 words. Hence
57; ".size ex_saved_reg1, 16"
58; [All of this dance is to avoid stack switching for each TLB Miss, since we
59; only need to save only a handful of regs, as opposed to complete reg file]
60;
61; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
62; core reg as it will not be SMP safe.
63; Thus scratch AUX reg is used (and no longer used to cache task PGD).
64; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
65; Epilogue thus has to locate the "per-cpu" storage for regs.
66; To avoid cache line bouncing the per-cpu global is aligned/sized per
67; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
68; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
69
70; As simple as that....
71;--------------------------------------------------------------------------
72
73; scratch memory to save [r0-r3] used to code TLB refill Handler
74ARCFP_DATA ex_saved_reg1
75 .align 1 << L1_CACHE_SHIFT
76 .type ex_saved_reg1, @object
77#ifdef CONFIG_SMP
78 .size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
79ex_saved_reg1:
80 .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
81#else
82 .size ex_saved_reg1, 16
83ex_saved_reg1:
84 .zero 16
85#endif
86
87.macro TLBMISS_FREEUP_REGS
88#ifdef CONFIG_SMP
89 sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
90 GET_CPU_ID r0 ; get to per cpu scratch mem,
91 lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
92 add r0, @ex_saved_reg1, r0
93#else
94 st r0, [@ex_saved_reg1]
95 mov_s r0, @ex_saved_reg1
96#endif
97 st_s r1, [r0, 4]
98 st_s r2, [r0, 8]
99 st_s r3, [r0, 12]
100
101 ; VERIFY if the ASID in MMU-PID Reg is same as
102 ; one in Linux data structures
103
104 tlb_paranoid_check_asm
105.endm
106
107.macro TLBMISS_RESTORE_REGS
108#ifdef CONFIG_SMP
109 GET_CPU_ID r0 ; get to per cpu scratch mem
110 lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
111 add r0, @ex_saved_reg1, r0
112 ld_s r3, [r0,12]
113 ld_s r2, [r0, 8]
114 ld_s r1, [r0, 4]
115 lr r0, [ARC_REG_SCRATCH_DATA0]
116#else
117 mov_s r0, @ex_saved_reg1
118 ld_s r3, [r0,12]
119 ld_s r2, [r0, 8]
120 ld_s r1, [r0, 4]
121 ld_s r0, [r0]
122#endif
123.endm
124
125#else /* ARCv2 */
126
127.macro TLBMISS_FREEUP_REGS
128 PUSH r0
129 PUSH r1
130 PUSH r2
131 PUSH r3
132.endm
133
134.macro TLBMISS_RESTORE_REGS
135 POP r3
136 POP r2
137 POP r1
138 POP r0
139.endm
140
141#endif
142
143;============================================================================
144; Troubleshooting Stuff
145;============================================================================
146
147; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
148; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
149; we use the MMU PID Reg to get current ASID.
150; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
151; So we try to detect this in TLB Mis shandler
152
153.macro tlb_paranoid_check_asm
154
155#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
156
157 GET_CURR_TASK_ON_CPU r3
158 ld r0, [r3, TASK_ACT_MM]
159 ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
160 breq r0, 0, 55f ; Error if no ASID allocated
161
162 lr r1, [ARC_REG_PID]
163 and r1, r1, 0xFF
164
165 and r2, r0, 0xFF ; MMU PID bits only for comparison
166 breq r1, r2, 5f
167
16855:
169 ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
170 lr r2, [erstatus]
171 bbit0 r2, STATUS_U_BIT, 5f
172
173 ; We sure are in troubled waters, Flag the error, but to do so
174 ; need to switch to kernel mode stack to call error routine
175 GET_TSK_STACK_BASE r3, sp
176
177 ; Call printk to shoutout aloud
178 mov r2, 1
179 j print_asid_mismatch
180
1815: ; ASIDs match so proceed normally
182 nop
183
184#endif
185
186.endm
187
188;============================================================================
189;TLB Miss handling Code
190;============================================================================
191
192;-----------------------------------------------------------------------------
193; This macro does the page-table lookup for the faulting address.
194; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
195.macro LOAD_FAULT_PTE
196
197 lr r2, [efa]
198
199#ifndef CONFIG_SMP
200 lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
201#else
202 GET_CURR_TASK_ON_CPU r1
203 ld r1, [r1, TASK_ACT_MM]
204 ld r1, [r1, MM_PGD]
205#endif
206
207 lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
208 ld.as r1, [r1, r0] ; PGD entry corresp to faulting addr
209 and.f r1, r1, PAGE_MASK ; Ignoring protection and other flags
210 ; contains Ptr to Page Table
211 bz.d do_slow_path_pf ; if no Page Table, do page fault
212
213 ; Get the PTE entry: The idea is
214 ; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr
215 ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
216 ; (3) z = pgtbl[y]
217 ; To avoid the multiply by in end, we do the -2, <<2 below
218
219 lsr r0, r2, (PAGE_SHIFT - 2)
220 and r0, r0, ( (PTRS_PER_PTE - 1) << 2)
221 ld.aw r0, [r1, r0] ; get PTE and PTE ptr for fault addr
222#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
223 and.f 0, r0, _PAGE_PRESENT
224 bz 1f
225 ld r3, [num_pte_not_present]
226 add r3, r3, 1
227 st r3, [num_pte_not_present]
2281:
229#endif
230
231.endm
232
233;-----------------------------------------------------------------
234; Convert Linux PTE entry into TLB entry
235; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
236; IN: r0 = PTE, r1 = ptr to PTE
237
238.macro CONV_PTE_TO_TLB
239 and r3, r0, PTE_BITS_RWX ; r w x
240 lsl r2, r3, 3 ; r w x 0 0 0 (GLOBAL, kernel only)
241 and.f 0, r0, _PAGE_GLOBAL
242 or.z r2, r2, r3 ; r w x r w x (!GLOBAL, user page)
243
244 and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
245 or r3, r3, r2
246
247 sr r3, [ARC_REG_TLBPD1] ; these go in PD1
248
249 and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
250
251 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
252
253 or r3, r3, r2 ; S | vaddr | {sasid|asid}
254 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
255.endm
256
257;-----------------------------------------------------------------
258; Commit the TLB entry into MMU
259
260.macro COMMIT_ENTRY_TO_MMU
261#if (CONFIG_ARC_MMU_VER < 4)
262
263 /* Get free TLB slot: Set = computed from vaddr, way = random */
264 sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
265
266 /* Commit the Write */
267#if (CONFIG_ARC_MMU_VER >= 2) /* introduced in v2 */
268 sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
269#else
270 sr TLBWrite, [ARC_REG_TLBCOMMAND]
271#endif
272
273#else
274 sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
275#endif
276.endm
277
278
279ARCFP_CODE ;Fast Path Code, candidate for ICCM
280
281;-----------------------------------------------------------------------------
282; I-TLB Miss Exception Handler
283;-----------------------------------------------------------------------------
284
285ENTRY(EV_TLBMissI)
286
287 TLBMISS_FREEUP_REGS
288
289#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
290 ld r0, [@numitlb]
291 add r0, r0, 1
292 st r0, [@numitlb]
293#endif
294
295 ;----------------------------------------------------------------
296 ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
297 LOAD_FAULT_PTE
298
299 ;----------------------------------------------------------------
300 ; VERIFY_PTE: Check if PTE permissions approp for executing code
301 cmp_s r2, VMALLOC_START
302 mov_s r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
303 or.hs r2, r2, _PAGE_GLOBAL
304
305 and r3, r0, r2 ; Mask out NON Flag bits from PTE
306 xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test )
307 bnz do_slow_path_pf
308
309 ; Let Linux VM know that the page was accessed
310 or r0, r0, _PAGE_ACCESSED ; set Accessed Bit
311 st_s r0, [r1] ; Write back PTE
312
313 CONV_PTE_TO_TLB
314 COMMIT_ENTRY_TO_MMU
315 TLBMISS_RESTORE_REGS
316EV_TLBMissI_fast_ret: ; additional label for VDK OS-kit instrumentation
317 rtie
318
319END(EV_TLBMissI)
320
321;-----------------------------------------------------------------------------
322; D-TLB Miss Exception Handler
323;-----------------------------------------------------------------------------
324
325ENTRY(EV_TLBMissD)
326
327 TLBMISS_FREEUP_REGS
328
329#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
330 ld r0, [@numdtlb]
331 add r0, r0, 1
332 st r0, [@numdtlb]
333#endif
334
335 ;----------------------------------------------------------------
336 ; Get the PTE corresponding to V-addr accessed
337 ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
338 LOAD_FAULT_PTE
339
340 ;----------------------------------------------------------------
341 ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
342
343 cmp_s r2, VMALLOC_START
344 mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE
345 or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only
346
347 ; Linux PTE [RWX] bits are semantically overloaded:
348 ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
349 ; -Otherwise they are user-mode permissions, and those are exactly
350 ; same for kernel mode as well (e.g. copy_(to|from)_user)
351
352 lr r3, [ecr]
353 btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access
354 or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE
355 btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access
356 or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE
357 ; Above laddering takes care of XCHG access (both R and W)
358
359 ; By now, r2 setup with all the Flags we need to check in PTE
360 and r3, r0, r2 ; Mask out NON Flag bits from PTE
361 brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
362
363 ;----------------------------------------------------------------
364 ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
365 lr r3, [ecr]
366 or r0, r0, _PAGE_ACCESSED ; Accessed bit always
367 btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; See if it was a Write Access ?
368 or.nz r0, r0, _PAGE_MODIFIED ; if Write, set Dirty bit as well
369 st_s r0, [r1] ; Write back PTE
370
371 CONV_PTE_TO_TLB
372
373#if (CONFIG_ARC_MMU_VER == 1)
374 ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
375 ; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
376 ; But only for old MMU or one with Metal Fix
377 TLB_WRITE_HEURISTICS
378#endif
379
380 COMMIT_ENTRY_TO_MMU
381 TLBMISS_RESTORE_REGS
382EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation
383 rtie
384
385;-------- Common routine to call Linux Page Fault Handler -----------
386do_slow_path_pf:
387
388 ; Restore the 4-scratch regs saved by fast path miss handler
389 TLBMISS_RESTORE_REGS
390
391 ; Slow path TLB Miss handled as a regular ARC Exception
392 ; (stack switching / save the complete reg-file).
393 b call_do_page_fault
394END(EV_TLBMissD)