tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2015 Microchip Technology
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17#ifndef _LAN78XX_H
18#define _LAN78XX_H
19
20/* USB Vendor Requests */
21#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
22#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
23#define USB_VENDOR_REQUEST_GET_STATS 0xA2
24
25/* Interrupt Endpoint status word bitfields */
26#define INT_ENP_EEE_START_TX_LPI_INT BIT(26)
27#define INT_ENP_EEE_STOP_TX_LPI_INT BIT(25)
28#define INT_ENP_EEE_RX_LPI_INT BIT(24)
29#define INT_ENP_RDFO_INT BIT(22)
30#define INT_ENP_TXE_INT BIT(21)
31#define INT_ENP_TX_DIS_INT BIT(19)
32#define INT_ENP_RX_DIS_INT BIT(18)
33#define INT_ENP_PHY_INT BIT(17)
34#define INT_ENP_DP_INT BIT(16)
35#define INT_ENP_MAC_ERR_INT BIT(15)
36#define INT_ENP_TDFU_INT BIT(14)
37#define INT_ENP_TDFO_INT BIT(13)
38#define INT_ENP_UTX_FP_INT BIT(12)
39
40#define TX_PKT_ALIGNMENT 4
41#define RX_PKT_ALIGNMENT 4
42
43/* Tx Command A */
44#define TX_CMD_A_IGE_ (0x20000000)
45#define TX_CMD_A_ICE_ (0x10000000)
46#define TX_CMD_A_LSO_ (0x08000000)
47#define TX_CMD_A_IPE_ (0x04000000)
48#define TX_CMD_A_TPE_ (0x02000000)
49#define TX_CMD_A_IVTG_ (0x01000000)
50#define TX_CMD_A_RVTG_ (0x00800000)
51#define TX_CMD_A_FCS_ (0x00400000)
52#define TX_CMD_A_LEN_MASK_ (0x000FFFFF)
53
54/* Tx Command B */
55#define TX_CMD_B_MSS_SHIFT_ (16)
56#define TX_CMD_B_MSS_MASK_ (0x3FFF0000)
57#define TX_CMD_B_MSS_MIN_ ((unsigned short)8)
58#define TX_CMD_B_VTAG_MASK_ (0x0000FFFF)
59#define TX_CMD_B_VTAG_PRI_MASK_ (0x0000E000)
60#define TX_CMD_B_VTAG_CFI_MASK_ (0x00001000)
61#define TX_CMD_B_VTAG_VID_MASK_ (0x00000FFF)
62
63/* Rx Command A */
64#define RX_CMD_A_ICE_ (0x80000000)
65#define RX_CMD_A_TCE_ (0x40000000)
66#define RX_CMD_A_CSE_MASK_ (0xC0000000)
67#define RX_CMD_A_IPV_ (0x20000000)
68#define RX_CMD_A_PID_MASK_ (0x18000000)
69#define RX_CMD_A_PID_NONE_IP_ (0x00000000)
70#define RX_CMD_A_PID_TCP_IP_ (0x08000000)
71#define RX_CMD_A_PID_UDP_IP_ (0x10000000)
72#define RX_CMD_A_PID_IP_ (0x18000000)
73#define RX_CMD_A_PFF_ (0x04000000)
74#define RX_CMD_A_BAM_ (0x02000000)
75#define RX_CMD_A_MAM_ (0x01000000)
76#define RX_CMD_A_FVTG_ (0x00800000)
77#define RX_CMD_A_RED_ (0x00400000)
78#define RX_CMD_A_RX_ERRS_MASK_ (0xC03F0000)
79#define RX_CMD_A_RWT_ (0x00200000)
80#define RX_CMD_A_RUNT_ (0x00100000)
81#define RX_CMD_A_LONG_ (0x00080000)
82#define RX_CMD_A_RXE_ (0x00040000)
83#define RX_CMD_A_DRB_ (0x00020000)
84#define RX_CMD_A_FCS_ (0x00010000)
85#define RX_CMD_A_UAM_ (0x00008000)
86#define RX_CMD_A_ICSM_ (0x00004000)
87#define RX_CMD_A_LEN_MASK_ (0x00003FFF)
88
89/* Rx Command B */
90#define RX_CMD_B_CSUM_SHIFT_ (16)
91#define RX_CMD_B_CSUM_MASK_ (0xFFFF0000)
92#define RX_CMD_B_VTAG_MASK_ (0x0000FFFF)
93#define RX_CMD_B_VTAG_PRI_MASK_ (0x0000E000)
94#define RX_CMD_B_VTAG_CFI_MASK_ (0x00001000)
95#define RX_CMD_B_VTAG_VID_MASK_ (0x00000FFF)
96
97/* Rx Command C */
98#define RX_CMD_C_WAKE_SHIFT_ (15)
99#define RX_CMD_C_WAKE_ (0x8000)
100#define RX_CMD_C_REF_FAIL_SHIFT_ (14)
101#define RX_CMD_C_REF_FAIL_ (0x4000)
102
103/* SCSRs */
104#define NUMBER_OF_REGS (193)
105
106#define ID_REV (0x00)
107#define ID_REV_CHIP_ID_MASK_ (0xFFFF0000)
108#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
109#define ID_REV_CHIP_ID_7800_ (0x7800)
110
111#define FPGA_REV (0x04)
112#define FPGA_REV_MINOR_MASK_ (0x0000FF00)
113#define FPGA_REV_MAJOR_MASK_ (0x000000FF)
114
115#define INT_STS (0x0C)
116#define INT_STS_CLEAR_ALL_ (0xFFFFFFFF)
117#define INT_STS_EEE_TX_LPI_STRT_ (0x04000000)
118#define INT_STS_EEE_TX_LPI_STOP_ (0x02000000)
119#define INT_STS_EEE_RX_LPI_ (0x01000000)
120#define INT_STS_RDFO_ (0x00400000)
121#define INT_STS_TXE_ (0x00200000)
122#define INT_STS_TX_DIS_ (0x00080000)
123#define INT_STS_RX_DIS_ (0x00040000)
124#define INT_STS_PHY_INT_ (0x00020000)
125#define INT_STS_DP_INT_ (0x00010000)
126#define INT_STS_MAC_ERR_ (0x00008000)
127#define INT_STS_TDFU_ (0x00004000)
128#define INT_STS_TDFO_ (0x00002000)
129#define INT_STS_UFX_FP_ (0x00001000)
130#define INT_STS_GPIO_MASK_ (0x00000FFF)
131#define INT_STS_GPIO11_ (0x00000800)
132#define INT_STS_GPIO10_ (0x00000400)
133#define INT_STS_GPIO9_ (0x00000200)
134#define INT_STS_GPIO8_ (0x00000100)
135#define INT_STS_GPIO7_ (0x00000080)
136#define INT_STS_GPIO6_ (0x00000040)
137#define INT_STS_GPIO5_ (0x00000020)
138#define INT_STS_GPIO4_ (0x00000010)
139#define INT_STS_GPIO3_ (0x00000008)
140#define INT_STS_GPIO2_ (0x00000004)
141#define INT_STS_GPIO1_ (0x00000002)
142#define INT_STS_GPIO0_ (0x00000001)
143
144#define HW_CFG (0x010)
145#define HW_CFG_CLK125_EN_ (0x02000000)
146#define HW_CFG_REFCLK25_EN_ (0x01000000)
147#define HW_CFG_LED3_EN_ (0x00800000)
148#define HW_CFG_LED2_EN_ (0x00400000)
149#define HW_CFG_LED1_EN_ (0x00200000)
150#define HW_CFG_LED0_EN_ (0x00100000)
151#define HW_CFG_EEE_PHY_LUSU_ (0x00020000)
152#define HW_CFG_EEE_TSU_ (0x00010000)
153#define HW_CFG_NETDET_STS_ (0x00008000)
154#define HW_CFG_NETDET_EN_ (0x00004000)
155#define HW_CFG_EEM_ (0x00002000)
156#define HW_CFG_RST_PROTECT_ (0x00001000)
157#define HW_CFG_CONNECT_BUF_ (0x00000400)
158#define HW_CFG_CONNECT_EN_ (0x00000200)
159#define HW_CFG_CONNECT_POL_ (0x00000100)
160#define HW_CFG_SUSPEND_N_SEL_MASK_ (0x000000C0)
161#define HW_CFG_SUSPEND_N_SEL_2 (0x00000000)
162#define HW_CFG_SUSPEND_N_SEL_12N (0x00000040)
163#define HW_CFG_SUSPEND_N_SEL_012N (0x00000080)
164#define HW_CFG_SUSPEND_N_SEL_0123N (0x000000C0)
165#define HW_CFG_SUSPEND_N_POL_ (0x00000020)
166#define HW_CFG_MEF_ (0x00000010)
167#define HW_CFG_ETC_ (0x00000008)
168#define HW_CFG_LRST_ (0x00000002)
169#define HW_CFG_SRST_ (0x00000001)
170
171#define PMT_CTL (0x014)
172#define PMT_CTL_EEE_WAKEUP_EN_ (0x00002000)
173#define PMT_CTL_EEE_WUPS_ (0x00001000)
174#define PMT_CTL_MAC_SRST_ (0x00000800)
175#define PMT_CTL_PHY_PWRUP_ (0x00000400)
176#define PMT_CTL_RES_CLR_WKP_MASK_ (0x00000300)
177#define PMT_CTL_RES_CLR_WKP_STS_ (0x00000200)
178#define PMT_CTL_RES_CLR_WKP_EN_ (0x00000100)
179#define PMT_CTL_READY_ (0x00000080)
180#define PMT_CTL_SUS_MODE_MASK_ (0x00000060)
181#define PMT_CTL_SUS_MODE_0_ (0x00000000)
182#define PMT_CTL_SUS_MODE_1_ (0x00000020)
183#define PMT_CTL_SUS_MODE_2_ (0x00000040)
184#define PMT_CTL_SUS_MODE_3_ (0x00000060)
185#define PMT_CTL_PHY_RST_ (0x00000010)
186#define PMT_CTL_WOL_EN_ (0x00000008)
187#define PMT_CTL_PHY_WAKE_EN_ (0x00000004)
188#define PMT_CTL_WUPS_MASK_ (0x00000003)
189#define PMT_CTL_WUPS_MLT_ (0x00000003)
190#define PMT_CTL_WUPS_MAC_ (0x00000002)
191#define PMT_CTL_WUPS_PHY_ (0x00000001)
192
193#define GPIO_CFG0 (0x018)
194#define GPIO_CFG0_GPIOEN_MASK_ (0x0000F000)
195#define GPIO_CFG0_GPIOEN3_ (0x00008000)
196#define GPIO_CFG0_GPIOEN2_ (0x00004000)
197#define GPIO_CFG0_GPIOEN1_ (0x00002000)
198#define GPIO_CFG0_GPIOEN0_ (0x00001000)
199#define GPIO_CFG0_GPIOBUF_MASK_ (0x00000F00)
200#define GPIO_CFG0_GPIOBUF3_ (0x00000800)
201#define GPIO_CFG0_GPIOBUF2_ (0x00000400)
202#define GPIO_CFG0_GPIOBUF1_ (0x00000200)
203#define GPIO_CFG0_GPIOBUF0_ (0x00000100)
204#define GPIO_CFG0_GPIODIR_MASK_ (0x000000F0)
205#define GPIO_CFG0_GPIODIR3_ (0x00000080)
206#define GPIO_CFG0_GPIODIR2_ (0x00000040)
207#define GPIO_CFG0_GPIODIR1_ (0x00000020)
208#define GPIO_CFG0_GPIODIR0_ (0x00000010)
209#define GPIO_CFG0_GPIOD_MASK_ (0x0000000F)
210#define GPIO_CFG0_GPIOD3_ (0x00000008)
211#define GPIO_CFG0_GPIOD2_ (0x00000004)
212#define GPIO_CFG0_GPIOD1_ (0x00000002)
213#define GPIO_CFG0_GPIOD0_ (0x00000001)
214
215#define GPIO_CFG1 (0x01C)
216#define GPIO_CFG1_GPIOEN_MASK_ (0xFF000000)
217#define GPIO_CFG1_GPIOEN11_ (0x80000000)
218#define GPIO_CFG1_GPIOEN10_ (0x40000000)
219#define GPIO_CFG1_GPIOEN9_ (0x20000000)
220#define GPIO_CFG1_GPIOEN8_ (0x10000000)
221#define GPIO_CFG1_GPIOEN7_ (0x08000000)
222#define GPIO_CFG1_GPIOEN6_ (0x04000000)
223#define GPIO_CFG1_GPIOEN5_ (0x02000000)
224#define GPIO_CFG1_GPIOEN4_ (0x01000000)
225#define GPIO_CFG1_GPIOBUF_MASK_ (0x00FF0000)
226#define GPIO_CFG1_GPIOBUF11_ (0x00800000)
227#define GPIO_CFG1_GPIOBUF10_ (0x00400000)
228#define GPIO_CFG1_GPIOBUF9_ (0x00200000)
229#define GPIO_CFG1_GPIOBUF8_ (0x00100000)
230#define GPIO_CFG1_GPIOBUF7_ (0x00080000)
231#define GPIO_CFG1_GPIOBUF6_ (0x00040000)
232#define GPIO_CFG1_GPIOBUF5_ (0x00020000)
233#define GPIO_CFG1_GPIOBUF4_ (0x00010000)
234#define GPIO_CFG1_GPIODIR_MASK_ (0x0000FF00)
235#define GPIO_CFG1_GPIODIR11_ (0x00008000)
236#define GPIO_CFG1_GPIODIR10_ (0x00004000)
237#define GPIO_CFG1_GPIODIR9_ (0x00002000)
238#define GPIO_CFG1_GPIODIR8_ (0x00001000)
239#define GPIO_CFG1_GPIODIR7_ (0x00000800)
240#define GPIO_CFG1_GPIODIR6_ (0x00000400)
241#define GPIO_CFG1_GPIODIR5_ (0x00000200)
242#define GPIO_CFG1_GPIODIR4_ (0x00000100)
243#define GPIO_CFG1_GPIOD_MASK_ (0x000000FF)
244#define GPIO_CFG1_GPIOD11_ (0x00000080)
245#define GPIO_CFG1_GPIOD10_ (0x00000040)
246#define GPIO_CFG1_GPIOD9_ (0x00000020)
247#define GPIO_CFG1_GPIOD8_ (0x00000010)
248#define GPIO_CFG1_GPIOD7_ (0x00000008)
249#define GPIO_CFG1_GPIOD6_ (0x00000004)
250#define GPIO_CFG1_GPIOD6_ (0x00000004)
251#define GPIO_CFG1_GPIOD5_ (0x00000002)
252#define GPIO_CFG1_GPIOD4_ (0x00000001)
253
254#define GPIO_WAKE (0x020)
255#define GPIO_WAKE_GPIOPOL_MASK_ (0x0FFF0000)
256#define GPIO_WAKE_GPIOPOL11_ (0x08000000)
257#define GPIO_WAKE_GPIOPOL10_ (0x04000000)
258#define GPIO_WAKE_GPIOPOL9_ (0x02000000)
259#define GPIO_WAKE_GPIOPOL8_ (0x01000000)
260#define GPIO_WAKE_GPIOPOL7_ (0x00800000)
261#define GPIO_WAKE_GPIOPOL6_ (0x00400000)
262#define GPIO_WAKE_GPIOPOL5_ (0x00200000)
263#define GPIO_WAKE_GPIOPOL4_ (0x00100000)
264#define GPIO_WAKE_GPIOPOL3_ (0x00080000)
265#define GPIO_WAKE_GPIOPOL2_ (0x00040000)
266#define GPIO_WAKE_GPIOPOL1_ (0x00020000)
267#define GPIO_WAKE_GPIOPOL0_ (0x00010000)
268#define GPIO_WAKE_GPIOWK_MASK_ (0x00000FFF)
269#define GPIO_WAKE_GPIOWK11_ (0x00000800)
270#define GPIO_WAKE_GPIOWK10_ (0x00000400)
271#define GPIO_WAKE_GPIOWK9_ (0x00000200)
272#define GPIO_WAKE_GPIOWK8_ (0x00000100)
273#define GPIO_WAKE_GPIOWK7_ (0x00000080)
274#define GPIO_WAKE_GPIOWK6_ (0x00000040)
275#define GPIO_WAKE_GPIOWK5_ (0x00000020)
276#define GPIO_WAKE_GPIOWK4_ (0x00000010)
277#define GPIO_WAKE_GPIOWK3_ (0x00000008)
278#define GPIO_WAKE_GPIOWK2_ (0x00000004)
279#define GPIO_WAKE_GPIOWK1_ (0x00000002)
280#define GPIO_WAKE_GPIOWK0_ (0x00000001)
281
282#define DP_SEL (0x024)
283#define DP_SEL_DPRDY_ (0x80000000)
284#define DP_SEL_RSEL_MASK_ (0x0000000F)
285#define DP_SEL_RSEL_USB_PHY_CSRS_ (0x0000000F)
286#define DP_SEL_RSEL_OTP_64BIT_ (0x00000009)
287#define DP_SEL_RSEL_OTP_8BIT_ (0x00000008)
288#define DP_SEL_RSEL_UTX_BUF_RAM_ (0x00000007)
289#define DP_SEL_RSEL_DESC_RAM_ (0x00000005)
290#define DP_SEL_RSEL_TXFIFO_ (0x00000004)
291#define DP_SEL_RSEL_RXFIFO_ (0x00000003)
292#define DP_SEL_RSEL_LSO_ (0x00000002)
293#define DP_SEL_RSEL_VLAN_DA_ (0x00000001)
294#define DP_SEL_RSEL_URXBUF_ (0x00000000)
295#define DP_SEL_VHF_HASH_LEN (16)
296#define DP_SEL_VHF_VLAN_LEN (128)
297
298#define DP_CMD (0x028)
299#define DP_CMD_WRITE_ (0x00000001)
300#define DP_CMD_READ_ (0x00000000)
301
302#define DP_ADDR (0x02C)
303#define DP_ADDR_MASK_ (0x00003FFF)
304
305#define DP_DATA (0x030)
306
307#define E2P_CMD (0x040)
308#define E2P_CMD_EPC_BUSY_ (0x80000000)
309#define E2P_CMD_EPC_CMD_MASK_ (0x70000000)
310#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000)
311#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000)
312#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000)
313#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000)
314#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
315#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
316#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000)
317#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
318#define E2P_CMD_EPC_TIMEOUT_ (0x00000400)
319#define E2P_CMD_EPC_DL_ (0x00000200)
320#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
321
322#define E2P_DATA (0x044)
323#define E2P_DATA_EEPROM_DATA_MASK_ (0x000000FF)
324
325#define BOS_ATTR (0x050)
326#define BOS_ATTR_BLOCK_SIZE_MASK_ (0x000000FF)
327
328#define SS_ATTR (0x054)
329#define SS_ATTR_POLL_INT_MASK_ (0x00FF0000)
330#define SS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00)
331#define SS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF)
332
333#define HS_ATTR (0x058)
334#define HS_ATTR_POLL_INT_MASK_ (0x00FF0000)
335#define HS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00)
336#define HS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF)
337
338#define FS_ATTR (0x05C)
339#define FS_ATTR_POLL_INT_MASK_ (0x00FF0000)
340#define FS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00)
341#define FS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF)
342
343#define STR_ATTR0 (0x060)
344#define STR_ATTR0_CFGSTR_DESC_SIZE_MASK_ (0xFF000000)
345#define STR_ATTR0_SERSTR_DESC_SIZE_MASK_ (0x00FF0000)
346#define STR_ATTR0_PRODSTR_DESC_SIZE_MASK_ (0x0000FF00)
347#define STR_ATTR0_MANUF_DESC_SIZE_MASK_ (0x000000FF)
348
349#define STR_ATTR1 (0x064)
350#define STR_ATTR1_INTSTR_DESC_SIZE_MASK_ (0x000000FF)
351
352#define STR_FLAG_ATTR (0x068)
353#define STR_FLAG_ATTR_PME_FLAGS_MASK_ (0x000000FF)
354
355#define USB_CFG0 (0x080)
356#define USB_CFG_LPM_RESPONSE_ (0x80000000)
357#define USB_CFG_LPM_CAPABILITY_ (0x40000000)
358#define USB_CFG_LPM_ENBL_SLPM_ (0x20000000)
359#define USB_CFG_HIRD_THR_MASK_ (0x1F000000)
360#define USB_CFG_HIRD_THR_960_ (0x1C000000)
361#define USB_CFG_HIRD_THR_885_ (0x1B000000)
362#define USB_CFG_HIRD_THR_810_ (0x1A000000)
363#define USB_CFG_HIRD_THR_735_ (0x19000000)
364#define USB_CFG_HIRD_THR_660_ (0x18000000)
365#define USB_CFG_HIRD_THR_585_ (0x17000000)
366#define USB_CFG_HIRD_THR_510_ (0x16000000)
367#define USB_CFG_HIRD_THR_435_ (0x15000000)
368#define USB_CFG_HIRD_THR_360_ (0x14000000)
369#define USB_CFG_HIRD_THR_285_ (0x13000000)
370#define USB_CFG_HIRD_THR_210_ (0x12000000)
371#define USB_CFG_HIRD_THR_135_ (0x11000000)
372#define USB_CFG_HIRD_THR_60_ (0x10000000)
373#define USB_CFG_MAX_BURST_BI_MASK_ (0x00F00000)
374#define USB_CFG_MAX_BURST_BO_MASK_ (0x000F0000)
375#define USB_CFG_MAX_DEV_SPEED_MASK_ (0x0000E000)
376#define USB_CFG_MAX_DEV_SPEED_SS_ (0x00008000)
377#define USB_CFG_MAX_DEV_SPEED_HS_ (0x00000000)
378#define USB_CFG_MAX_DEV_SPEED_FS_ (0x00002000)
379#define USB_CFG_PHY_BOOST_MASK_ (0x00000180)
380#define USB_CFG_PHY_BOOST_PLUS_12_ (0x00000180)
381#define USB_CFG_PHY_BOOST_PLUS_8_ (0x00000100)
382#define USB_CFG_PHY_BOOST_PLUS_4_ (0x00000080)
383#define USB_CFG_PHY_BOOST_NORMAL_ (0x00000000)
384#define USB_CFG_BIR_ (0x00000040)
385#define USB_CFG_BCE_ (0x00000020)
386#define USB_CFG_PORT_SWAP_ (0x00000010)
387#define USB_CFG_LPM_EN_ (0x00000008)
388#define USB_CFG_RMT_WKP_ (0x00000004)
389#define USB_CFG_PWR_SEL_ (0x00000002)
390#define USB_CFG_STALL_BO_DIS_ (0x00000001)
391
392#define USB_CFG1 (0x084)
393#define USB_CFG1_U1_TIMEOUT_MASK_ (0xFF000000)
394#define USB_CFG1_U2_TIMEOUT_MASK_ (0x00FF0000)
395#define USB_CFG1_HS_TOUT_CAL_MASK_ (0x0000E000)
396#define USB_CFG1_DEV_U2_INIT_EN_ (0x00001000)
397#define USB_CFG1_DEV_U2_EN_ (0x00000800)
398#define USB_CFG1_DEV_U1_INIT_EN_ (0x00000400)
399#define USB_CFG1_DEV_U1_EN_ (0x00000200)
400#define USB_CFG1_LTM_ENABLE_ (0x00000100)
401#define USB_CFG1_FS_TOUT_CAL_MASK_ (0x00000070)
402#define USB_CFG1_SCALE_DOWN_MASK_ (0x00000003)
403#define USB_CFG1_SCALE_DOWN_MODE3_ (0x00000003)
404#define USB_CFG1_SCALE_DOWN_MODE2_ (0x00000002)
405#define USB_CFG1_SCALE_DOWN_MODE1_ (0x00000001)
406#define USB_CFG1_SCALE_DOWN_MODE0_ (0x00000000)
407
408#define USB_CFG2 (0x088)
409#define USB_CFG2_SS_DETACH_TIME_MASK_ (0xFFFF0000)
410#define USB_CFG2_HS_DETACH_TIME_MASK_ (0x0000FFFF)
411
412#define BURST_CAP (0x090)
413#define BURST_CAP_SIZE_MASK_ (0x000000FF)
414
415#define BULK_IN_DLY (0x094)
416#define BULK_IN_DLY_MASK_ (0x0000FFFF)
417
418#define INT_EP_CTL (0x098)
419#define INT_EP_INTEP_ON_ (0x80000000)
420#define INT_STS_EEE_TX_LPI_STRT_EN_ (0x04000000)
421#define INT_STS_EEE_TX_LPI_STOP_EN_ (0x02000000)
422#define INT_STS_EEE_RX_LPI_EN_ (0x01000000)
423#define INT_EP_RDFO_EN_ (0x00400000)
424#define INT_EP_TXE_EN_ (0x00200000)
425#define INT_EP_TX_DIS_EN_ (0x00080000)
426#define INT_EP_RX_DIS_EN_ (0x00040000)
427#define INT_EP_PHY_INT_EN_ (0x00020000)
428#define INT_EP_DP_INT_EN_ (0x00010000)
429#define INT_EP_MAC_ERR_EN_ (0x00008000)
430#define INT_EP_TDFU_EN_ (0x00004000)
431#define INT_EP_TDFO_EN_ (0x00002000)
432#define INT_EP_UTX_FP_EN_ (0x00001000)
433#define INT_EP_GPIO_EN_MASK_ (0x00000FFF)
434
435#define PIPE_CTL (0x09C)
436#define PIPE_CTL_TXSWING_ (0x00000040)
437#define PIPE_CTL_TXMARGIN_MASK_ (0x00000038)
438#define PIPE_CTL_TXDEEMPHASIS_MASK_ (0x00000006)
439#define PIPE_CTL_ELASTICITYBUFFERMODE_ (0x00000001)
440
441#define U1_LATENCY (0xA0)
442#define U2_LATENCY (0xA4)
443
444#define USB_STATUS (0x0A8)
445#define USB_STATUS_REMOTE_WK_ (0x00100000)
446#define USB_STATUS_FUNC_REMOTE_WK_ (0x00080000)
447#define USB_STATUS_LTM_ENABLE_ (0x00040000)
448#define USB_STATUS_U2_ENABLE_ (0x00020000)
449#define USB_STATUS_U1_ENABLE_ (0x00010000)
450#define USB_STATUS_SET_SEL_ (0x00000020)
451#define USB_STATUS_REMOTE_WK_STS_ (0x00000010)
452#define USB_STATUS_FUNC_REMOTE_WK_STS_ (0x00000008)
453#define USB_STATUS_LTM_ENABLE_STS_ (0x00000004)
454#define USB_STATUS_U2_ENABLE_STS_ (0x00000002)
455#define USB_STATUS_U1_ENABLE_STS_ (0x00000001)
456
457#define USB_CFG3 (0x0AC)
458#define USB_CFG3_EN_U2_LTM_ (0x40000000)
459#define USB_CFG3_BULK_OUT_NUMP_OVR_ (0x20000000)
460#define USB_CFG3_DIS_FAST_U1_EXIT_ (0x10000000)
461#define USB_CFG3_LPM_NYET_THR_ (0x0F000000)
462#define USB_CFG3_RX_DET_2_POL_LFPS_ (0x00800000)
463#define USB_CFG3_LFPS_FILT_ (0x00400000)
464#define USB_CFG3_SKIP_RX_DET_ (0x00200000)
465#define USB_CFG3_DELAY_P1P2P3_ (0x001C0000)
466#define USB_CFG3_DELAY_PHY_PWR_CHG_ (0x00020000)
467#define USB_CFG3_U1U2_EXIT_FR_ (0x00010000)
468#define USB_CFG3_REQ_P1P2P3 (0x00008000)
469#define USB_CFG3_HST_PRT_CMPL_ (0x00004000)
470#define USB_CFG3_DIS_SCRAMB_ (0x00002000)
471#define USB_CFG3_PWR_DN_SCALE_ (0x00001FFF)
472
473#define RFE_CTL (0x0B0)
474#define RFE_CTL_IGMP_COE_ (0x00004000)
475#define RFE_CTL_ICMP_COE_ (0x00002000)
476#define RFE_CTL_TCPUDP_COE_ (0x00001000)
477#define RFE_CTL_IP_COE_ (0x00000800)
478#define RFE_CTL_BCAST_EN_ (0x00000400)
479#define RFE_CTL_MCAST_EN_ (0x00000200)
480#define RFE_CTL_UCAST_EN_ (0x00000100)
481#define RFE_CTL_VLAN_STRIP_ (0x00000080)
482#define RFE_CTL_DISCARD_UNTAGGED_ (0x00000040)
483#define RFE_CTL_VLAN_FILTER_ (0x00000020)
484#define RFE_CTL_SA_FILTER_ (0x00000010)
485#define RFE_CTL_MCAST_HASH_ (0x00000008)
486#define RFE_CTL_DA_HASH_ (0x00000004)
487#define RFE_CTL_DA_PERFECT_ (0x00000002)
488#define RFE_CTL_RST_ (0x00000001)
489
490#define VLAN_TYPE (0x0B4)
491#define VLAN_TYPE_MASK_ (0x0000FFFF)
492
493#define FCT_RX_CTL (0x0C0)
494#define FCT_RX_CTL_EN_ (0x80000000)
495#define FCT_RX_CTL_RST_ (0x40000000)
496#define FCT_RX_CTL_SBF_ (0x02000000)
497#define FCT_RX_CTL_OVFL_ (0x01000000)
498#define FCT_RX_CTL_DROP_ (0x00800000)
499#define FCT_RX_CTL_NOT_EMPTY_ (0x00400000)
500#define FCT_RX_CTL_EMPTY_ (0x00200000)
501#define FCT_RX_CTL_DIS_ (0x00100000)
502#define FCT_RX_CTL_USED_MASK_ (0x0000FFFF)
503
504#define FCT_TX_CTL (0x0C4)
505#define FCT_TX_CTL_EN_ (0x80000000)
506#define FCT_TX_CTL_RST_ (0x40000000)
507#define FCT_TX_CTL_NOT_EMPTY_ (0x00400000)
508#define FCT_TX_CTL_EMPTY_ (0x00200000)
509#define FCT_TX_CTL_DIS_ (0x00100000)
510#define FCT_TX_CTL_USED_MASK_ (0x0000FFFF)
511
512#define FCT_RX_FIFO_END (0x0C8)
513#define FCT_RX_FIFO_END_MASK_ (0x0000007F)
514
515#define FCT_TX_FIFO_END (0x0CC)
516#define FCT_TX_FIFO_END_MASK_ (0x0000003F)
517
518#define FCT_FLOW (0x0D0)
519#define FCT_FLOW_OFF_MASK_ (0x00007F00)
520#define FCT_FLOW_ON_MASK_ (0x0000007F)
521
522#define RX_DP_STOR (0x0D4)
523#define RX_DP_STORE_TOT_RXUSED_MASK_ (0xFFFF0000)
524#define RX_DP_STORE_UTX_RXUSED_MASK_ (0x0000FFFF)
525
526#define TX_DP_STOR (0x0D8)
527#define TX_DP_STORE_TOT_TXUSED_MASK_ (0xFFFF0000)
528#define TX_DP_STORE_URX_TXUSED_MASK_ (0x0000FFFF)
529
530#define LTM_BELT_IDLE0 (0x0E0)
531#define LTM_BELT_IDLE0_IDLE1000_ (0x0FFF0000)
532#define LTM_BELT_IDLE0_IDLE100_ (0x00000FFF)
533
534#define LTM_BELT_IDLE1 (0x0E4)
535#define LTM_BELT_IDLE1_IDLE10_ (0x00000FFF)
536
537#define LTM_BELT_ACT0 (0x0E8)
538#define LTM_BELT_ACT0_ACT1000_ (0x0FFF0000)
539#define LTM_BELT_ACT0_ACT100_ (0x00000FFF)
540
541#define LTM_BELT_ACT1 (0x0EC)
542#define LTM_BELT_ACT1_ACT10_ (0x00000FFF)
543
544#define LTM_INACTIVE0 (0x0F0)
545#define LTM_INACTIVE0_TIMER1000_ (0xFFFF0000)
546#define LTM_INACTIVE0_TIMER100_ (0x0000FFFF)
547
548#define LTM_INACTIVE1 (0x0F4)
549#define LTM_INACTIVE1_TIMER10_ (0x0000FFFF)
550
551#define MAC_CR (0x100)
552#define MAC_CR_GMII_EN_ (0x00080000)
553#define MAC_CR_EEE_TX_CLK_STOP_EN_ (0x00040000)
554#define MAC_CR_EEE_EN_ (0x00020000)
555#define MAC_CR_EEE_TLAR_EN_ (0x00010000)
556#define MAC_CR_ADP_ (0x00002000)
557#define MAC_CR_AUTO_DUPLEX_ (0x00001000)
558#define MAC_CR_AUTO_SPEED_ (0x00000800)
559#define MAC_CR_LOOPBACK_ (0x00000400)
560#define MAC_CR_BOLMT_MASK_ (0x000000C0)
561#define MAC_CR_FULL_DUPLEX_ (0x00000008)
562#define MAC_CR_SPEED_MASK_ (0x00000006)
563#define MAC_CR_SPEED_1000_ (0x00000004)
564#define MAC_CR_SPEED_100_ (0x00000002)
565#define MAC_CR_SPEED_10_ (0x00000000)
566#define MAC_CR_RST_ (0x00000001)
567
568#define MAC_RX (0x104)
569#define MAC_RX_MAX_SIZE_SHIFT_ (16)
570#define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
571#define MAC_RX_FCS_STRIP_ (0x00000010)
572#define MAC_RX_VLAN_FSE_ (0x00000004)
573#define MAC_RX_RXD_ (0x00000002)
574#define MAC_RX_RXEN_ (0x00000001)
575
576#define MAC_TX (0x108)
577#define MAC_TX_BAD_FCS_ (0x00000004)
578#define MAC_TX_TXD_ (0x00000002)
579#define MAC_TX_TXEN_ (0x00000001)
580
581#define FLOW (0x10C)
582#define FLOW_CR_FORCE_FC_ (0x80000000)
583#define FLOW_CR_TX_FCEN_ (0x40000000)
584#define FLOW_CR_RX_FCEN_ (0x20000000)
585#define FLOW_CR_FPF_ (0x10000000)
586#define FLOW_CR_FCPT_MASK_ (0x0000FFFF)
587
588#define RAND_SEED (0x110)
589#define RAND_SEED_MASK_ (0x0000FFFF)
590
591#define ERR_STS (0x114)
592#define ERR_STS_FERR_ (0x00000100)
593#define ERR_STS_LERR_ (0x00000080)
594#define ERR_STS_RFERR_ (0x00000040)
595#define ERR_STS_ECERR_ (0x00000010)
596#define ERR_STS_ALERR_ (0x00000008)
597#define ERR_STS_URERR_ (0x00000004)
598
599#define RX_ADDRH (0x118)
600#define RX_ADDRH_MASK_ (0x0000FFFF)
601
602#define RX_ADDRL (0x11C)
603#define RX_ADDRL_MASK_ (0xFFFFFFFF)
604
605#define MII_ACC (0x120)
606#define MII_ACC_PHY_ADDR_SHIFT_ (11)
607#define MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
608#define MII_ACC_MIIRINDA_SHIFT_ (6)
609#define MII_ACC_MIIRINDA_MASK_ (0x000007C0)
610#define MII_ACC_MII_READ_ (0x00000000)
611#define MII_ACC_MII_WRITE_ (0x00000002)
612#define MII_ACC_MII_BUSY_ (0x00000001)
613
614#define MII_DATA (0x124)
615#define MII_DATA_MASK_ (0x0000FFFF)
616
617#define MAC_RGMII_ID (0x128)
618#define MAC_RGMII_ID_TXC_DELAY_EN_ (0x00000002)
619#define MAC_RGMII_ID_RXC_DELAY_EN_ (0x00000001)
620
621#define EEE_TX_LPI_REQ_DLY (0x130)
622#define EEE_TX_LPI_REQ_DLY_CNT_MASK_ (0xFFFFFFFF)
623
624#define EEE_TW_TX_SYS (0x134)
625#define EEE_TW_TX_SYS_CNT1G_MASK_ (0xFFFF0000)
626#define EEE_TW_TX_SYS_CNT100M_MASK_ (0x0000FFFF)
627
628#define EEE_TX_LPI_REM_DLY (0x138)
629#define EEE_TX_LPI_REM_DLY_CNT_ (0x00FFFFFF)
630
631#define WUCSR (0x140)
632#define WUCSR_TESTMODE_ (0x80000000)
633#define WUCSR_RFE_WAKE_EN_ (0x00004000)
634#define WUCSR_EEE_TX_WAKE_ (0x00002000)
635#define WUCSR_EEE_TX_WAKE_EN_ (0x00001000)
636#define WUCSR_EEE_RX_WAKE_ (0x00000800)
637#define WUCSR_EEE_RX_WAKE_EN_ (0x00000400)
638#define WUCSR_RFE_WAKE_FR_ (0x00000200)
639#define WUCSR_STORE_WAKE_ (0x00000100)
640#define WUCSR_PFDA_FR_ (0x00000080)
641#define WUCSR_WUFR_ (0x00000040)
642#define WUCSR_MPR_ (0x00000020)
643#define WUCSR_BCST_FR_ (0x00000010)
644#define WUCSR_PFDA_EN_ (0x00000008)
645#define WUCSR_WAKE_EN_ (0x00000004)
646#define WUCSR_MPEN_ (0x00000002)
647#define WUCSR_BCST_EN_ (0x00000001)
648
649#define WK_SRC (0x144)
650#define WK_SRC_GPIOX_INT_WK_SHIFT_ (20)
651#define WK_SRC_GPIOX_INT_WK_MASK_ (0xFFF00000)
652#define WK_SRC_IPV6_TCPSYN_RCD_WK_ (0x00010000)
653#define WK_SRC_IPV4_TCPSYN_RCD_WK_ (0x00008000)
654#define WK_SRC_EEE_TX_WK_ (0x00004000)
655#define WK_SRC_EEE_RX_WK_ (0x00002000)
656#define WK_SRC_GOOD_FR_WK_ (0x00001000)
657#define WK_SRC_PFDA_FR_WK_ (0x00000800)
658#define WK_SRC_MP_FR_WK_ (0x00000400)
659#define WK_SRC_BCAST_FR_WK_ (0x00000200)
660#define WK_SRC_WU_FR_WK_ (0x00000100)
661#define WK_SRC_WUFF_MATCH_MASK_ (0x0000001F)
662
663#define WUF_CFG0 (0x150)
664#define NUM_OF_WUF_CFG (32)
665#define WUF_CFG_BEGIN (WUF_CFG0)
666#define WUF_CFG(index) (WUF_CFG_BEGIN + (4 * (index)))
667#define WUF_CFGX_EN_ (0x80000000)
668#define WUF_CFGX_TYPE_MASK_ (0x03000000)
669#define WUF_CFGX_TYPE_MCAST_ (0x02000000)
670#define WUF_CFGX_TYPE_ALL_ (0x01000000)
671#define WUF_CFGX_TYPE_UCAST_ (0x00000000)
672#define WUF_CFGX_OFFSET_SHIFT_ (16)
673#define WUF_CFGX_OFFSET_MASK_ (0x00FF0000)
674#define WUF_CFGX_CRC16_MASK_ (0x0000FFFF)
675
676#define WUF_MASK0_0 (0x200)
677#define WUF_MASK0_1 (0x204)
678#define WUF_MASK0_2 (0x208)
679#define WUF_MASK0_3 (0x20C)
680#define NUM_OF_WUF_MASK (32)
681#define WUF_MASK0_BEGIN (WUF_MASK0_0)
682#define WUF_MASK1_BEGIN (WUF_MASK0_1)
683#define WUF_MASK2_BEGIN (WUF_MASK0_2)
684#define WUF_MASK3_BEGIN (WUF_MASK0_3)
685#define WUF_MASK0(index) (WUF_MASK0_BEGIN + (0x10 * (index)))
686#define WUF_MASK1(index) (WUF_MASK1_BEGIN + (0x10 * (index)))
687#define WUF_MASK2(index) (WUF_MASK2_BEGIN + (0x10 * (index)))
688#define WUF_MASK3(index) (WUF_MASK3_BEGIN + (0x10 * (index)))
689
690#define MAF_BASE (0x400)
691#define MAF_HIX (0x00)
692#define MAF_LOX (0x04)
693#define NUM_OF_MAF (33)
694#define MAF_HI_BEGIN (MAF_BASE + MAF_HIX)
695#define MAF_LO_BEGIN (MAF_BASE + MAF_LOX)
696#define MAF_HI(index) (MAF_BASE + (8 * (index)) + (MAF_HIX))
697#define MAF_LO(index) (MAF_BASE + (8 * (index)) + (MAF_LOX))
698#define MAF_HI_VALID_ (0x80000000)
699#define MAF_HI_TYPE_MASK_ (0x40000000)
700#define MAF_HI_TYPE_SRC_ (0x40000000)
701#define MAF_HI_TYPE_DST_ (0x00000000)
702#define MAF_HI_ADDR_MASK (0x0000FFFF)
703#define MAF_LO_ADDR_MASK (0xFFFFFFFF)
704
705#define WUCSR2 (0x600)
706#define WUCSR2_CSUM_DISABLE_ (0x80000000)
707#define WUCSR2_NA_SA_SEL_ (0x00000100)
708#define WUCSR2_NS_RCD_ (0x00000080)
709#define WUCSR2_ARP_RCD_ (0x00000040)
710#define WUCSR2_IPV6_TCPSYN_RCD_ (0x00000020)
711#define WUCSR2_IPV4_TCPSYN_RCD_ (0x00000010)
712#define WUCSR2_NS_OFFLOAD_EN_ (0x00000008)
713#define WUCSR2_ARP_OFFLOAD_EN_ (0x00000004)
714#define WUCSR2_IPV6_TCPSYN_WAKE_EN_ (0x00000002)
715#define WUCSR2_IPV4_TCPSYN_WAKE_EN_ (0x00000001)
716
717#define NS1_IPV6_ADDR_DEST0 (0x610)
718#define NS1_IPV6_ADDR_DEST1 (0x614)
719#define NS1_IPV6_ADDR_DEST2 (0x618)
720#define NS1_IPV6_ADDR_DEST3 (0x61C)
721
722#define NS1_IPV6_ADDR_SRC0 (0x620)
723#define NS1_IPV6_ADDR_SRC1 (0x624)
724#define NS1_IPV6_ADDR_SRC2 (0x628)
725#define NS1_IPV6_ADDR_SRC3 (0x62C)
726
727#define NS1_ICMPV6_ADDR0_0 (0x630)
728#define NS1_ICMPV6_ADDR0_1 (0x634)
729#define NS1_ICMPV6_ADDR0_2 (0x638)
730#define NS1_ICMPV6_ADDR0_3 (0x63C)
731
732#define NS1_ICMPV6_ADDR1_0 (0x640)
733#define NS1_ICMPV6_ADDR1_1 (0x644)
734#define NS1_ICMPV6_ADDR1_2 (0x648)
735#define NS1_ICMPV6_ADDR1_3 (0x64C)
736
737#define NS2_IPV6_ADDR_DEST0 (0x650)
738#define NS2_IPV6_ADDR_DEST1 (0x654)
739#define NS2_IPV6_ADDR_DEST2 (0x658)
740#define NS2_IPV6_ADDR_DEST3 (0x65C)
741
742#define NS2_IPV6_ADDR_SRC0 (0x660)
743#define NS2_IPV6_ADDR_SRC1 (0x664)
744#define NS2_IPV6_ADDR_SRC2 (0x668)
745#define NS2_IPV6_ADDR_SRC3 (0x66C)
746
747#define NS2_ICMPV6_ADDR0_0 (0x670)
748#define NS2_ICMPV6_ADDR0_1 (0x674)
749#define NS2_ICMPV6_ADDR0_2 (0x678)
750#define NS2_ICMPV6_ADDR0_3 (0x67C)
751
752#define NS2_ICMPV6_ADDR1_0 (0x680)
753#define NS2_ICMPV6_ADDR1_1 (0x684)
754#define NS2_ICMPV6_ADDR1_2 (0x688)
755#define NS2_ICMPV6_ADDR1_3 (0x68C)
756
757#define SYN_IPV4_ADDR_SRC (0x690)
758#define SYN_IPV4_ADDR_DEST (0x694)
759#define SYN_IPV4_TCP_PORTS (0x698)
760#define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_SHIFT_ (16)
761#define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_MASK_ (0xFFFF0000)
762#define SYN_IPV4_TCP_PORTS_IPV4_SRC_PORT_MASK_ (0x0000FFFF)
763
764#define SYN_IPV6_ADDR_SRC0 (0x69C)
765#define SYN_IPV6_ADDR_SRC1 (0x6A0)
766#define SYN_IPV6_ADDR_SRC2 (0x6A4)
767#define SYN_IPV6_ADDR_SRC3 (0x6A8)
768
769#define SYN_IPV6_ADDR_DEST0 (0x6AC)
770#define SYN_IPV6_ADDR_DEST1 (0x6B0)
771#define SYN_IPV6_ADDR_DEST2 (0x6B4)
772#define SYN_IPV6_ADDR_DEST3 (0x6B8)
773
774#define SYN_IPV6_TCP_PORTS (0x6BC)
775#define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_SHIFT_ (16)
776#define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_MASK_ (0xFFFF0000)
777#define SYN_IPV6_TCP_PORTS_IPV6_SRC_PORT_MASK_ (0x0000FFFF)
778
779#define ARP_SPA (0x6C0)
780#define ARP_TPA (0x6C4)
781
782#define PHY_DEV_ID (0x700)
783#define PHY_DEV_ID_REV_SHIFT_ (28)
784#define PHY_DEV_ID_REV_SHIFT_ (28)
785#define PHY_DEV_ID_REV_MASK_ (0xF0000000)
786#define PHY_DEV_ID_MODEL_SHIFT_ (22)
787#define PHY_DEV_ID_MODEL_MASK_ (0x0FC00000)
788#define PHY_DEV_ID_OUI_MASK_ (0x003FFFFF)
789
790#define OTP_BASE_ADDR (0x00001000)
791#define OTP_ADDR_RANGE_ (0x1FF)
792
793#define OTP_PWR_DN (OTP_BASE_ADDR + 4 * 0x00)
794#define OTP_PWR_DN_PWRDN_N_ (0x01)
795
796#define OTP_ADDR1 (OTP_BASE_ADDR + 4 * 0x01)
797#define OTP_ADDR1_15_11 (0x1F)
798
799#define OTP_ADDR2 (OTP_BASE_ADDR + 4 * 0x02)
800#define OTP_ADDR2_10_3 (0xFF)
801
802#define OTP_ADDR3 (OTP_BASE_ADDR + 4 * 0x03)
803#define OTP_ADDR3_2_0 (0x03)
804
805#define OTP_PRGM_DATA (OTP_BASE_ADDR + 4 * 0x04)
806
807#define OTP_PRGM_MODE (OTP_BASE_ADDR + 4 * 0x05)
808#define OTP_PRGM_MODE_BYTE_ (0x01)
809
810#define OTP_RD_DATA (OTP_BASE_ADDR + 4 * 0x06)
811
812#define OTP_FUNC_CMD (OTP_BASE_ADDR + 4 * 0x08)
813#define OTP_FUNC_CMD_RESET_ (0x04)
814#define OTP_FUNC_CMD_PROGRAM_ (0x02)
815#define OTP_FUNC_CMD_READ_ (0x01)
816
817#define OTP_TST_CMD (OTP_BASE_ADDR + 4 * 0x09)
818#define OTP_TST_CMD_TEST_DEC_SEL_ (0x10)
819#define OTP_TST_CMD_PRGVRFY_ (0x08)
820#define OTP_TST_CMD_WRTEST_ (0x04)
821#define OTP_TST_CMD_TESTDEC_ (0x02)
822#define OTP_TST_CMD_BLANKCHECK_ (0x01)
823
824#define OTP_CMD_GO (OTP_BASE_ADDR + 4 * 0x0A)
825#define OTP_CMD_GO_GO_ (0x01)
826
827#define OTP_PASS_FAIL (OTP_BASE_ADDR + 4 * 0x0B)
828#define OTP_PASS_FAIL_PASS_ (0x02)
829#define OTP_PASS_FAIL_FAIL_ (0x01)
830
831#define OTP_STATUS (OTP_BASE_ADDR + 4 * 0x0C)
832#define OTP_STATUS_OTP_LOCK_ (0x10)
833#define OTP_STATUS_WEB_ (0x08)
834#define OTP_STATUS_PGMEN (0x04)
835#define OTP_STATUS_CPUMPEN_ (0x02)
836#define OTP_STATUS_BUSY_ (0x01)
837
838#define OTP_MAX_PRG (OTP_BASE_ADDR + 4 * 0x0D)
839#define OTP_MAX_PRG_MAX_PROG (0x1F)
840
841#define OTP_INTR_STATUS (OTP_BASE_ADDR + 4 * 0x10)
842#define OTP_INTR_STATUS_READY_ (0x01)
843
844#define OTP_INTR_MASK (OTP_BASE_ADDR + 4 * 0x11)
845#define OTP_INTR_MASK_READY_ (0x01)
846
847#define OTP_RSTB_PW1 (OTP_BASE_ADDR + 4 * 0x14)
848#define OTP_RSTB_PW2 (OTP_BASE_ADDR + 4 * 0x15)
849#define OTP_PGM_PW1 (OTP_BASE_ADDR + 4 * 0x18)
850#define OTP_PGM_PW2 (OTP_BASE_ADDR + 4 * 0x19)
851#define OTP_READ_PW1 (OTP_BASE_ADDR + 4 * 0x1C)
852#define OTP_READ_PW2 (OTP_BASE_ADDR + 4 * 0x1D)
853#define OTP_TCRST (OTP_BASE_ADDR + 4 * 0x20)
854#define OTP_RSRD (OTP_BASE_ADDR + 4 * 0x21)
855#define OTP_TREADEN_VAL (OTP_BASE_ADDR + 4 * 0x22)
856#define OTP_TDLES_VAL (OTP_BASE_ADDR + 4 * 0x23)
857#define OTP_TWWL_VAL (OTP_BASE_ADDR + 4 * 0x24)
858#define OTP_TDLEH_VAL (OTP_BASE_ADDR + 4 * 0x25)
859#define OTP_TWPED_VAL (OTP_BASE_ADDR + 4 * 0x26)
860#define OTP_TPES_VAL (OTP_BASE_ADDR + 4 * 0x27)
861#define OTP_TCPS_VAL (OTP_BASE_ADDR + 4 * 0x28)
862#define OTP_TCPH_VAL (OTP_BASE_ADDR + 4 * 0x29)
863#define OTP_TPGMVFY_VAL (OTP_BASE_ADDR + 4 * 0x2A)
864#define OTP_TPEH_VAL (OTP_BASE_ADDR + 4 * 0x2B)
865#define OTP_TPGRST_VAL (OTP_BASE_ADDR + 4 * 0x2C)
866#define OTP_TCLES_VAL (OTP_BASE_ADDR + 4 * 0x2D)
867#define OTP_TCLEH_VAL (OTP_BASE_ADDR + 4 * 0x2E)
868#define OTP_TRDES_VAL (OTP_BASE_ADDR + 4 * 0x2F)
869#define OTP_TBCACC_VAL (OTP_BASE_ADDR + 4 * 0x30)
870#define OTP_TAAC_VAL (OTP_BASE_ADDR + 4 * 0x31)
871#define OTP_TACCT_VAL (OTP_BASE_ADDR + 4 * 0x32)
872#define OTP_TRDEP_VAL (OTP_BASE_ADDR + 4 * 0x38)
873#define OTP_TPGSV_VAL (OTP_BASE_ADDR + 4 * 0x39)
874#define OTP_TPVSR_VAL (OTP_BASE_ADDR + 4 * 0x3A)
875#define OTP_TPVHR_VAL (OTP_BASE_ADDR + 4 * 0x3B)
876#define OTP_TPVSA_VAL (OTP_BASE_ADDR + 4 * 0x3C)
877
878#define PHY_ID1 (0x02)
879#define PHY_ID2 (0x03)
880
881#define PHY_DEV_ID_OUI_VTSE (0x04001C)
882#define PHY_DEV_ID_MODEL_VTSE_8502 (0x23)
883
884#define PHY_AUTONEG_ADV (0x04)
885#define NWAY_AR_NEXT_PAGE_ (0x8000)
886#define NWAY_AR_REMOTE_FAULT_ (0x2000)
887#define NWAY_AR_ASM_DIR_ (0x0800)
888#define NWAY_AR_PAUSE_ (0x0400)
889#define NWAY_AR_100T4_CAPS_ (0x0200)
890#define NWAY_AR_100TX_FD_CAPS_ (0x0100)
891#define NWAY_AR_SELECTOR_FIELD_ (0x001F)
892#define NWAY_AR_100TX_HD_CAPS_ (0x0080)
893#define NWAY_AR_10T_FD_CAPS_ (0x0040)
894#define NWAY_AR_10T_HD_CAPS_ (0x0020)
895#define NWAY_AR_ALL_CAPS_ (NWAY_AR_10T_HD_CAPS_ | \
896 NWAY_AR_10T_FD_CAPS_ | \
897 NWAY_AR_100TX_HD_CAPS_ | \
898 NWAY_AR_100TX_FD_CAPS_)
899#define NWAY_AR_PAUSE_MASK (NWAY_AR_PAUSE_ | NWAY_AR_ASM_DIR_)
900
901#define PHY_LP_ABILITY (0x05)
902#define NWAY_LPAR_NEXT_PAGE_ (0x8000)
903#define NWAY_LPAR_ACKNOWLEDGE_ (0x4000)
904#define NWAY_LPAR_REMOTE_FAULT_ (0x2000)
905#define NWAY_LPAR_ASM_DIR_ (0x0800)
906#define NWAY_LPAR_PAUSE_ (0x0400)
907#define NWAY_LPAR_100T4_CAPS_ (0x0200)
908#define NWAY_LPAR_100TX_FD_CAPS_ (0x0100)
909#define NWAY_LPAR_100TX_HD_CAPS_ (0x0080)
910#define NWAY_LPAR_10T_FD_CAPS_ (0x0040)
911#define NWAY_LPAR_10T_HD_CAPS_ (0x0020)
912#define NWAY_LPAR_SELECTOR_FIELD_ (0x001F)
913
914#define PHY_AUTONEG_EXP (0x06)
915#define NWAY_ER_PAR_DETECT_FAULT_ (0x0010)
916#define NWAY_ER_LP_NEXT_PAGE_CAPS_ (0x0008)
917#define NWAY_ER_NEXT_PAGE_CAPS_ (0x0004)
918#define NWAY_ER_PAGE_RXD_ (0x0002)
919#define NWAY_ER_LP_NWAY_CAPS_ (0x0001)
920
921#define PHY_NEXT_PAGE_TX (0x07)
922#define NPTX_NEXT_PAGE_ (0x8000)
923#define NPTX_MSG_PAGE_ (0x2000)
924#define NPTX_ACKNOWLDGE2_ (0x1000)
925#define NPTX_TOGGLE_ (0x0800)
926#define NPTX_MSG_CODE_FIELD_ (0x0001)
927
928#define PHY_LP_NEXT_PAGE (0x08)
929#define LP_RNPR_NEXT_PAGE_ (0x8000)
930#define LP_RNPR_ACKNOWLDGE_ (0x4000)
931#define LP_RNPR_MSG_PAGE_ (0x2000)
932#define LP_RNPR_ACKNOWLDGE2_ (0x1000)
933#define LP_RNPR_TOGGLE_ (0x0800)
934#define LP_RNPR_MSG_CODE_FIELD_ (0x0001)
935
936#define PHY_1000T_CTRL (0x09)
937#define CR_1000T_TEST_MODE_4_ (0x8000)
938#define CR_1000T_TEST_MODE_3_ (0x6000)
939#define CR_1000T_TEST_MODE_2_ (0x4000)
940#define CR_1000T_TEST_MODE_1_ (0x2000)
941#define CR_1000T_MS_ENABLE_ (0x1000)
942#define CR_1000T_MS_VALUE_ (0x0800)
943#define CR_1000T_REPEATER_DTE_ (0x0400)
944#define CR_1000T_FD_CAPS_ (0x0200)
945#define CR_1000T_HD_CAPS_ (0x0100)
946#define CR_1000T_ASYM_PAUSE_ (0x0080)
947#define CR_1000T_TEST_MODE_NORMAL_ (0x0000)
948
949#define PHY_1000T_STATUS (0x0A)
950#define SR_1000T_MS_CONFIG_FAULT_ (0x8000)
951#define SR_1000T_MS_CONFIG_RES_ (0x4000)
952#define SR_1000T_LOCAL_RX_STATUS_ (0x2000)
953#define SR_1000T_REMOTE_RX_STATUS_ (0x1000)
954#define SR_1000T_LP_FD_CAPS_ (0x0800)
955#define SR_1000T_LP_HD_CAPS_ (0x0400)
956#define SR_1000T_ASYM_PAUSE_DIR_ (0x0100)
957#define SR_1000T_IDLE_ERROR_CNT_ (0x00FF)
958#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
959#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
960#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
961#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
962#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
963
964#define PHY_EXT_STATUS (0x0F)
965#define IEEE_ESR_1000X_FD_CAPS_ (0x8000)
966#define IEEE_ESR_1000X_HD_CAPS_ (0x4000)
967#define IEEE_ESR_1000T_FD_CAPS_ (0x2000)
968#define IEEE_ESR_1000T_HD_CAPS_ (0x1000)
969#define PHY_TX_POLARITY_MASK_ (0x0100)
970#define PHY_TX_NORMAL_POLARITY_ (0x0000)
971#define AUTO_POLARITY_DISABLE_ (0x0010)
972
973#define PHY_MMD_CTL (0x0D)
974#define PHY_MMD_CTRL_OP_MASK_ (0xC000)
975#define PHY_MMD_CTRL_OP_REG_ (0x0000)
976#define PHY_MMD_CTRL_OP_DNI_ (0x4000)
977#define PHY_MMD_CTRL_OP_DPIRW_ (0x8000)
978#define PHY_MMD_CTRL_OP_DPIWO_ (0xC000)
979#define PHY_MMD_CTRL_DEV_ADDR_MASK_ (0x001F)
980
981#define PHY_MMD_REG_DATA (0x0E)
982
983/* VTSE Vendor Specific registers */
984#define PHY_VTSE_BYPASS (0x12)
985#define PHY_VTSE_BYPASS_DISABLE_PAIR_SWAP_ (0x0020)
986
987#define PHY_VTSE_INT_MASK (0x19)
988#define PHY_VTSE_INT_MASK_MDINTPIN_EN_ (0x8000)
989#define PHY_VTSE_INT_MASK_SPEED_CHANGE_ (0x4000)
990#define PHY_VTSE_INT_MASK_LINK_CHANGE_ (0x2000)
991#define PHY_VTSE_INT_MASK_FDX_CHANGE_ (0x1000)
992#define PHY_VTSE_INT_MASK_AUTONEG_ERR_ (0x0800)
993#define PHY_VTSE_INT_MASK_AUTONEG_DONE_ (0x0400)
994#define PHY_VTSE_INT_MASK_POE_DETECT_ (0x0200)
995#define PHY_VTSE_INT_MASK_SYMBOL_ERR_ (0x0100)
996#define PHY_VTSE_INT_MASK_FAST_LINK_FAIL_ (0x0080)
997#define PHY_VTSE_INT_MASK_WOL_EVENT_ (0x0040)
998#define PHY_VTSE_INT_MASK_EXTENDED_INT_ (0x0020)
999#define PHY_VTSE_INT_MASK_RESERVED_ (0x0010)
1000#define PHY_VTSE_INT_MASK_FALSE_CARRIER_ (0x0008)
1001#define PHY_VTSE_INT_MASK_LINK_SPEED_DS_ (0x0004)
1002#define PHY_VTSE_INT_MASK_MASTER_SLAVE_DONE_ (0x0002)
1003#define PHY_VTSE_INT_MASK_RX__ER_ (0x0001)
1004
1005#define PHY_VTSE_INT_STS (0x1A)
1006#define PHY_VTSE_INT_STS_INT_ACTIVE_ (0x8000)
1007#define PHY_VTSE_INT_STS_SPEED_CHANGE_ (0x4000)
1008#define PHY_VTSE_INT_STS_LINK_CHANGE_ (0x2000)
1009#define PHY_VTSE_INT_STS_FDX_CHANGE_ (0x1000)
1010#define PHY_VTSE_INT_STS_AUTONEG_ERR_ (0x0800)
1011#define PHY_VTSE_INT_STS_AUTONEG_DONE_ (0x0400)
1012#define PHY_VTSE_INT_STS_POE_DETECT_ (0x0200)
1013#define PHY_VTSE_INT_STS_SYMBOL_ERR_ (0x0100)
1014#define PHY_VTSE_INT_STS_FAST_LINK_FAIL_ (0x0080)
1015#define PHY_VTSE_INT_STS_WOL_EVENT_ (0x0040)
1016#define PHY_VTSE_INT_STS_EXTENDED_INT_ (0x0020)
1017#define PHY_VTSE_INT_STS_RESERVED_ (0x0010)
1018#define PHY_VTSE_INT_STS_FALSE_CARRIER_ (0x0008)
1019#define PHY_VTSE_INT_STS_LINK_SPEED_DS_ (0x0004)
1020#define PHY_VTSE_INT_STS_MASTER_SLAVE_DONE_ (0x0002)
1021#define PHY_VTSE_INT_STS_RX_ER_ (0x0001)
1022
1023/* VTSE PHY registers */
1024#define PHY_EXT_GPIO_PAGE (0x1F)
1025#define PHY_EXT_GPIO_PAGE_SPACE_0 (0x0000)
1026#define PHY_EXT_GPIO_PAGE_SPACE_1 (0x0001)
1027#define PHY_EXT_GPIO_PAGE_SPACE_2 (0x0002)
1028
1029/* Extended Register Page 1 space */
1030#define PHY_EXT_MODE_CTRL (0x13)
1031#define PHY_EXT_MODE_CTRL_MDIX_MASK_ (0x000C)
1032#define PHY_EXT_MODE_CTRL_AUTO_MDIX_ (0x0000)
1033#define PHY_EXT_MODE_CTRL_MDI_ (0x0008)
1034#define PHY_EXT_MODE_CTRL_MDI_X_ (0x000C)
1035
1036#define PHY_ANA_10BASE_T_HD 0x01
1037#define PHY_ANA_10BASE_T_FD 0x02
1038#define PHY_ANA_100BASE_TX_HD 0x04
1039#define PHY_ANA_100BASE_TX_FD 0x08
1040#define PHY_ANA_1000BASE_T_FD 0x10
1041#define PHY_ANA_ALL_SUPPORTED_MEDIA (PHY_ANA_10BASE_T_HD | \
1042 PHY_ANA_10BASE_T_FD | \
1043 PHY_ANA_100BASE_TX_HD | \
1044 PHY_ANA_100BASE_TX_FD | \
1045 PHY_ANA_1000BASE_T_FD)
1046/* PHY MMD registers */
1047#define PHY_MMD_DEV_3 3
1048
1049#define PHY_EEE_PCS_STATUS (0x1)
1050#define PHY_EEE_PCS_STATUS_TX_LPI_RCVD_ ((WORD)0x0800)
1051#define PHY_EEE_PCS_STATUS_RX_LPI_RCVD_ ((WORD)0x0400)
1052#define PHY_EEE_PCS_STATUS_TX_LPI_IND_ ((WORD)0x0200)
1053#define PHY_EEE_PCS_STATUS_RX_LPI_IND_ ((WORD)0x0100)
1054#define PHY_EEE_PCS_STATUS_PCS_RCV_LNK_STS_ ((WORD)0x0004)
1055
1056#define PHY_EEE_CAPABILITIES (0x14)
1057#define PHY_EEE_CAPABILITIES_1000BT_EEE_ ((WORD)0x0004)
1058#define PHY_EEE_CAPABILITIES_100BT_EEE_ ((WORD)0x0002)
1059
1060#define PHY_MMD_DEV_7 7
1061
1062#define PHY_EEE_ADVERTISEMENT (0x3C)
1063#define PHY_EEE_ADVERTISEMENT_1000BT_EEE_ ((WORD)0x0004)
1064#define PHY_EEE_ADVERTISEMENT_100BT_EEE_ ((WORD)0x0002)
1065
1066#define PHY_EEE_LP_ADVERTISEMENT (0x3D)
1067#define PHY_EEE_1000BT_EEE_CAPABLE_ ((WORD)0x0004)
1068#define PHY_EEE_100BT_EEE_CAPABLE_ ((WORD)0x0002)
1069#endif /* _LAN78XX_H */