tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * include/linux/irqchip/arm-gic.h
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __LINUX_IRQCHIP_ARM_GIC_H
11#define __LINUX_IRQCHIP_ARM_GIC_H
12
13#define GIC_CPU_CTRL 0x00
14#define GIC_CPU_PRIMASK 0x04
15#define GIC_CPU_BINPOINT 0x08
16#define GIC_CPU_INTACK 0x0c
17#define GIC_CPU_EOI 0x10
18#define GIC_CPU_RUNNINGPRI 0x14
19#define GIC_CPU_HIGHPRI 0x18
20#define GIC_CPU_ALIAS_BINPOINT 0x1c
21#define GIC_CPU_ACTIVEPRIO 0xd0
22#define GIC_CPU_IDENT 0xfc
23#define GIC_CPU_DEACTIVATE 0x1000
24
25#define GICC_ENABLE 0x1
26#define GICC_INT_PRI_THRESHOLD 0xf0
27
28#define GIC_CPU_CTRL_EOImodeNS (1 << 9)
29
30#define GICC_IAR_INT_ID_MASK 0x3ff
31#define GICC_INT_SPURIOUS 1023
32#define GICC_DIS_BYPASS_MASK 0x1e0
33
34#define GIC_DIST_CTRL 0x000
35#define GIC_DIST_CTR 0x004
36#define GIC_DIST_IGROUP 0x080
37#define GIC_DIST_ENABLE_SET 0x100
38#define GIC_DIST_ENABLE_CLEAR 0x180
39#define GIC_DIST_PENDING_SET 0x200
40#define GIC_DIST_PENDING_CLEAR 0x280
41#define GIC_DIST_ACTIVE_SET 0x300
42#define GIC_DIST_ACTIVE_CLEAR 0x380
43#define GIC_DIST_PRI 0x400
44#define GIC_DIST_TARGET 0x800
45#define GIC_DIST_CONFIG 0xc00
46#define GIC_DIST_SOFTINT 0xf00
47#define GIC_DIST_SGI_PENDING_CLEAR 0xf10
48#define GIC_DIST_SGI_PENDING_SET 0xf20
49
50#define GICD_ENABLE 0x1
51#define GICD_DISABLE 0x0
52#define GICD_INT_ACTLOW_LVLTRIG 0x0
53#define GICD_INT_EN_CLR_X32 0xffffffff
54#define GICD_INT_EN_SET_SGI 0x0000ffff
55#define GICD_INT_EN_CLR_PPI 0xffff0000
56#define GICD_INT_DEF_PRI 0xa0
57#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
58 (GICD_INT_DEF_PRI << 16) |\
59 (GICD_INT_DEF_PRI << 8) |\
60 GICD_INT_DEF_PRI)
61
62#define GICH_HCR 0x0
63#define GICH_VTR 0x4
64#define GICH_VMCR 0x8
65#define GICH_MISR 0x10
66#define GICH_EISR0 0x20
67#define GICH_EISR1 0x24
68#define GICH_ELRSR0 0x30
69#define GICH_ELRSR1 0x34
70#define GICH_APR 0xf0
71#define GICH_LR0 0x100
72
73#define GICH_HCR_EN (1 << 0)
74#define GICH_HCR_UIE (1 << 1)
75
76#define GICH_LR_VIRTUALID (0x3ff << 0)
77#define GICH_LR_PHYSID_CPUID_SHIFT (10)
78#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)
79#define GICH_LR_STATE (3 << 28)
80#define GICH_LR_PENDING_BIT (1 << 28)
81#define GICH_LR_ACTIVE_BIT (1 << 29)
82#define GICH_LR_EOI (1 << 19)
83#define GICH_LR_HW (1 << 31)
84
85#define GICH_VMCR_CTRL_SHIFT 0
86#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT)
87#define GICH_VMCR_PRIMASK_SHIFT 27
88#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT)
89#define GICH_VMCR_BINPOINT_SHIFT 21
90#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT)
91#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18
92#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
93
94#define GICH_MISR_EOI (1 << 0)
95#define GICH_MISR_U (1 << 1)
96
97#ifndef __ASSEMBLY__
98
99#include <linux/irqdomain.h>
100
101struct device_node;
102
103void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
104 u32 offset, struct device_node *);
105void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
106int gic_cpu_if_down(unsigned int gic_nr);
107
108static inline void gic_init(unsigned int nr, int start,
109 void __iomem *dist , void __iomem *cpu)
110{
111 gic_init_bases(nr, start, dist, cpu, 0, NULL);
112}
113
114int gicv2m_of_init(struct device_node *node, struct irq_domain *parent);
115
116void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
117int gic_get_cpu_id(unsigned int cpu);
118void gic_migrate_target(unsigned int new_cpu_id);
119unsigned long gic_get_sgir_physaddr(void);
120
121#endif /* __ASSEMBLY */
122#endif