Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 MLX5_SET(typ, p, fld[idx], v); \
85} while (0)
86
87#define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 << __mlx5_dw_bit_off(typ, fld))); \
93} while (0)
94
95#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97__mlx5_mask(typ, fld))
98
99#define MLX5_GET_PR(typ, p, fld) ({ \
100 u32 ___t = MLX5_GET(typ, p, fld); \
101 pr_debug(#fld " = 0x%x\n", ___t); \
102 ___t; \
103})
104
105#define __MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108} while (0)
109
110#define MLX5_SET64(typ, p, fld, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld, v); \
113} while (0)
114
115#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 __MLX5_SET64(typ, p, fld[idx], v); \
118} while (0)
119
120#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET64_PR(typ, p, fld) ({ \
123 u64 ___t = MLX5_GET64(typ, p, fld); \
124 pr_debug(#fld " = 0x%llx\n", ___t); \
125 ___t; \
126})
127
128#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130__mlx5_mask16(typ, fld))
131
132#define MLX5_SET16(typ, p, fld, v) do { \
133 u16 _v = v; \
134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 << __mlx5_16_bit_off(typ, fld))); \
139} while (0)
140
141/* Big endian getters */
142#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 __mlx5_64_off(typ, fld)))
144
145#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
146 type_t tmp; \
147 switch (sizeof(tmp)) { \
148 case sizeof(u8): \
149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
150 break; \
151 case sizeof(u16): \
152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 break; \
154 case sizeof(u32): \
155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 break; \
157 case sizeof(u64): \
158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 break; \
160 } \
161 tmp; \
162 })
163
164enum mlx5_inline_modes {
165 MLX5_INLINE_MODE_NONE,
166 MLX5_INLINE_MODE_L2,
167 MLX5_INLINE_MODE_IP,
168 MLX5_INLINE_MODE_TCP_UDP,
169};
170
171enum {
172 MLX5_MAX_COMMANDS = 32,
173 MLX5_CMD_DATA_BLOCK_SIZE = 512,
174 MLX5_PCI_CMD_XPORT = 7,
175 MLX5_MKEY_BSF_OCTO_SIZE = 4,
176 MLX5_MAX_PSVS = 4,
177};
178
179enum {
180 MLX5_EXTENDED_UD_AV = 0x80000000,
181};
182
183enum {
184 MLX5_CQ_STATE_ARMED = 9,
185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
186 MLX5_CQ_STATE_FIRED = 0xa,
187};
188
189enum {
190 MLX5_STAT_RATE_OFFSET = 5,
191};
192
193enum {
194 MLX5_INLINE_SEG = 0x80000000,
195};
196
197enum {
198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199};
200
201enum {
202 MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 MLX5_MAX_LOG_PKEY_TABLE = 5,
204};
205
206enum {
207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208};
209
210enum {
211 MLX5_PFAULT_SUBTYPE_WQE = 0,
212 MLX5_PFAULT_SUBTYPE_RDMA = 1,
213};
214
215enum {
216 MLX5_PERM_LOCAL_READ = 1 << 2,
217 MLX5_PERM_LOCAL_WRITE = 1 << 3,
218 MLX5_PERM_REMOTE_READ = 1 << 4,
219 MLX5_PERM_REMOTE_WRITE = 1 << 5,
220 MLX5_PERM_ATOMIC = 1 << 6,
221 MLX5_PERM_UMR_EN = 1 << 7,
222};
223
224enum {
225 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
226 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
227 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
228 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
229 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
230};
231
232enum {
233 MLX5_EN_RD = (u64)1,
234 MLX5_EN_WR = (u64)2
235};
236
237enum {
238 MLX5_ADAPTER_PAGE_SHIFT = 12,
239 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
240};
241
242enum {
243 MLX5_BFREGS_PER_UAR = 4,
244 MLX5_MAX_UARS = 1 << 8,
245 MLX5_NON_FP_BFREGS_PER_UAR = 2,
246 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
247 MLX5_NON_FP_BFREGS_PER_UAR,
248 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
249 MLX5_NON_FP_BFREGS_PER_UAR,
250 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
251 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
252 MLX5_MIN_DYN_BFREGS = 512,
253 MLX5_MAX_DYN_BFREGS = 1024,
254};
255
256enum {
257 MLX5_MKEY_MASK_LEN = 1ull << 0,
258 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
259 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
260 MLX5_MKEY_MASK_PD = 1ull << 7,
261 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
262 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
263 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
264 MLX5_MKEY_MASK_KEY = 1ull << 13,
265 MLX5_MKEY_MASK_QPN = 1ull << 14,
266 MLX5_MKEY_MASK_LR = 1ull << 17,
267 MLX5_MKEY_MASK_LW = 1ull << 18,
268 MLX5_MKEY_MASK_RR = 1ull << 19,
269 MLX5_MKEY_MASK_RW = 1ull << 20,
270 MLX5_MKEY_MASK_A = 1ull << 21,
271 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
272 MLX5_MKEY_MASK_FREE = 1ull << 29,
273};
274
275enum {
276 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
277
278 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
279 MLX5_UMR_CHECK_FREE = (2 << 5),
280
281 MLX5_UMR_INLINE = (1 << 7),
282};
283
284#define MLX5_UMR_MTT_ALIGNMENT 0x40
285#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
286#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
287
288#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
289
290enum {
291 MLX5_EVENT_QUEUE_TYPE_QP = 0,
292 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
293 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
294 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
295};
296
297enum mlx5_event {
298 MLX5_EVENT_TYPE_COMP = 0x0,
299
300 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
301 MLX5_EVENT_TYPE_COMM_EST = 0x02,
302 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
303 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
304 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
305
306 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
307 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
308 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
309 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
310 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
311 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
312
313 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
314 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
315 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
316 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
317 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
318 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
319 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
320 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
321
322 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
323 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
324
325 MLX5_EVENT_TYPE_CMD = 0x0a,
326 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
327
328 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
329 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
330
331 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
332
333 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
334 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
335
336 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
337};
338
339enum {
340 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
341 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
342};
343
344enum {
345 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
346};
347
348enum {
349 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
350 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
351 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
352 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
353 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
354 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
355 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
356};
357
358enum {
359 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
360 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
361 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
362 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
363 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
364 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
365 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
366 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
367 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
368 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
369 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
370 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
371};
372
373enum {
374 MLX5_ROCE_VERSION_1 = 0,
375 MLX5_ROCE_VERSION_2 = 2,
376};
377
378enum {
379 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
380 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
381};
382
383enum {
384 MLX5_ROCE_L3_TYPE_IPV4 = 0,
385 MLX5_ROCE_L3_TYPE_IPV6 = 1,
386};
387
388enum {
389 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
390 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
391};
392
393enum {
394 MLX5_OPCODE_NOP = 0x00,
395 MLX5_OPCODE_SEND_INVAL = 0x01,
396 MLX5_OPCODE_RDMA_WRITE = 0x08,
397 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
398 MLX5_OPCODE_SEND = 0x0a,
399 MLX5_OPCODE_SEND_IMM = 0x0b,
400 MLX5_OPCODE_LSO = 0x0e,
401 MLX5_OPCODE_RDMA_READ = 0x10,
402 MLX5_OPCODE_ATOMIC_CS = 0x11,
403 MLX5_OPCODE_ATOMIC_FA = 0x12,
404 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
405 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
406 MLX5_OPCODE_BIND_MW = 0x18,
407 MLX5_OPCODE_CONFIG_CMD = 0x1f,
408
409 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
410 MLX5_RECV_OPCODE_SEND = 0x01,
411 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
412 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
413
414 MLX5_CQE_OPCODE_ERROR = 0x1e,
415 MLX5_CQE_OPCODE_RESIZE = 0x16,
416
417 MLX5_OPCODE_SET_PSV = 0x20,
418 MLX5_OPCODE_GET_PSV = 0x21,
419 MLX5_OPCODE_CHECK_PSV = 0x22,
420 MLX5_OPCODE_RGET_PSV = 0x26,
421 MLX5_OPCODE_RCHECK_PSV = 0x27,
422
423 MLX5_OPCODE_UMR = 0x25,
424
425};
426
427enum {
428 MLX5_SET_PORT_RESET_QKEY = 0,
429 MLX5_SET_PORT_GUID0 = 16,
430 MLX5_SET_PORT_NODE_GUID = 17,
431 MLX5_SET_PORT_SYS_GUID = 18,
432 MLX5_SET_PORT_GID_TABLE = 19,
433 MLX5_SET_PORT_PKEY_TABLE = 20,
434};
435
436enum {
437 MLX5_BW_NO_LIMIT = 0,
438 MLX5_100_MBPS_UNIT = 3,
439 MLX5_GBPS_UNIT = 4,
440};
441
442enum {
443 MLX5_MAX_PAGE_SHIFT = 31
444};
445
446enum {
447 MLX5_CAP_OFF_CMDIF_CSUM = 46,
448};
449
450enum {
451 /*
452 * Max wqe size for rdma read is 512 bytes, so this
453 * limits our max_sge_rd as the wqe needs to fit:
454 * - ctrl segment (16 bytes)
455 * - rdma segment (16 bytes)
456 * - scatter elements (16 bytes each)
457 */
458 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
459};
460
461enum mlx5_odp_transport_cap_bits {
462 MLX5_ODP_SUPPORT_SEND = 1 << 31,
463 MLX5_ODP_SUPPORT_RECV = 1 << 30,
464 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
465 MLX5_ODP_SUPPORT_READ = 1 << 28,
466};
467
468struct mlx5_odp_caps {
469 char reserved[0x10];
470 struct {
471 __be32 rc_odp_caps;
472 __be32 uc_odp_caps;
473 __be32 ud_odp_caps;
474 } per_transport_caps;
475 char reserved2[0xe4];
476};
477
478struct mlx5_cmd_layout {
479 u8 type;
480 u8 rsvd0[3];
481 __be32 inlen;
482 __be64 in_ptr;
483 __be32 in[4];
484 __be32 out[4];
485 __be64 out_ptr;
486 __be32 outlen;
487 u8 token;
488 u8 sig;
489 u8 rsvd1;
490 u8 status_own;
491};
492
493struct health_buffer {
494 __be32 assert_var[5];
495 __be32 rsvd0[3];
496 __be32 assert_exit_ptr;
497 __be32 assert_callra;
498 __be32 rsvd1[2];
499 __be32 fw_ver;
500 __be32 hw_id;
501 __be32 rsvd2;
502 u8 irisc_index;
503 u8 synd;
504 __be16 ext_synd;
505};
506
507enum mlx5_cmd_addr_l_sz_offset {
508 MLX5_NIC_IFC_OFFSET = 8,
509};
510
511struct mlx5_init_seg {
512 __be32 fw_rev;
513 __be32 cmdif_rev_fw_sub;
514 __be32 rsvd0[2];
515 __be32 cmdq_addr_h;
516 __be32 cmdq_addr_l_sz;
517 __be32 cmd_dbell;
518 __be32 rsvd1[120];
519 __be32 initializing;
520 struct health_buffer health;
521 __be32 rsvd2[880];
522 __be32 internal_timer_h;
523 __be32 internal_timer_l;
524 __be32 rsvd3[2];
525 __be32 health_counter;
526 __be32 rsvd4[1019];
527 __be64 ieee1588_clk;
528 __be32 ieee1588_clk_type;
529 __be32 clr_intx;
530};
531
532struct mlx5_eqe_comp {
533 __be32 reserved[6];
534 __be32 cqn;
535};
536
537struct mlx5_eqe_qp_srq {
538 __be32 reserved1[5];
539 u8 type;
540 u8 reserved2[3];
541 __be32 qp_srq_n;
542};
543
544struct mlx5_eqe_cq_err {
545 __be32 cqn;
546 u8 reserved1[7];
547 u8 syndrome;
548};
549
550struct mlx5_eqe_port_state {
551 u8 reserved0[8];
552 u8 port;
553};
554
555struct mlx5_eqe_gpio {
556 __be32 reserved0[2];
557 __be64 gpio_event;
558};
559
560struct mlx5_eqe_congestion {
561 u8 type;
562 u8 rsvd0;
563 u8 congestion_level;
564};
565
566struct mlx5_eqe_stall_vl {
567 u8 rsvd0[3];
568 u8 port_vl;
569};
570
571struct mlx5_eqe_cmd {
572 __be32 vector;
573 __be32 rsvd[6];
574};
575
576struct mlx5_eqe_page_req {
577 u8 rsvd0[2];
578 __be16 func_id;
579 __be32 num_pages;
580 __be32 rsvd1[5];
581};
582
583struct mlx5_eqe_page_fault {
584 __be32 bytes_committed;
585 union {
586 struct {
587 u16 reserved1;
588 __be16 wqe_index;
589 u16 reserved2;
590 __be16 packet_length;
591 __be32 token;
592 u8 reserved4[8];
593 __be32 pftype_wq;
594 } __packed wqe;
595 struct {
596 __be32 r_key;
597 u16 reserved1;
598 __be16 packet_length;
599 __be32 rdma_op_len;
600 __be64 rdma_va;
601 __be32 pftype_token;
602 } __packed rdma;
603 } __packed;
604} __packed;
605
606struct mlx5_eqe_vport_change {
607 u8 rsvd0[2];
608 __be16 vport_num;
609 __be32 rsvd1[6];
610} __packed;
611
612struct mlx5_eqe_port_module {
613 u8 reserved_at_0[1];
614 u8 module;
615 u8 reserved_at_2[1];
616 u8 module_status;
617 u8 reserved_at_4[2];
618 u8 error_type;
619} __packed;
620
621struct mlx5_eqe_pps {
622 u8 rsvd0[3];
623 u8 pin;
624 u8 rsvd1[4];
625 union {
626 struct {
627 __be32 time_sec;
628 __be32 time_nsec;
629 };
630 struct {
631 __be64 time_stamp;
632 };
633 };
634 u8 rsvd2[12];
635} __packed;
636
637struct mlx5_eqe_dct {
638 __be32 reserved[6];
639 __be32 dctn;
640};
641
642struct mlx5_eqe_temp_warning {
643 __be64 sensor_warning_msb;
644 __be64 sensor_warning_lsb;
645} __packed;
646
647union ev_data {
648 __be32 raw[7];
649 struct mlx5_eqe_cmd cmd;
650 struct mlx5_eqe_comp comp;
651 struct mlx5_eqe_qp_srq qp_srq;
652 struct mlx5_eqe_cq_err cq_err;
653 struct mlx5_eqe_port_state port;
654 struct mlx5_eqe_gpio gpio;
655 struct mlx5_eqe_congestion cong;
656 struct mlx5_eqe_stall_vl stall_vl;
657 struct mlx5_eqe_page_req req_pages;
658 struct mlx5_eqe_page_fault page_fault;
659 struct mlx5_eqe_vport_change vport_change;
660 struct mlx5_eqe_port_module port_module;
661 struct mlx5_eqe_pps pps;
662 struct mlx5_eqe_dct dct;
663 struct mlx5_eqe_temp_warning temp_warning;
664} __packed;
665
666struct mlx5_eqe {
667 u8 rsvd0;
668 u8 type;
669 u8 rsvd1;
670 u8 sub_type;
671 __be32 rsvd2[7];
672 union ev_data data;
673 __be16 rsvd3;
674 u8 signature;
675 u8 owner;
676} __packed;
677
678struct mlx5_cmd_prot_block {
679 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
680 u8 rsvd0[48];
681 __be64 next;
682 __be32 block_num;
683 u8 rsvd1;
684 u8 token;
685 u8 ctrl_sig;
686 u8 sig;
687};
688
689enum {
690 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
691};
692
693struct mlx5_err_cqe {
694 u8 rsvd0[32];
695 __be32 srqn;
696 u8 rsvd1[18];
697 u8 vendor_err_synd;
698 u8 syndrome;
699 __be32 s_wqe_opcode_qpn;
700 __be16 wqe_counter;
701 u8 signature;
702 u8 op_own;
703};
704
705struct mlx5_cqe64 {
706 u8 outer_l3_tunneled;
707 u8 rsvd0;
708 __be16 wqe_id;
709 u8 lro_tcppsh_abort_dupack;
710 u8 lro_min_ttl;
711 __be16 lro_tcp_win;
712 __be32 lro_ack_seq_num;
713 __be32 rss_hash_result;
714 u8 rss_hash_type;
715 u8 ml_path;
716 u8 rsvd20[2];
717 __be16 check_sum;
718 __be16 slid;
719 __be32 flags_rqpn;
720 u8 hds_ip_ext;
721 u8 l4_l3_hdr_type;
722 __be16 vlan_info;
723 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
724 __be32 imm_inval_pkey;
725 u8 rsvd40[4];
726 __be32 byte_cnt;
727 __be32 timestamp_h;
728 __be32 timestamp_l;
729 __be32 sop_drop_qpn;
730 __be16 wqe_counter;
731 u8 signature;
732 u8 op_own;
733};
734
735struct mlx5_mini_cqe8 {
736 union {
737 __be32 rx_hash_result;
738 struct {
739 __be16 checksum;
740 __be16 rsvd;
741 };
742 struct {
743 __be16 wqe_counter;
744 u8 s_wqe_opcode;
745 u8 reserved;
746 } s_wqe_info;
747 };
748 __be32 byte_cnt;
749};
750
751enum {
752 MLX5_NO_INLINE_DATA,
753 MLX5_INLINE_DATA32_SEG,
754 MLX5_INLINE_DATA64_SEG,
755 MLX5_COMPRESSED,
756};
757
758enum {
759 MLX5_CQE_FORMAT_CSUM = 0x1,
760};
761
762#define MLX5_MINI_CQE_ARRAY_SIZE 8
763
764static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
765{
766 return (cqe->op_own >> 2) & 0x3;
767}
768
769static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
770{
771 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
772}
773
774static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
775{
776 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
777}
778
779static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
780{
781 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
782}
783
784static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
785{
786 return cqe->outer_l3_tunneled & 0x1;
787}
788
789static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
790{
791 return cqe->l4_l3_hdr_type & 0x1;
792}
793
794static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
795{
796 u32 hi, lo;
797
798 hi = be32_to_cpu(cqe->timestamp_h);
799 lo = be32_to_cpu(cqe->timestamp_l);
800
801 return (u64)lo | ((u64)hi << 32);
802}
803
804#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
805#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
806
807struct mpwrq_cqe_bc {
808 __be16 filler_consumed_strides;
809 __be16 byte_cnt;
810};
811
812static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
813{
814 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
815
816 return be16_to_cpu(bc->byte_cnt);
817}
818
819static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
820{
821 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
822}
823
824static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
825{
826 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
827
828 return mpwrq_get_cqe_bc_consumed_strides(bc);
829}
830
831static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
832{
833 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
834
835 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
836}
837
838static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
839{
840 return be16_to_cpu(cqe->wqe_counter);
841}
842
843enum {
844 CQE_L4_HDR_TYPE_NONE = 0x0,
845 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
846 CQE_L4_HDR_TYPE_UDP = 0x2,
847 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
848 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
849};
850
851enum {
852 CQE_RSS_HTYPE_IP = 0x3 << 2,
853 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
854 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
855 */
856 CQE_RSS_HTYPE_L4 = 0x3 << 6,
857 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
858 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
859 */
860};
861
862enum {
863 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
864 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
865 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
866};
867
868enum {
869 CQE_L2_OK = 1 << 0,
870 CQE_L3_OK = 1 << 1,
871 CQE_L4_OK = 1 << 2,
872};
873
874struct mlx5_sig_err_cqe {
875 u8 rsvd0[16];
876 __be32 expected_trans_sig;
877 __be32 actual_trans_sig;
878 __be32 expected_reftag;
879 __be32 actual_reftag;
880 __be16 syndrome;
881 u8 rsvd22[2];
882 __be32 mkey;
883 __be64 err_offset;
884 u8 rsvd30[8];
885 __be32 qpn;
886 u8 rsvd38[2];
887 u8 signature;
888 u8 op_own;
889};
890
891struct mlx5_wqe_srq_next_seg {
892 u8 rsvd0[2];
893 __be16 next_wqe_index;
894 u8 signature;
895 u8 rsvd1[11];
896};
897
898union mlx5_ext_cqe {
899 struct ib_grh grh;
900 u8 inl[64];
901};
902
903struct mlx5_cqe128 {
904 union mlx5_ext_cqe inl_grh;
905 struct mlx5_cqe64 cqe64;
906};
907
908enum {
909 MLX5_MKEY_STATUS_FREE = 1 << 6,
910};
911
912enum {
913 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
914 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
915 MLX5_MKEY_BSF_EN = 1 << 30,
916 MLX5_MKEY_LEN64 = 1 << 31,
917};
918
919struct mlx5_mkey_seg {
920 /* This is a two bit field occupying bits 31-30.
921 * bit 31 is always 0,
922 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
923 */
924 u8 status;
925 u8 pcie_control;
926 u8 flags;
927 u8 version;
928 __be32 qpn_mkey7_0;
929 u8 rsvd1[4];
930 __be32 flags_pd;
931 __be64 start_addr;
932 __be64 len;
933 __be32 bsfs_octo_size;
934 u8 rsvd2[16];
935 __be32 xlt_oct_size;
936 u8 rsvd3[3];
937 u8 log2_page_size;
938 u8 rsvd4[4];
939};
940
941#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
942
943enum {
944 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
945};
946
947enum {
948 VPORT_STATE_DOWN = 0x0,
949 VPORT_STATE_UP = 0x1,
950};
951
952enum {
953 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
954 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
955 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
956};
957
958enum {
959 MLX5_L3_PROT_TYPE_IPV4 = 0,
960 MLX5_L3_PROT_TYPE_IPV6 = 1,
961};
962
963enum {
964 MLX5_L4_PROT_TYPE_TCP = 0,
965 MLX5_L4_PROT_TYPE_UDP = 1,
966};
967
968enum {
969 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
970 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
971 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
972 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
973 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
974};
975
976enum {
977 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
978 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
979 MLX5_MATCH_INNER_HEADERS = 1 << 2,
980
981};
982
983enum {
984 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
985 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
986};
987
988enum {
989 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
990 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
991 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
992};
993
994enum mlx5_list_type {
995 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
996 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
997 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
998};
999
1000enum {
1001 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1002 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1003};
1004
1005enum mlx5_wol_mode {
1006 MLX5_WOL_DISABLE = 0,
1007 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1008 MLX5_WOL_MAGIC = 1 << 2,
1009 MLX5_WOL_ARP = 1 << 3,
1010 MLX5_WOL_BROADCAST = 1 << 4,
1011 MLX5_WOL_MULTICAST = 1 << 5,
1012 MLX5_WOL_UNICAST = 1 << 6,
1013 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1014};
1015
1016enum mlx5_mpls_supported_fields {
1017 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1018 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1019 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1020 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1021};
1022
1023enum mlx5_flex_parser_protos {
1024 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1025 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1026};
1027
1028/* MLX5 DEV CAPs */
1029
1030/* TODO: EAT.ME */
1031enum mlx5_cap_mode {
1032 HCA_CAP_OPMOD_GET_MAX = 0,
1033 HCA_CAP_OPMOD_GET_CUR = 1,
1034};
1035
1036enum mlx5_cap_type {
1037 MLX5_CAP_GENERAL = 0,
1038 MLX5_CAP_ETHERNET_OFFLOADS,
1039 MLX5_CAP_ODP,
1040 MLX5_CAP_ATOMIC,
1041 MLX5_CAP_ROCE,
1042 MLX5_CAP_IPOIB_OFFLOADS,
1043 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1044 MLX5_CAP_FLOW_TABLE,
1045 MLX5_CAP_ESWITCH_FLOW_TABLE,
1046 MLX5_CAP_ESWITCH,
1047 MLX5_CAP_RESERVED,
1048 MLX5_CAP_VECTOR_CALC,
1049 MLX5_CAP_QOS,
1050 MLX5_CAP_DEBUG,
1051 MLX5_CAP_RESERVED_14,
1052 MLX5_CAP_DEV_MEM,
1053 /* NUM OF CAP Types */
1054 MLX5_CAP_NUM
1055};
1056
1057enum mlx5_pcam_reg_groups {
1058 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1059};
1060
1061enum mlx5_pcam_feature_groups {
1062 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1063};
1064
1065enum mlx5_mcam_reg_groups {
1066 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1067};
1068
1069enum mlx5_mcam_feature_groups {
1070 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1071};
1072
1073enum mlx5_qcam_reg_groups {
1074 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1075};
1076
1077enum mlx5_qcam_feature_groups {
1078 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1079};
1080
1081/* GET Dev Caps macros */
1082#define MLX5_CAP_GEN(mdev, cap) \
1083 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1084
1085#define MLX5_CAP_GEN_64(mdev, cap) \
1086 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1087
1088#define MLX5_CAP_GEN_MAX(mdev, cap) \
1089 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1090
1091#define MLX5_CAP_ETH(mdev, cap) \
1092 MLX5_GET(per_protocol_networking_offload_caps,\
1093 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1094
1095#define MLX5_CAP_ETH_MAX(mdev, cap) \
1096 MLX5_GET(per_protocol_networking_offload_caps,\
1097 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1098
1099#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1100 MLX5_GET(per_protocol_networking_offload_caps,\
1101 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1102
1103#define MLX5_CAP_ROCE(mdev, cap) \
1104 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1105
1106#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1107 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1108
1109#define MLX5_CAP_ATOMIC(mdev, cap) \
1110 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1111
1112#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1113 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1114
1115#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1116 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1117
1118#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1119 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1120
1121#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1122 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1123
1124#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1125 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1126
1127#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1128 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1129
1130#define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1131 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1132
1133#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1134 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1135
1136#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1137 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1138
1139#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1140 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1141
1142#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1143 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1144
1145#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1146 MLX5_GET(flow_table_eswitch_cap, \
1147 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1148
1149#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1150 MLX5_GET(flow_table_eswitch_cap, \
1151 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1152
1153#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1154 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1155
1156#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1157 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1158
1159#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1160 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1161
1162#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1163 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1164
1165#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1166 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1167
1168#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1169 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1170
1171#define MLX5_CAP_ESW(mdev, cap) \
1172 MLX5_GET(e_switch_cap, \
1173 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1174
1175#define MLX5_CAP_ESW_MAX(mdev, cap) \
1176 MLX5_GET(e_switch_cap, \
1177 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1178
1179#define MLX5_CAP_ODP(mdev, cap)\
1180 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1181
1182#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1183 MLX5_GET(vector_calc_cap, \
1184 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1185
1186#define MLX5_CAP_QOS(mdev, cap)\
1187 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1188
1189#define MLX5_CAP_DEBUG(mdev, cap)\
1190 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1191
1192#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1193 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1194
1195#define MLX5_CAP_PCAM_REG(mdev, reg) \
1196 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1197
1198#define MLX5_CAP_MCAM_REG(mdev, reg) \
1199 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1200
1201#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1202 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1203
1204#define MLX5_CAP_QCAM_REG(mdev, fld) \
1205 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1206
1207#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1208 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1209
1210#define MLX5_CAP_FPGA(mdev, cap) \
1211 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1212
1213#define MLX5_CAP64_FPGA(mdev, cap) \
1214 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1215
1216#define MLX5_CAP_DEV_MEM(mdev, cap)\
1217 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1218
1219#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1220 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1221
1222enum {
1223 MLX5_CMD_STAT_OK = 0x0,
1224 MLX5_CMD_STAT_INT_ERR = 0x1,
1225 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1226 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1227 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1228 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1229 MLX5_CMD_STAT_RES_BUSY = 0x6,
1230 MLX5_CMD_STAT_LIM_ERR = 0x8,
1231 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1232 MLX5_CMD_STAT_IX_ERR = 0xa,
1233 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1234 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1235 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1236 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1237 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1238 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1239};
1240
1241enum {
1242 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1243 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1244 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1245 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1246 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1247 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1248 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1249 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1250 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1251 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1252};
1253
1254enum {
1255 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1256};
1257
1258static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1259{
1260 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1261 return 0;
1262 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1263}
1264
1265#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1266#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1267#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1268#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1269 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1270 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1271
1272#endif /* MLX5_DEVICE_H */