tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

kernel / drivers / phy / qualcomm / phy-qcom-qmp.c
at v4.20 1837 lines 61 kB view raw
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/clk-provider.h> 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/io.h> 11#include <linux/iopoll.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_device.h> 16#include <linux/of_address.h> 17#include <linux/phy/phy.h> 18#include <linux/platform_device.h> 19#include <linux/regulator/consumer.h> 20#include <linux/reset.h> 21#include <linux/slab.h> 22 23#include <dt-bindings/phy/phy.h> 24 25#include "phy-qcom-qmp.h" 26 27/* QPHY_SW_RESET bit */ 28#define SW_RESET BIT(0) 29/* QPHY_POWER_DOWN_CONTROL */ 30#define SW_PWRDN BIT(0) 31#define REFCLK_DRV_DSBL BIT(1) 32/* QPHY_START_CONTROL bits */ 33#define SERDES_START BIT(0) 34#define PCS_START BIT(1) 35#define PLL_READY_GATE_EN BIT(3) 36/* QPHY_PCS_STATUS bit */ 37#define PHYSTATUS BIT(6) 38/* QPHY_COM_PCS_READY_STATUS bit */ 39#define PCS_READY BIT(0) 40 41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 42/* DP PHY soft reset */ 43#define SW_DPPHY_RESET BIT(0) 44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 45#define SW_DPPHY_RESET_MUX BIT(1) 46/* USB3 PHY soft reset */ 47#define SW_USB3PHY_RESET BIT(2) 48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 49#define SW_USB3PHY_RESET_MUX BIT(3) 50 51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 52#define USB3_MODE BIT(0) /* enables USB3 mode */ 53#define DP_MODE BIT(1) /* enables DP mode */ 54 55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 56#define ARCVR_DTCT_EN BIT(0) 57#define ALFPS_DTCT_EN BIT(1) 58#define ARCVR_DTCT_EVENT_SEL BIT(4) 59 60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 61#define IRQ_CLEAR BIT(0) 62 63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 64#define RCVR_DETECT BIT(0) 65 66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 68 69#define PHY_INIT_COMPLETE_TIMEOUT 1000 70#define POWER_DOWN_DELAY_US_MIN 10 71#define POWER_DOWN_DELAY_US_MAX 11 72 73#define MAX_PROP_NAME 32 74 75struct qmp_phy_init_tbl { 76 unsigned int offset; 77 unsigned int val; 78 /* 79 * register part of layout ? 80 * if yes, then offset gives index in the reg-layout 81 */ 82 int in_layout; 83}; 84 85#define QMP_PHY_INIT_CFG(o, v) \ 86 { \ 87 .offset = o, \ 88 .val = v, \ 89 } 90 91#define QMP_PHY_INIT_CFG_L(o, v) \ 92 { \ 93 .offset = o, \ 94 .val = v, \ 95 .in_layout = 1, \ 96 } 97 98/* set of registers with offsets different per-PHY */ 99enum qphy_reg_layout { 100 /* Common block control registers */ 101 QPHY_COM_SW_RESET, 102 QPHY_COM_POWER_DOWN_CONTROL, 103 QPHY_COM_START_CONTROL, 104 QPHY_COM_PCS_READY_STATUS, 105 /* PCS registers */ 106 QPHY_PLL_LOCK_CHK_DLY_TIME, 107 QPHY_FLL_CNTRL1, 108 QPHY_FLL_CNTRL2, 109 QPHY_FLL_CNT_VAL_L, 110 QPHY_FLL_CNT_VAL_H_TOL, 111 QPHY_FLL_MAN_CODE, 112 QPHY_SW_RESET, 113 QPHY_START_CTRL, 114 QPHY_PCS_READY_STATUS, 115 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 116 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 117 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 118}; 119 120static const unsigned int pciephy_regs_layout[] = { 121 [QPHY_COM_SW_RESET] = 0x400, 122 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 123 [QPHY_COM_START_CONTROL] = 0x408, 124 [QPHY_COM_PCS_READY_STATUS] = 0x448, 125 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, 126 [QPHY_FLL_CNTRL1] = 0xc4, 127 [QPHY_FLL_CNTRL2] = 0xc8, 128 [QPHY_FLL_CNT_VAL_L] = 0xcc, 129 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, 130 [QPHY_FLL_MAN_CODE] = 0xd4, 131 [QPHY_SW_RESET] = 0x00, 132 [QPHY_START_CTRL] = 0x08, 133 [QPHY_PCS_READY_STATUS] = 0x174, 134}; 135 136static const unsigned int usb3phy_regs_layout[] = { 137 [QPHY_FLL_CNTRL1] = 0xc0, 138 [QPHY_FLL_CNTRL2] = 0xc4, 139 [QPHY_FLL_CNT_VAL_L] = 0xc8, 140 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, 141 [QPHY_FLL_MAN_CODE] = 0xd0, 142 [QPHY_SW_RESET] = 0x00, 143 [QPHY_START_CTRL] = 0x08, 144 [QPHY_PCS_READY_STATUS] = 0x17c, 145 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, 146 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, 147 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, 148}; 149 150static const unsigned int qmp_v3_usb3phy_regs_layout[] = { 151 [QPHY_SW_RESET] = 0x00, 152 [QPHY_START_CTRL] = 0x08, 153 [QPHY_PCS_READY_STATUS] = 0x174, 154 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 155 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 156 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 157}; 158 159static const unsigned int sdm845_ufsphy_regs_layout[] = { 160 [QPHY_START_CTRL] = 0x00, 161 [QPHY_PCS_READY_STATUS] = 0x160, 162}; 163 164static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { 165 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 166 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 167 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 168 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 169 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), 170 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 171 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 172 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 173 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), 174 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 175 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 176 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 177 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), 178 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 179 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 180 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 181 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 182 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 183 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), 184 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), 185 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 186 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 187 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 188 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), 189 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 190 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 191 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 192 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 193 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 194 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 195 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 196 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 197 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), 198 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 199 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 200 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 201 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), 202 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 203 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 204 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 205 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 206 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 207 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), 208}; 209 210static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { 211 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 212 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 213}; 214 215static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { 216 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 217 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), 218 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), 219 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 220 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), 221 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 222 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), 223 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 224 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 225 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), 226}; 227 228static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 229 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), 230 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), 231 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 232 233 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), 234 235 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), 236 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), 237 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), 238 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), 239 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), 240}; 241 242static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 243 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 244 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 245 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 246 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 247 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 248 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 250 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 251 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 252 /* PLL and Loop filter settings */ 253 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 254 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 255 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 256 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 257 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 258 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 259 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 260 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 261 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 262 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 263 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 264 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 265 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 266 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 267 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 268 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 269 /* SSC settings */ 270 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 271 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 272 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 273 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 274 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 276 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 277}; 278 279static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 280 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 281 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 282 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 283}; 284 285static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 286 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 287 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 288 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 289 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 290 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 291 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 292 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 293 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 294 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 295 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 296}; 297 298static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 299 /* FLL settings */ 300 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), 301 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), 302 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), 303 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), 304 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), 305 306 /* Lock Det settings */ 307 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), 308 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), 309 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), 310 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), 311}; 312 313static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 314 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 315 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 316 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 317 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 318 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 319 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f), 320 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 321 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 322 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 323 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 324 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 325 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 326 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 327 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 328 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 329 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 330 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 331 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 332 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 333 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 334 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 335 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 336 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 337 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 338 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 339 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 340 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 341 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 342 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 343 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 344 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 345 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 346 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa), 347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 349 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 351 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 352 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 353 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 354 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 355 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7), 356}; 357 358static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 359 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 360 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 361 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 362 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 363}; 364 365static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 366 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 367 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 368 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 369 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 370 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 371 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 372 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 373 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), 374}; 375 376static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 377 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), 378 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), 379 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 380 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 381 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 382 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 383 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 384 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), 385 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), 386 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), 387 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), 388 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 389 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 390}; 391 392static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 429}; 430 431static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 433 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 434 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 435 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 436 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 437}; 438 439static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 449}; 450 451static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 452 /* FLL settings */ 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 458 459 /* Lock Det settings */ 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 464 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 484 485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 496}; 497 498static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 535}; 536 537static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 538 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 539 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 540 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 541 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 542 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 543}; 544 545static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 546 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 547 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 548 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 549 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 550 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 551 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 552 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 553 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 554 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 556 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 557}; 558 559static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 560 /* FLL settings */ 561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 562 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 566 567 /* Lock Det settings */ 568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 572 573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 592 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 604 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 607}; 608 609static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { 610 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 611 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 612 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 613 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 614 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 615 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), 616 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 617 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 618 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 619 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 620 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 621 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 622 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), 623 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), 624 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), 625 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), 626 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 627 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 628 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 629 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 630 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 631 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 632 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), 633 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 634 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), 635 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), 636 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), 637 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), 638 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), 639 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), 640 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 641 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 642 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), 643 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 644 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 645 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 646 647 /* Rate B */ 648 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 649}; 650 651static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { 652 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 653 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), 654 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 655}; 656 657static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { 658 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 659 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 660 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 661 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 662 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 663 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 664 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 665 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 666 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 667 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 668 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 669 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 670 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 671 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 672 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 673 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 674}; 675 676static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { 677 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), 678 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), 679 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), 680 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), 681 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), 682 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), 683 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), 684 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), 685}; 686 687/* struct qmp_phy_cfg - per-PHY initialization config */ 688struct qmp_phy_cfg { 689 /* phy-type - PCIE/UFS/USB */ 690 unsigned int type; 691 /* number of lanes provided by phy */ 692 int nlanes; 693 694 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 695 const struct qmp_phy_init_tbl *serdes_tbl; 696 int serdes_tbl_num; 697 const struct qmp_phy_init_tbl *tx_tbl; 698 int tx_tbl_num; 699 const struct qmp_phy_init_tbl *rx_tbl; 700 int rx_tbl_num; 701 const struct qmp_phy_init_tbl *pcs_tbl; 702 int pcs_tbl_num; 703 704 /* clock ids to be requested */ 705 const char * const *clk_list; 706 int num_clks; 707 /* resets to be requested */ 708 const char * const *reset_list; 709 int num_resets; 710 /* regulators to be requested */ 711 const char * const *vreg_list; 712 int num_vregs; 713 714 /* array of registers with different offsets */ 715 const unsigned int *regs; 716 717 unsigned int start_ctrl; 718 unsigned int pwrdn_ctrl; 719 unsigned int mask_pcs_ready; 720 unsigned int mask_com_pcs_ready; 721 722 /* true, if PHY has a separate PHY_COM control block */ 723 bool has_phy_com_ctrl; 724 /* true, if PHY has a reset for individual lanes */ 725 bool has_lane_rst; 726 /* true, if PHY needs delay after POWER_DOWN */ 727 bool has_pwrdn_delay; 728 /* power_down delay in usec */ 729 int pwrdn_delay_min; 730 int pwrdn_delay_max; 731 732 /* true, if PHY has a separate DP_COM control block */ 733 bool has_phy_dp_com_ctrl; 734 /* true, if PHY has secondary tx/rx lanes to be configured */ 735 bool is_dual_lane_phy; 736 /* Register offset of secondary tx/rx lanes for USB DP combo PHY */ 737 unsigned int tx_b_lane_offset; 738 unsigned int rx_b_lane_offset; 739 740 /* true, if PCS block has no separate SW_RESET register */ 741 bool no_pcs_sw_reset; 742}; 743 744/** 745 * struct qmp_phy - per-lane phy descriptor 746 * 747 * @phy: generic phy 748 * @tx: iomapped memory space for lane's tx 749 * @rx: iomapped memory space for lane's rx 750 * @pcs: iomapped memory space for lane's pcs 751 * @pcs_misc: iomapped memory space for lane's pcs_misc 752 * @pipe_clk: pipe lock 753 * @index: lane index 754 * @qmp: QMP phy to which this lane belongs 755 * @lane_rst: lane's reset controller 756 */ 757struct qmp_phy { 758 struct phy *phy; 759 void __iomem *tx; 760 void __iomem *rx; 761 void __iomem *pcs; 762 void __iomem *pcs_misc; 763 struct clk *pipe_clk; 764 unsigned int index; 765 struct qcom_qmp *qmp; 766 struct reset_control *lane_rst; 767}; 768 769/** 770 * struct qcom_qmp - structure holding QMP phy block attributes 771 * 772 * @dev: device 773 * @serdes: iomapped memory space for phy's serdes 774 * @dp_com: iomapped memory space for phy's dp_com control block 775 * 776 * @clks: array of clocks required by phy 777 * @resets: array of resets required by phy 778 * @vregs: regulator supplies bulk data 779 * 780 * @cfg: phy specific configuration 781 * @phys: array of per-lane phy descriptors 782 * @phy_mutex: mutex lock for PHY common block initialization 783 * @init_count: phy common block initialization count 784 * @phy_initialized: indicate if PHY has been initialized 785 * @mode: current PHY mode 786 */ 787struct qcom_qmp { 788 struct device *dev; 789 void __iomem *serdes; 790 void __iomem *dp_com; 791 792 struct clk_bulk_data *clks; 793 struct reset_control **resets; 794 struct regulator_bulk_data *vregs; 795 796 const struct qmp_phy_cfg *cfg; 797 struct qmp_phy **phys; 798 799 struct mutex phy_mutex; 800 int init_count; 801 bool phy_initialized; 802 enum phy_mode mode; 803}; 804 805static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 806{ 807 u32 reg; 808 809 reg = readl(base + offset); 810 reg |= val; 811 writel(reg, base + offset); 812 813 /* ensure that above write is through */ 814 readl(base + offset); 815} 816 817static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 818{ 819 u32 reg; 820 821 reg = readl(base + offset); 822 reg &= ~val; 823 writel(reg, base + offset); 824 825 /* ensure that above write is through */ 826 readl(base + offset); 827} 828 829/* list of clocks required by phy */ 830static const char * const msm8996_phy_clk_l[] = { 831 "aux", "cfg_ahb", "ref", 832}; 833 834static const char * const qmp_v3_phy_clk_l[] = { 835 "aux", "cfg_ahb", "ref", "com_aux", 836}; 837 838static const char * const sdm845_ufs_phy_clk_l[] = { 839 "ref", "ref_aux", 840}; 841 842/* list of resets */ 843static const char * const msm8996_pciephy_reset_l[] = { 844 "phy", "common", "cfg", 845}; 846 847static const char * const msm8996_usb3phy_reset_l[] = { 848 "phy", "common", 849}; 850 851/* list of regulators */ 852static const char * const qmp_phy_vreg_l[] = { 853 "vdda-phy", "vdda-pll", 854}; 855 856static const struct qmp_phy_cfg msm8996_pciephy_cfg = { 857 .type = PHY_TYPE_PCIE, 858 .nlanes = 3, 859 860 .serdes_tbl = msm8996_pcie_serdes_tbl, 861 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), 862 .tx_tbl = msm8996_pcie_tx_tbl, 863 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), 864 .rx_tbl = msm8996_pcie_rx_tbl, 865 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), 866 .pcs_tbl = msm8996_pcie_pcs_tbl, 867 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), 868 .clk_list = msm8996_phy_clk_l, 869 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 870 .reset_list = msm8996_pciephy_reset_l, 871 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), 872 .vreg_list = qmp_phy_vreg_l, 873 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 874 .regs = pciephy_regs_layout, 875 876 .start_ctrl = PCS_START | PLL_READY_GATE_EN, 877 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 878 .mask_com_pcs_ready = PCS_READY, 879 880 .has_phy_com_ctrl = true, 881 .has_lane_rst = true, 882 .has_pwrdn_delay = true, 883 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 884 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 885}; 886 887static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 888 .type = PHY_TYPE_USB3, 889 .nlanes = 1, 890 891 .serdes_tbl = msm8996_usb3_serdes_tbl, 892 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 893 .tx_tbl = msm8996_usb3_tx_tbl, 894 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 895 .rx_tbl = msm8996_usb3_rx_tbl, 896 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 897 .pcs_tbl = msm8996_usb3_pcs_tbl, 898 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 899 .clk_list = msm8996_phy_clk_l, 900 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 901 .reset_list = msm8996_usb3phy_reset_l, 902 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 903 .vreg_list = qmp_phy_vreg_l, 904 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 905 .regs = usb3phy_regs_layout, 906 907 .start_ctrl = SERDES_START | PCS_START, 908 .pwrdn_ctrl = SW_PWRDN, 909 .mask_pcs_ready = PHYSTATUS, 910}; 911 912/* list of resets */ 913static const char * const ipq8074_pciephy_reset_l[] = { 914 "phy", "common", 915}; 916 917static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 918 .type = PHY_TYPE_PCIE, 919 .nlanes = 1, 920 921 .serdes_tbl = ipq8074_pcie_serdes_tbl, 922 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 923 .tx_tbl = ipq8074_pcie_tx_tbl, 924 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 925 .rx_tbl = ipq8074_pcie_rx_tbl, 926 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 927 .pcs_tbl = ipq8074_pcie_pcs_tbl, 928 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 929 .clk_list = NULL, 930 .num_clks = 0, 931 .reset_list = ipq8074_pciephy_reset_l, 932 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 933 .vreg_list = NULL, 934 .num_vregs = 0, 935 .regs = pciephy_regs_layout, 936 937 .start_ctrl = SERDES_START | PCS_START, 938 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 939 .mask_pcs_ready = PHYSTATUS, 940 941 .has_phy_com_ctrl = false, 942 .has_lane_rst = false, 943 .has_pwrdn_delay = true, 944 .pwrdn_delay_min = 995, /* us */ 945 .pwrdn_delay_max = 1005, /* us */ 946}; 947 948static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 949 .type = PHY_TYPE_USB3, 950 .nlanes = 1, 951 952 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 953 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 954 .tx_tbl = qmp_v3_usb3_tx_tbl, 955 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 956 .rx_tbl = qmp_v3_usb3_rx_tbl, 957 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 958 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 959 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 960 .clk_list = qmp_v3_phy_clk_l, 961 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 962 .reset_list = msm8996_usb3phy_reset_l, 963 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 964 .vreg_list = qmp_phy_vreg_l, 965 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 966 .regs = qmp_v3_usb3phy_regs_layout, 967 968 .start_ctrl = SERDES_START | PCS_START, 969 .pwrdn_ctrl = SW_PWRDN, 970 .mask_pcs_ready = PHYSTATUS, 971 972 .has_pwrdn_delay = true, 973 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 974 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 975 976 .has_phy_dp_com_ctrl = true, 977 .is_dual_lane_phy = true, 978 .tx_b_lane_offset = 0x400, 979 .rx_b_lane_offset = 0x400, 980}; 981 982static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 983 .type = PHY_TYPE_USB3, 984 .nlanes = 1, 985 986 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 987 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 988 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 989 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 990 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 991 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 992 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 993 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 994 .clk_list = qmp_v3_phy_clk_l, 995 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 996 .reset_list = msm8996_usb3phy_reset_l, 997 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 998 .vreg_list = qmp_phy_vreg_l, 999 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1000 .regs = qmp_v3_usb3phy_regs_layout, 1001 1002 .start_ctrl = SERDES_START | PCS_START, 1003 .pwrdn_ctrl = SW_PWRDN, 1004 .mask_pcs_ready = PHYSTATUS, 1005 1006 .has_pwrdn_delay = true, 1007 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1008 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1009}; 1010 1011static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 1012 .type = PHY_TYPE_UFS, 1013 .nlanes = 2, 1014 1015 .serdes_tbl = sdm845_ufsphy_serdes_tbl, 1016 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), 1017 .tx_tbl = sdm845_ufsphy_tx_tbl, 1018 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), 1019 .rx_tbl = sdm845_ufsphy_rx_tbl, 1020 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), 1021 .pcs_tbl = sdm845_ufsphy_pcs_tbl, 1022 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), 1023 .clk_list = sdm845_ufs_phy_clk_l, 1024 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1025 .vreg_list = qmp_phy_vreg_l, 1026 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1027 .regs = sdm845_ufsphy_regs_layout, 1028 1029 .start_ctrl = SERDES_START, 1030 .pwrdn_ctrl = SW_PWRDN, 1031 .mask_pcs_ready = PCS_READY, 1032 1033 .is_dual_lane_phy = true, 1034 .tx_b_lane_offset = 0x400, 1035 .rx_b_lane_offset = 0x400, 1036 1037 .no_pcs_sw_reset = true, 1038}; 1039 1040static void qcom_qmp_phy_configure(void __iomem *base, 1041 const unsigned int *regs, 1042 const struct qmp_phy_init_tbl tbl[], 1043 int num) 1044{ 1045 int i; 1046 const struct qmp_phy_init_tbl *t = tbl; 1047 1048 if (!t) 1049 return; 1050 1051 for (i = 0; i < num; i++, t++) { 1052 if (t->in_layout) 1053 writel(t->val, base + regs[t->offset]); 1054 else 1055 writel(t->val, base + t->offset); 1056 } 1057} 1058 1059static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) 1060{ 1061 struct qcom_qmp *qmp = qphy->qmp; 1062 const struct qmp_phy_cfg *cfg = qmp->cfg; 1063 void __iomem *serdes = qmp->serdes; 1064 void __iomem *pcs = qphy->pcs; 1065 void __iomem *dp_com = qmp->dp_com; 1066 int ret, i; 1067 1068 mutex_lock(&qmp->phy_mutex); 1069 if (qmp->init_count++) { 1070 mutex_unlock(&qmp->phy_mutex); 1071 return 0; 1072 } 1073 1074 /* turn on regulator supplies */ 1075 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1076 if (ret) { 1077 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1078 goto err_reg_enable; 1079 } 1080 1081 for (i = 0; i < cfg->num_resets; i++) { 1082 ret = reset_control_assert(qmp->resets[i]); 1083 if (ret) { 1084 dev_err(qmp->dev, "%s reset assert failed\n", 1085 cfg->reset_list[i]); 1086 goto err_rst_assert; 1087 } 1088 } 1089 1090 for (i = cfg->num_resets - 1; i >= 0; i--) { 1091 ret = reset_control_deassert(qmp->resets[i]); 1092 if (ret) { 1093 dev_err(qmp->dev, "%s reset deassert failed\n", 1094 qmp->cfg->reset_list[i]); 1095 goto err_rst; 1096 } 1097 } 1098 1099 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1100 if (ret) { 1101 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); 1102 goto err_rst; 1103 } 1104 1105 if (cfg->has_phy_dp_com_ctrl) { 1106 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 1107 SW_PWRDN); 1108 /* override hardware control for reset of qmp phy */ 1109 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1110 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1111 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1112 1113 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 1114 USB3_MODE | DP_MODE); 1115 1116 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 1117 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1118 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1119 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1120 } 1121 1122 if (cfg->has_phy_com_ctrl) 1123 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 1124 SW_PWRDN); 1125 else 1126 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 1127 1128 /* Serdes configuration */ 1129 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl, 1130 cfg->serdes_tbl_num); 1131 1132 if (cfg->has_phy_com_ctrl) { 1133 void __iomem *status; 1134 unsigned int mask, val; 1135 1136 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 1137 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1138 SERDES_START | PCS_START); 1139 1140 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 1141 mask = cfg->mask_com_pcs_ready; 1142 1143 ret = readl_poll_timeout(status, val, (val & mask), 10, 1144 PHY_INIT_COMPLETE_TIMEOUT); 1145 if (ret) { 1146 dev_err(qmp->dev, 1147 "phy common block init timed-out\n"); 1148 goto err_com_init; 1149 } 1150 } 1151 1152 mutex_unlock(&qmp->phy_mutex); 1153 1154 return 0; 1155 1156err_com_init: 1157 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1158err_rst: 1159 while (++i < cfg->num_resets) 1160 reset_control_assert(qmp->resets[i]); 1161err_rst_assert: 1162 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1163err_reg_enable: 1164 mutex_unlock(&qmp->phy_mutex); 1165 1166 return ret; 1167} 1168 1169static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) 1170{ 1171 const struct qmp_phy_cfg *cfg = qmp->cfg; 1172 void __iomem *serdes = qmp->serdes; 1173 int i = cfg->num_resets; 1174 1175 mutex_lock(&qmp->phy_mutex); 1176 if (--qmp->init_count) { 1177 mutex_unlock(&qmp->phy_mutex); 1178 return 0; 1179 } 1180 1181 if (cfg->has_phy_com_ctrl) { 1182 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1183 SERDES_START | PCS_START); 1184 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 1185 SW_RESET); 1186 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 1187 SW_PWRDN); 1188 } 1189 1190 while (--i >= 0) 1191 reset_control_assert(qmp->resets[i]); 1192 1193 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1194 1195 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1196 1197 mutex_unlock(&qmp->phy_mutex); 1198 1199 return 0; 1200} 1201 1202/* PHY Initialization */ 1203static int qcom_qmp_phy_init(struct phy *phy) 1204{ 1205 struct qmp_phy *qphy = phy_get_drvdata(phy); 1206 struct qcom_qmp *qmp = qphy->qmp; 1207 const struct qmp_phy_cfg *cfg = qmp->cfg; 1208 void __iomem *tx = qphy->tx; 1209 void __iomem *rx = qphy->rx; 1210 void __iomem *pcs = qphy->pcs; 1211 void __iomem *dp_com = qmp->dp_com; 1212 void __iomem *status; 1213 unsigned int mask, val; 1214 int ret; 1215 1216 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1217 1218 ret = qcom_qmp_phy_com_init(qphy); 1219 if (ret) 1220 return ret; 1221 1222 if (cfg->has_lane_rst) { 1223 ret = reset_control_deassert(qphy->lane_rst); 1224 if (ret) { 1225 dev_err(qmp->dev, "lane%d reset deassert failed\n", 1226 qphy->index); 1227 goto err_lane_rst; 1228 } 1229 } 1230 1231 ret = clk_prepare_enable(qphy->pipe_clk); 1232 if (ret) { 1233 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1234 goto err_clk_enable; 1235 } 1236 1237 /* Tx, Rx, and PCS configurations */ 1238 qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num); 1239 /* Configuration for other LANE for USB-DP combo PHY */ 1240 if (cfg->is_dual_lane_phy) 1241 qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs, 1242 cfg->tx_tbl, cfg->tx_tbl_num); 1243 1244 qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); 1245 if (cfg->is_dual_lane_phy) 1246 qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs, 1247 cfg->rx_tbl, cfg->rx_tbl_num); 1248 1249 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1250 1251 /* 1252 * UFS PHY requires the deassert of software reset before serdes start. 1253 * For UFS PHYs that do not have software reset control bits, defer 1254 * starting serdes until the power on callback. 1255 */ 1256 if ((cfg->type == PHY_TYPE_UFS) && cfg->no_pcs_sw_reset) 1257 goto out; 1258 1259 /* 1260 * Pull out PHY from POWER DOWN state. 1261 * This is active low enable signal to power-down PHY. 1262 */ 1263 if(cfg->type == PHY_TYPE_PCIE) 1264 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 1265 1266 if (cfg->has_pwrdn_delay) 1267 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1268 1269 /* Pull PHY out of reset state */ 1270 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1271 if (cfg->has_phy_dp_com_ctrl) 1272 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1273 1274 /* start SerDes and Phy-Coding-Sublayer */ 1275 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1276 1277 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1278 mask = cfg->mask_pcs_ready; 1279 1280 ret = readl_poll_timeout(status, val, !(val & mask), 1, 1281 PHY_INIT_COMPLETE_TIMEOUT); 1282 if (ret) { 1283 dev_err(qmp->dev, "phy initialization timed-out\n"); 1284 goto err_pcs_ready; 1285 } 1286 qmp->phy_initialized = true; 1287 1288out: 1289 return ret; 1290 1291err_pcs_ready: 1292 clk_disable_unprepare(qphy->pipe_clk); 1293err_clk_enable: 1294 if (cfg->has_lane_rst) 1295 reset_control_assert(qphy->lane_rst); 1296err_lane_rst: 1297 qcom_qmp_phy_com_exit(qmp); 1298 1299 return ret; 1300} 1301 1302static int qcom_qmp_phy_exit(struct phy *phy) 1303{ 1304 struct qmp_phy *qphy = phy_get_drvdata(phy); 1305 struct qcom_qmp *qmp = qphy->qmp; 1306 const struct qmp_phy_cfg *cfg = qmp->cfg; 1307 1308 clk_disable_unprepare(qphy->pipe_clk); 1309 1310 /* PHY reset */ 1311 if (!cfg->no_pcs_sw_reset) 1312 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1313 1314 /* stop SerDes and Phy-Coding-Sublayer */ 1315 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1316 1317 /* Put PHY into POWER DOWN state: active low */ 1318 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 1319 1320 if (cfg->has_lane_rst) 1321 reset_control_assert(qphy->lane_rst); 1322 1323 qcom_qmp_phy_com_exit(qmp); 1324 1325 qmp->phy_initialized = false; 1326 1327 return 0; 1328} 1329 1330static int qcom_qmp_phy_poweron(struct phy *phy) 1331{ 1332 struct qmp_phy *qphy = phy_get_drvdata(phy); 1333 struct qcom_qmp *qmp = qphy->qmp; 1334 const struct qmp_phy_cfg *cfg = qmp->cfg; 1335 void __iomem *pcs = qphy->pcs; 1336 void __iomem *status; 1337 unsigned int mask, val; 1338 int ret = 0; 1339 1340 if (cfg->type != PHY_TYPE_UFS) 1341 return 0; 1342 1343 /* 1344 * For UFS PHY that has not software reset control, serdes start 1345 * should only happen when UFS driver explicitly calls phy_power_on 1346 * after it deasserts software reset. 1347 */ 1348 if (cfg->no_pcs_sw_reset && !qmp->phy_initialized && 1349 (qmp->init_count != 0)) { 1350 /* start SerDes and Phy-Coding-Sublayer */ 1351 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1352 1353 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1354 mask = cfg->mask_pcs_ready; 1355 1356 ret = readl_poll_timeout(status, val, !(val & mask), 1, 1357 PHY_INIT_COMPLETE_TIMEOUT); 1358 if (ret) { 1359 dev_err(qmp->dev, "phy initialization timed-out\n"); 1360 return ret; 1361 } 1362 qmp->phy_initialized = true; 1363 } 1364 1365 return ret; 1366} 1367 1368static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode) 1369{ 1370 struct qmp_phy *qphy = phy_get_drvdata(phy); 1371 struct qcom_qmp *qmp = qphy->qmp; 1372 1373 qmp->mode = mode; 1374 1375 return 0; 1376} 1377 1378static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) 1379{ 1380 struct qcom_qmp *qmp = qphy->qmp; 1381 const struct qmp_phy_cfg *cfg = qmp->cfg; 1382 void __iomem *pcs = qphy->pcs; 1383 void __iomem *pcs_misc = qphy->pcs_misc; 1384 u32 intr_mask; 1385 1386 if (qmp->mode == PHY_MODE_USB_HOST_SS || 1387 qmp->mode == PHY_MODE_USB_DEVICE_SS) 1388 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 1389 else 1390 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 1391 1392 /* Clear any pending interrupts status */ 1393 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1394 /* Writing 1 followed by 0 clears the interrupt */ 1395 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1396 1397 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1398 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 1399 1400 /* Enable required PHY autonomous mode interrupts */ 1401 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 1402 1403 /* Enable i/o clamp_n for autonomous mode */ 1404 if (pcs_misc) 1405 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1406} 1407 1408static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) 1409{ 1410 struct qcom_qmp *qmp = qphy->qmp; 1411 const struct qmp_phy_cfg *cfg = qmp->cfg; 1412 void __iomem *pcs = qphy->pcs; 1413 void __iomem *pcs_misc = qphy->pcs_misc; 1414 1415 /* Disable i/o clamp_n on resume for normal mode */ 1416 if (pcs_misc) 1417 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1418 1419 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1420 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 1421 1422 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1423 /* Writing 1 followed by 0 clears the interrupt */ 1424 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1425} 1426 1427static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) 1428{ 1429 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1430 struct qmp_phy *qphy = qmp->phys[0]; 1431 const struct qmp_phy_cfg *cfg = qmp->cfg; 1432 1433 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 1434 1435 /* Supported only for USB3 PHY */ 1436 if (cfg->type != PHY_TYPE_USB3) 1437 return 0; 1438 1439 if (!qmp->phy_initialized) { 1440 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1441 return 0; 1442 } 1443 1444 qcom_qmp_phy_enable_autonomous_mode(qphy); 1445 1446 clk_disable_unprepare(qphy->pipe_clk); 1447 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1448 1449 return 0; 1450} 1451 1452static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) 1453{ 1454 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1455 struct qmp_phy *qphy = qmp->phys[0]; 1456 const struct qmp_phy_cfg *cfg = qmp->cfg; 1457 int ret = 0; 1458 1459 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 1460 1461 /* Supported only for USB3 PHY */ 1462 if (cfg->type != PHY_TYPE_USB3) 1463 return 0; 1464 1465 if (!qmp->phy_initialized) { 1466 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1467 return 0; 1468 } 1469 1470 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1471 if (ret) { 1472 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); 1473 return ret; 1474 } 1475 1476 ret = clk_prepare_enable(qphy->pipe_clk); 1477 if (ret) { 1478 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 1479 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1480 return ret; 1481 } 1482 1483 qcom_qmp_phy_disable_autonomous_mode(qphy); 1484 1485 return 0; 1486} 1487 1488static int qcom_qmp_phy_vreg_init(struct device *dev) 1489{ 1490 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1491 int num = qmp->cfg->num_vregs; 1492 int i; 1493 1494 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 1495 if (!qmp->vregs) 1496 return -ENOMEM; 1497 1498 for (i = 0; i < num; i++) 1499 qmp->vregs[i].supply = qmp->cfg->vreg_list[i]; 1500 1501 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1502} 1503 1504static int qcom_qmp_phy_reset_init(struct device *dev) 1505{ 1506 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1507 int i; 1508 1509 qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets, 1510 sizeof(*qmp->resets), GFP_KERNEL); 1511 if (!qmp->resets) 1512 return -ENOMEM; 1513 1514 for (i = 0; i < qmp->cfg->num_resets; i++) { 1515 struct reset_control *rst; 1516 const char *name = qmp->cfg->reset_list[i]; 1517 1518 rst = devm_reset_control_get(dev, name); 1519 if (IS_ERR(rst)) { 1520 dev_err(dev, "failed to get %s reset\n", name); 1521 return PTR_ERR(rst); 1522 } 1523 qmp->resets[i] = rst; 1524 } 1525 1526 return 0; 1527} 1528 1529static int qcom_qmp_phy_clk_init(struct device *dev) 1530{ 1531 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1532 int num = qmp->cfg->num_clks; 1533 int i; 1534 1535 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 1536 if (!qmp->clks) 1537 return -ENOMEM; 1538 1539 for (i = 0; i < num; i++) 1540 qmp->clks[i].id = qmp->cfg->clk_list[i]; 1541 1542 return devm_clk_bulk_get(dev, num, qmp->clks); 1543} 1544 1545/* 1546 * Register a fixed rate pipe clock. 1547 * 1548 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 1549 * controls it. The <s>_pipe_clk coming out of the GCC is requested 1550 * by the PHY driver for its operations. 1551 * We register the <s>_pipe_clksrc here. The gcc driver takes care 1552 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 1553 * Below picture shows this relationship. 1554 * 1555 * +---------------+ 1556 * | PHY block |<<---------------------------------------+ 1557 * | | | 1558 * | +-------+ | +-----+ | 1559 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 1560 * clk | +-------+ | +-----+ 1561 * +---------------+ 1562 */ 1563static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 1564{ 1565 struct clk_fixed_rate *fixed; 1566 struct clk_init_data init = { }; 1567 int ret; 1568 1569 if ((qmp->cfg->type != PHY_TYPE_USB3) && 1570 (qmp->cfg->type != PHY_TYPE_PCIE)) { 1571 /* not all phys register pipe clocks, so return success */ 1572 return 0; 1573 } 1574 1575 ret = of_property_read_string(np, "clock-output-names", &init.name); 1576 if (ret) { 1577 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 1578 return ret; 1579 } 1580 1581 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 1582 if (!fixed) 1583 return -ENOMEM; 1584 1585 init.ops = &clk_fixed_rate_ops; 1586 1587 /* controllers using QMP phys use 125MHz pipe clock interface */ 1588 fixed->fixed_rate = 125000000; 1589 fixed->hw.init = &init; 1590 1591 return devm_clk_hw_register(qmp->dev, &fixed->hw); 1592} 1593 1594static const struct phy_ops qcom_qmp_phy_gen_ops = { 1595 .init = qcom_qmp_phy_init, 1596 .exit = qcom_qmp_phy_exit, 1597 .power_on = qcom_qmp_phy_poweron, 1598 .set_mode = qcom_qmp_phy_set_mode, 1599 .owner = THIS_MODULE, 1600}; 1601 1602static 1603int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) 1604{ 1605 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1606 struct phy *generic_phy; 1607 struct qmp_phy *qphy; 1608 char prop_name[MAX_PROP_NAME]; 1609 int ret; 1610 1611 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 1612 if (!qphy) 1613 return -ENOMEM; 1614 1615 /* 1616 * Get memory resources for each phy lane: 1617 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; and 1618 * pcs_misc (optional) -> 3. 1619 */ 1620 qphy->tx = of_iomap(np, 0); 1621 if (!qphy->tx) 1622 return -ENOMEM; 1623 1624 qphy->rx = of_iomap(np, 1); 1625 if (!qphy->rx) 1626 return -ENOMEM; 1627 1628 qphy->pcs = of_iomap(np, 2); 1629 if (!qphy->pcs) 1630 return -ENOMEM; 1631 1632 qphy->pcs_misc = of_iomap(np, 3); 1633 if (!qphy->pcs_misc) 1634 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1635 1636 /* 1637 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 1638 * based phys, so they essentially have pipe clock. So, 1639 * we return error in case phy is USB3 or PIPE type. 1640 * Otherwise, we initialize pipe clock to NULL for 1641 * all phys that don't need this. 1642 */ 1643 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 1644 qphy->pipe_clk = of_clk_get_by_name(np, prop_name); 1645 if (IS_ERR(qphy->pipe_clk)) { 1646 if (qmp->cfg->type == PHY_TYPE_PCIE || 1647 qmp->cfg->type == PHY_TYPE_USB3) { 1648 ret = PTR_ERR(qphy->pipe_clk); 1649 if (ret != -EPROBE_DEFER) 1650 dev_err(dev, 1651 "failed to get lane%d pipe_clk, %d\n", 1652 id, ret); 1653 return ret; 1654 } 1655 qphy->pipe_clk = NULL; 1656 } 1657 1658 /* Get lane reset, if any */ 1659 if (qmp->cfg->has_lane_rst) { 1660 snprintf(prop_name, sizeof(prop_name), "lane%d", id); 1661 qphy->lane_rst = of_reset_control_get(np, prop_name); 1662 if (IS_ERR(qphy->lane_rst)) { 1663 dev_err(dev, "failed to get lane%d reset\n", id); 1664 return PTR_ERR(qphy->lane_rst); 1665 } 1666 } 1667 1668 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops); 1669 if (IS_ERR(generic_phy)) { 1670 ret = PTR_ERR(generic_phy); 1671 dev_err(dev, "failed to create qphy %d\n", ret); 1672 return ret; 1673 } 1674 1675 qphy->phy = generic_phy; 1676 qphy->index = id; 1677 qphy->qmp = qmp; 1678 qmp->phys[id] = qphy; 1679 phy_set_drvdata(generic_phy, qphy); 1680 1681 return 0; 1682} 1683 1684static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 1685 { 1686 .compatible = "qcom,msm8996-qmp-pcie-phy", 1687 .data = &msm8996_pciephy_cfg, 1688 }, { 1689 .compatible = "qcom,msm8996-qmp-usb3-phy", 1690 .data = &msm8996_usb3phy_cfg, 1691 }, { 1692 .compatible = "qcom,ipq8074-qmp-pcie-phy", 1693 .data = &ipq8074_pciephy_cfg, 1694 }, { 1695 .compatible = "qcom,sdm845-qmp-usb3-phy", 1696 .data = &qmp_v3_usb3phy_cfg, 1697 }, { 1698 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 1699 .data = &qmp_v3_usb3_uniphy_cfg, 1700 }, { 1701 .compatible = "qcom,sdm845-qmp-ufs-phy", 1702 .data = &sdm845_ufsphy_cfg, 1703 }, 1704 { }, 1705}; 1706MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); 1707 1708static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { 1709 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, 1710 qcom_qmp_phy_runtime_resume, NULL) 1711}; 1712 1713static int qcom_qmp_phy_probe(struct platform_device *pdev) 1714{ 1715 struct qcom_qmp *qmp; 1716 struct device *dev = &pdev->dev; 1717 struct resource *res; 1718 struct device_node *child; 1719 struct phy_provider *phy_provider; 1720 void __iomem *base; 1721 int num, id; 1722 int ret; 1723 1724 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1725 if (!qmp) 1726 return -ENOMEM; 1727 1728 qmp->dev = dev; 1729 dev_set_drvdata(dev, qmp); 1730 1731 /* Get the specific init parameters of QMP phy */ 1732 qmp->cfg = of_device_get_match_data(dev); 1733 if (!qmp->cfg) 1734 return -EINVAL; 1735 1736 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1737 base = devm_ioremap_resource(dev, res); 1738 if (IS_ERR(base)) 1739 return PTR_ERR(base); 1740 1741 /* per PHY serdes; usually located at base address */ 1742 qmp->serdes = base; 1743 1744 /* per PHY dp_com; if PHY has dp_com control block */ 1745 if (qmp->cfg->has_phy_dp_com_ctrl) { 1746 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1747 "dp_com"); 1748 base = devm_ioremap_resource(dev, res); 1749 if (IS_ERR(base)) 1750 return PTR_ERR(base); 1751 1752 qmp->dp_com = base; 1753 } 1754 1755 mutex_init(&qmp->phy_mutex); 1756 1757 ret = qcom_qmp_phy_clk_init(dev); 1758 if (ret) 1759 return ret; 1760 1761 ret = qcom_qmp_phy_reset_init(dev); 1762 if (ret) 1763 return ret; 1764 1765 ret = qcom_qmp_phy_vreg_init(dev); 1766 if (ret) { 1767 if (ret != -EPROBE_DEFER) 1768 dev_err(dev, "failed to get regulator supplies: %d\n", 1769 ret); 1770 return ret; 1771 } 1772 1773 num = of_get_available_child_count(dev->of_node); 1774 /* do we have a rogue child node ? */ 1775 if (num > qmp->cfg->nlanes) 1776 return -EINVAL; 1777 1778 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 1779 if (!qmp->phys) 1780 return -ENOMEM; 1781 1782 id = 0; 1783 pm_runtime_set_active(dev); 1784 pm_runtime_enable(dev); 1785 /* 1786 * Prevent runtime pm from being ON by default. Users can enable 1787 * it using power/control in sysfs. 1788 */ 1789 pm_runtime_forbid(dev); 1790 1791 for_each_available_child_of_node(dev->of_node, child) { 1792 /* Create per-lane phy */ 1793 ret = qcom_qmp_phy_create(dev, child, id); 1794 if (ret) { 1795 dev_err(dev, "failed to create lane%d phy, %d\n", 1796 id, ret); 1797 pm_runtime_disable(dev); 1798 return ret; 1799 } 1800 1801 /* 1802 * Register the pipe clock provided by phy. 1803 * See function description to see details of this pipe clock. 1804 */ 1805 ret = phy_pipe_clk_register(qmp, child); 1806 if (ret) { 1807 dev_err(qmp->dev, 1808 "failed to register pipe clock source\n"); 1809 pm_runtime_disable(dev); 1810 return ret; 1811 } 1812 id++; 1813 } 1814 1815 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1816 if (!IS_ERR(phy_provider)) 1817 dev_info(dev, "Registered Qcom-QMP phy\n"); 1818 else 1819 pm_runtime_disable(dev); 1820 1821 return PTR_ERR_OR_ZERO(phy_provider); 1822} 1823 1824static struct platform_driver qcom_qmp_phy_driver = { 1825 .probe = qcom_qmp_phy_probe, 1826 .driver = { 1827 .name = "qcom-qmp-phy", 1828 .pm = &qcom_qmp_phy_pm_ops, 1829 .of_match_table = qcom_qmp_phy_of_match_table, 1830 }, 1831}; 1832 1833module_platform_driver(qcom_qmp_phy_driver); 1834 1835MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1836MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); 1837MODULE_LICENSE("GPL v2");