tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* stk-sensor.c: Driver for ov96xx sensor (used in some Syntek webcams)
2 *
3 * Copyright 2007-2008 Jaime Velasco Juan <jsagarribay@gmail.com>
4 *
5 * Some parts derived from ov7670.c:
6 * Copyright 2006 One Laptop Per Child Association, Inc. Written
7 * by Jonathan Corbet with substantial inspiration from Mark
8 * McClelland's ovcamchip code.
9 *
10 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
11 *
12 * This file may be distributed under the terms of the GNU General
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24/* Controlling the sensor via the STK1125 vendor specific control interface:
25 * The camera uses an OmniVision sensor and the stk1125 provides an
26 * SCCB(i2c)-USB bridge which let us program the sensor.
27 * In my case the sensor id is 0x9652, it can be read from sensor's register
28 * 0x0A and 0x0B as follows:
29 * - read register #R:
30 * output #R to index 0x0208
31 * output 0x0070 to index 0x0200
32 * input 1 byte from index 0x0201 (some kind of status register)
33 * until its value is 0x01
34 * input 1 byte from index 0x0209. This is the value of #R
35 * - write value V to register #R
36 * output #R to index 0x0204
37 * output V to index 0x0205
38 * output 0x0005 to index 0x0200
39 * input 1 byte from index 0x0201 until its value becomes 0x04
40 */
41
42/* It seems the i2c bus is controlled with these registers */
43
44#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
46#include "stk-webcam.h"
47
48#define STK_IIC_BASE (0x0200)
49# define STK_IIC_OP (STK_IIC_BASE)
50# define STK_IIC_OP_TX (0x05)
51# define STK_IIC_OP_RX (0x70)
52# define STK_IIC_STAT (STK_IIC_BASE+1)
53# define STK_IIC_STAT_TX_OK (0x04)
54# define STK_IIC_STAT_RX_OK (0x01)
55/* I don't know what does this register.
56 * when it is 0x00 or 0x01, we cannot talk to the sensor,
57 * other values work */
58# define STK_IIC_ENABLE (STK_IIC_BASE+2)
59# define STK_IIC_ENABLE_NO (0x00)
60/* This is what the driver writes in windows */
61# define STK_IIC_ENABLE_YES (0x1e)
62/*
63 * Address of the slave. Seems like the binary driver look for the
64 * sensor in multiple places, attempting a reset sequence.
65 * We only know about the ov9650
66 */
67# define STK_IIC_ADDR (STK_IIC_BASE+3)
68# define STK_IIC_TX_INDEX (STK_IIC_BASE+4)
69# define STK_IIC_TX_VALUE (STK_IIC_BASE+5)
70# define STK_IIC_RX_INDEX (STK_IIC_BASE+8)
71# define STK_IIC_RX_VALUE (STK_IIC_BASE+9)
72
73#define MAX_RETRIES (50)
74
75#define SENSOR_ADDRESS (0x60)
76
77/* From ov7670.c (These registers aren't fully accurate) */
78
79/* Registers */
80#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
81#define REG_BLUE 0x01 /* blue gain */
82#define REG_RED 0x02 /* red gain */
83#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
84#define REG_COM1 0x04 /* Control 1 */
85#define COM1_CCIR656 0x40 /* CCIR656 enable */
86#define COM1_QFMT 0x20 /* QVGA/QCIF format */
87#define COM1_SKIP_0 0x00 /* Do not skip any row */
88#define COM1_SKIP_2 0x04 /* Skip 2 rows of 4 */
89#define COM1_SKIP_3 0x08 /* Skip 3 rows of 4 */
90#define REG_BAVE 0x05 /* U/B Average level */
91#define REG_GbAVE 0x06 /* Y/Gb Average level */
92#define REG_AECHH 0x07 /* AEC MS 5 bits */
93#define REG_RAVE 0x08 /* V/R Average level */
94#define REG_COM2 0x09 /* Control 2 */
95#define COM2_SSLEEP 0x10 /* Soft sleep mode */
96#define REG_PID 0x0a /* Product ID MSB */
97#define REG_VER 0x0b /* Product ID LSB */
98#define REG_COM3 0x0c /* Control 3 */
99#define COM3_SWAP 0x40 /* Byte swap */
100#define COM3_SCALEEN 0x08 /* Enable scaling */
101#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
102#define REG_COM4 0x0d /* Control 4 */
103#define REG_COM5 0x0e /* All "reserved" */
104#define REG_COM6 0x0f /* Control 6 */
105#define REG_AECH 0x10 /* More bits of AEC value */
106#define REG_CLKRC 0x11 /* Clock control */
107#define CLK_PLL 0x80 /* Enable internal PLL */
108#define CLK_EXT 0x40 /* Use external clock directly */
109#define CLK_SCALE 0x3f /* Mask for internal clock scale */
110#define REG_COM7 0x12 /* Control 7 */
111#define COM7_RESET 0x80 /* Register reset */
112#define COM7_FMT_MASK 0x38
113#define COM7_FMT_SXGA 0x00
114#define COM7_FMT_VGA 0x40
115#define COM7_FMT_CIF 0x20 /* CIF format */
116#define COM7_FMT_QVGA 0x10 /* QVGA format */
117#define COM7_FMT_QCIF 0x08 /* QCIF format */
118#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
119#define COM7_YUV 0x00 /* YUV */
120#define COM7_BAYER 0x01 /* Bayer format */
121#define COM7_PBAYER 0x05 /* "Processed bayer" */
122#define REG_COM8 0x13 /* Control 8 */
123#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
124#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
125#define COM8_BFILT 0x20 /* Band filter enable */
126#define COM8_AGC 0x04 /* Auto gain enable */
127#define COM8_AWB 0x02 /* White balance enable */
128#define COM8_AEC 0x01 /* Auto exposure enable */
129#define REG_COM9 0x14 /* Control 9 - gain ceiling */
130#define REG_COM10 0x15 /* Control 10 */
131#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
132#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
133#define COM10_HREF_REV 0x08 /* Reverse HREF */
134#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
135#define COM10_VS_NEG 0x02 /* VSYNC negative */
136#define COM10_HS_NEG 0x01 /* HSYNC negative */
137#define REG_HSTART 0x17 /* Horiz start high bits */
138#define REG_HSTOP 0x18 /* Horiz stop high bits */
139#define REG_VSTART 0x19 /* Vert start high bits */
140#define REG_VSTOP 0x1a /* Vert stop high bits */
141#define REG_PSHFT 0x1b /* Pixel delay after HREF */
142#define REG_MIDH 0x1c /* Manuf. ID high */
143#define REG_MIDL 0x1d /* Manuf. ID low */
144#define REG_MVFP 0x1e /* Mirror / vflip */
145#define MVFP_MIRROR 0x20 /* Mirror image */
146#define MVFP_FLIP 0x10 /* Vertical flip */
147
148#define REG_AEW 0x24 /* AGC upper limit */
149#define REG_AEB 0x25 /* AGC lower limit */
150#define REG_VPT 0x26 /* AGC/AEC fast mode op region */
151#define REG_ADVFL 0x2d /* Insert dummy lines (LSB) */
152#define REG_ADVFH 0x2e /* Insert dummy lines (MSB) */
153#define REG_HSYST 0x30 /* HSYNC rising edge delay */
154#define REG_HSYEN 0x31 /* HSYNC falling edge delay */
155#define REG_HREF 0x32 /* HREF pieces */
156#define REG_TSLB 0x3a /* lots of stuff */
157#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
158#define TSLB_BYTEORD 0x08 /* swap bytes in 16bit mode? */
159#define REG_COM11 0x3b /* Control 11 */
160#define COM11_NIGHT 0x80 /* NIght mode enable */
161#define COM11_NMFR 0x60 /* Two bit NM frame rate */
162#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
163#define COM11_50HZ 0x08 /* Manual 50Hz select */
164#define COM11_EXP 0x02
165#define REG_COM12 0x3c /* Control 12 */
166#define COM12_HREF 0x80 /* HREF always */
167#define REG_COM13 0x3d /* Control 13 */
168#define COM13_GAMMA 0x80 /* Gamma enable */
169#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
170#define COM13_CMATRIX 0x10 /* Enable color matrix for RGB or YUV */
171#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
172#define REG_COM14 0x3e /* Control 14 */
173#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
174#define REG_EDGE 0x3f /* Edge enhancement factor */
175#define REG_COM15 0x40 /* Control 15 */
176#define COM15_R10F0 0x00 /* Data range 10 to F0 */
177#define COM15_R01FE 0x80 /* 01 to FE */
178#define COM15_R00FF 0xc0 /* 00 to FF */
179#define COM15_RGB565 0x10 /* RGB565 output */
180#define COM15_RGBFIXME 0x20 /* FIXME */
181#define COM15_RGB555 0x30 /* RGB555 output */
182#define REG_COM16 0x41 /* Control 16 */
183#define COM16_AWBGAIN 0x08 /* AWB gain enable */
184#define REG_COM17 0x42 /* Control 17 */
185#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
186#define COM17_CBAR 0x08 /* DSP Color bar */
187
188/*
189 * This matrix defines how the colors are generated, must be
190 * tweaked to adjust hue and saturation.
191 *
192 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
193 *
194 * They are nine-bit signed quantities, with the sign bit
195 * stored in 0x58. Sign for v-red is bit 0, and up from there.
196 */
197#define REG_CMATRIX_BASE 0x4f
198#define CMATRIX_LEN 6
199#define REG_CMATRIX_SIGN 0x58
200
201
202#define REG_BRIGHT 0x55 /* Brightness */
203#define REG_CONTRAS 0x56 /* Contrast control */
204
205#define REG_GFIX 0x69 /* Fix gain control */
206
207#define REG_RGB444 0x8c /* RGB 444 control */
208#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
209#define R444_RGBX 0x01 /* Empty nibble at end */
210
211#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
212#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
213
214#define REG_BD50MAX 0xa5 /* 50hz banding step limit */
215#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
216#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
217#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
218#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
219#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
220#define REG_BD60MAX 0xab /* 60hz banding step limit */
221
222
223
224
225/* Returns 0 if OK */
226static int stk_sensor_outb(struct stk_camera *dev, u8 reg, u8 val)
227{
228 int i = 0;
229 u8 tmpval = 0;
230
231 if (stk_camera_write_reg(dev, STK_IIC_TX_INDEX, reg))
232 return 1;
233 if (stk_camera_write_reg(dev, STK_IIC_TX_VALUE, val))
234 return 1;
235 if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_TX))
236 return 1;
237 do {
238 if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval))
239 return 1;
240 i++;
241 } while (tmpval == 0 && i < MAX_RETRIES);
242 if (tmpval != STK_IIC_STAT_TX_OK) {
243 if (tmpval)
244 pr_err("stk_sensor_outb failed, status=0x%02x\n",
245 tmpval);
246 return 1;
247 } else
248 return 0;
249}
250
251static int stk_sensor_inb(struct stk_camera *dev, u8 reg, u8 *val)
252{
253 int i = 0;
254 u8 tmpval = 0;
255
256 if (stk_camera_write_reg(dev, STK_IIC_RX_INDEX, reg))
257 return 1;
258 if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_RX))
259 return 1;
260 do {
261 if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval))
262 return 1;
263 i++;
264 } while (tmpval == 0 && i < MAX_RETRIES);
265 if (tmpval != STK_IIC_STAT_RX_OK) {
266 if (tmpval)
267 pr_err("stk_sensor_inb failed, status=0x%02x\n",
268 tmpval);
269 return 1;
270 }
271
272 if (stk_camera_read_reg(dev, STK_IIC_RX_VALUE, &tmpval))
273 return 1;
274
275 *val = tmpval;
276 return 0;
277}
278
279static int stk_sensor_write_regvals(struct stk_camera *dev,
280 struct regval *rv)
281{
282 int ret;
283 if (rv == NULL)
284 return 0;
285 while (rv->reg != 0xff || rv->val != 0xff) {
286 ret = stk_sensor_outb(dev, rv->reg, rv->val);
287 if (ret != 0)
288 return ret;
289 rv++;
290 }
291 return 0;
292}
293
294int stk_sensor_sleep(struct stk_camera *dev)
295{
296 u8 tmp;
297 return stk_sensor_inb(dev, REG_COM2, &tmp)
298 || stk_sensor_outb(dev, REG_COM2, tmp|COM2_SSLEEP);
299}
300
301int stk_sensor_wakeup(struct stk_camera *dev)
302{
303 u8 tmp;
304 return stk_sensor_inb(dev, REG_COM2, &tmp)
305 || stk_sensor_outb(dev, REG_COM2, tmp&~COM2_SSLEEP);
306}
307
308static struct regval ov_initvals[] = {
309 {REG_CLKRC, CLK_PLL},
310 {REG_COM11, 0x01},
311 {0x6a, 0x7d},
312 {REG_AECH, 0x40},
313 {REG_GAIN, 0x00},
314 {REG_BLUE, 0x80},
315 {REG_RED, 0x80},
316 /* Do not enable fast AEC for now */
317 /*{REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC},*/
318 {REG_COM8, COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC},
319 {0x39, 0x50}, {0x38, 0x93},
320 {0x37, 0x00}, {0x35, 0x81},
321 {REG_COM5, 0x20},
322 {REG_COM1, 0x00},
323 {REG_COM3, 0x00},
324 {REG_COM4, 0x00},
325 {REG_PSHFT, 0x00},
326 {0x16, 0x07},
327 {0x33, 0xe2}, {0x34, 0xbf},
328 {REG_COM16, 0x00},
329 {0x96, 0x04},
330 /* Gamma curve values */
331/* { 0x7a, 0x20 }, { 0x7b, 0x10 },
332 { 0x7c, 0x1e }, { 0x7d, 0x35 },
333 { 0x7e, 0x5a }, { 0x7f, 0x69 },
334 { 0x80, 0x76 }, { 0x81, 0x80 },
335 { 0x82, 0x88 }, { 0x83, 0x8f },
336 { 0x84, 0x96 }, { 0x85, 0xa3 },
337 { 0x86, 0xaf }, { 0x87, 0xc4 },
338 { 0x88, 0xd7 }, { 0x89, 0xe8 },
339*/
340 {REG_GFIX, 0x40},
341 {0x8e, 0x00},
342 {REG_COM12, 0x73},
343 {0x8f, 0xdf}, {0x8b, 0x06},
344 {0x8c, 0x20},
345 {0x94, 0x88}, {0x95, 0x88},
346/* {REG_COM15, 0xc1}, TODO */
347 {0x29, 0x3f},
348 {REG_COM6, 0x42},
349 {REG_BD50MAX, 0x80},
350 {REG_HAECC6, 0xb8}, {REG_HAECC7, 0x92},
351 {REG_BD60MAX, 0x0a},
352 {0x90, 0x00}, {0x91, 0x00},
353 {REG_HAECC1, 0x00}, {REG_HAECC2, 0x00},
354 {REG_AEW, 0x68}, {REG_AEB, 0x5c},
355 {REG_VPT, 0xc3},
356 {REG_COM9, 0x2e},
357 {0x2a, 0x00}, {0x2b, 0x00},
358
359 {0xff, 0xff}, /* END MARKER */
360};
361
362/* Probe the I2C bus and initialise the sensor chip */
363int stk_sensor_init(struct stk_camera *dev)
364{
365 u8 idl = 0;
366 u8 idh = 0;
367
368 if (stk_camera_write_reg(dev, STK_IIC_ENABLE, STK_IIC_ENABLE_YES)
369 || stk_camera_write_reg(dev, STK_IIC_ADDR, SENSOR_ADDRESS)
370 || stk_sensor_outb(dev, REG_COM7, COM7_RESET)) {
371 pr_err("Sensor resetting failed\n");
372 return -ENODEV;
373 }
374 msleep(10);
375 /* Read the manufacturer ID: ov = 0x7FA2 */
376 if (stk_sensor_inb(dev, REG_MIDH, &idh)
377 || stk_sensor_inb(dev, REG_MIDL, &idl)) {
378 pr_err("Strange error reading sensor ID\n");
379 return -ENODEV;
380 }
381 if (idh != 0x7f || idl != 0xa2) {
382 pr_err("Huh? you don't have a sensor from ovt\n");
383 return -ENODEV;
384 }
385 if (stk_sensor_inb(dev, REG_PID, &idh)
386 || stk_sensor_inb(dev, REG_VER, &idl)) {
387 pr_err("Could not read sensor model\n");
388 return -ENODEV;
389 }
390 stk_sensor_write_regvals(dev, ov_initvals);
391 msleep(10);
392 pr_info("OmniVision sensor detected, id %02X%02X at address %x\n",
393 idh, idl, SENSOR_ADDRESS);
394 return 0;
395}
396
397/* V4L2_PIX_FMT_UYVY */
398static struct regval ov_fmt_uyvy[] = {
399 {REG_TSLB, TSLB_YLAST|0x08 },
400 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
401 { 0x50, 0x80 }, /* "matrix coefficient 2" */
402 { 0x51, 0 }, /* vb */
403 { 0x52, 0x22 }, /* "matrix coefficient 4" */
404 { 0x53, 0x5e }, /* "matrix coefficient 5" */
405 { 0x54, 0x80 }, /* "matrix coefficient 6" */
406 {REG_COM13, COM13_UVSAT|COM13_CMATRIX},
407 {REG_COM15, COM15_R00FF },
408 {0xff, 0xff}, /* END MARKER */
409};
410/* V4L2_PIX_FMT_YUYV */
411static struct regval ov_fmt_yuyv[] = {
412 {REG_TSLB, 0 },
413 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
414 { 0x50, 0x80 }, /* "matrix coefficient 2" */
415 { 0x51, 0 }, /* vb */
416 { 0x52, 0x22 }, /* "matrix coefficient 4" */
417 { 0x53, 0x5e }, /* "matrix coefficient 5" */
418 { 0x54, 0x80 }, /* "matrix coefficient 6" */
419 {REG_COM13, COM13_UVSAT|COM13_CMATRIX},
420 {REG_COM15, COM15_R00FF },
421 {0xff, 0xff}, /* END MARKER */
422};
423
424/* V4L2_PIX_FMT_RGB565X rrrrrggg gggbbbbb */
425static struct regval ov_fmt_rgbr[] = {
426 { REG_RGB444, 0 }, /* No RGB444 please */
427 {REG_TSLB, 0x00},
428 { REG_COM1, 0x0 },
429 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
430 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
431 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
432 { 0x51, 0 }, /* vb */
433 { 0x52, 0x3d }, /* "matrix coefficient 4" */
434 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
435 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
436 { REG_COM13, COM13_GAMMA },
437 { REG_COM15, COM15_RGB565|COM15_R00FF },
438 { 0xff, 0xff },
439};
440
441/* V4L2_PIX_FMT_RGB565 gggbbbbb rrrrrggg */
442static struct regval ov_fmt_rgbp[] = {
443 { REG_RGB444, 0 }, /* No RGB444 please */
444 {REG_TSLB, TSLB_BYTEORD },
445 { REG_COM1, 0x0 },
446 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
447 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
448 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
449 { 0x51, 0 }, /* vb */
450 { 0x52, 0x3d }, /* "matrix coefficient 4" */
451 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
452 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
453 { REG_COM13, COM13_GAMMA },
454 { REG_COM15, COM15_RGB565|COM15_R00FF },
455 { 0xff, 0xff },
456};
457
458/* V4L2_PIX_FMT_SRGGB8 */
459static struct regval ov_fmt_bayer[] = {
460 /* This changes color order */
461 {REG_TSLB, 0x40}, /* BGGR */
462 /* {REG_TSLB, 0x08}, */ /* BGGR with vertical image flipping */
463 {REG_COM15, COM15_R00FF },
464 {0xff, 0xff}, /* END MARKER */
465};
466/*
467 * Store a set of start/stop values into the camera.
468 */
469static int stk_sensor_set_hw(struct stk_camera *dev,
470 int hstart, int hstop, int vstart, int vstop)
471{
472 int ret;
473 unsigned char v;
474/*
475 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
476 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
477 * a mystery "edge offset" value in the top two bits of href.
478 */
479 ret = stk_sensor_outb(dev, REG_HSTART, (hstart >> 3) & 0xff);
480 ret += stk_sensor_outb(dev, REG_HSTOP, (hstop >> 3) & 0xff);
481 ret += stk_sensor_inb(dev, REG_HREF, &v);
482 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
483 msleep(10);
484 ret += stk_sensor_outb(dev, REG_HREF, v);
485/*
486 * Vertical: similar arrangement (note: this is different from ov7670.c)
487 */
488 ret += stk_sensor_outb(dev, REG_VSTART, (vstart >> 3) & 0xff);
489 ret += stk_sensor_outb(dev, REG_VSTOP, (vstop >> 3) & 0xff);
490 ret += stk_sensor_inb(dev, REG_VREF, &v);
491 v = (v & 0xc0) | ((vstop & 0x7) << 3) | (vstart & 0x7);
492 msleep(10);
493 ret += stk_sensor_outb(dev, REG_VREF, v);
494 return ret;
495}
496
497
498int stk_sensor_configure(struct stk_camera *dev)
499{
500 int com7;
501 /*
502 * We setup the sensor to output dummy lines in low-res modes,
503 * so we don't get absurdly hight framerates.
504 */
505 unsigned dummylines;
506 int flip;
507 struct regval *rv;
508
509 switch (dev->vsettings.mode) {
510 case MODE_QCIF: com7 = COM7_FMT_QCIF;
511 dummylines = 604;
512 break;
513 case MODE_QVGA: com7 = COM7_FMT_QVGA;
514 dummylines = 267;
515 break;
516 case MODE_CIF: com7 = COM7_FMT_CIF;
517 dummylines = 412;
518 break;
519 case MODE_VGA: com7 = COM7_FMT_VGA;
520 dummylines = 11;
521 break;
522 case MODE_SXGA: com7 = COM7_FMT_SXGA;
523 dummylines = 0;
524 break;
525 default:
526 pr_err("Unsupported mode %d\n", dev->vsettings.mode);
527 return -EFAULT;
528 }
529 switch (dev->vsettings.palette) {
530 case V4L2_PIX_FMT_UYVY:
531 com7 |= COM7_YUV;
532 rv = ov_fmt_uyvy;
533 break;
534 case V4L2_PIX_FMT_YUYV:
535 com7 |= COM7_YUV;
536 rv = ov_fmt_yuyv;
537 break;
538 case V4L2_PIX_FMT_RGB565:
539 com7 |= COM7_RGB;
540 rv = ov_fmt_rgbp;
541 break;
542 case V4L2_PIX_FMT_RGB565X:
543 com7 |= COM7_RGB;
544 rv = ov_fmt_rgbr;
545 break;
546 case V4L2_PIX_FMT_SBGGR8:
547 com7 |= COM7_PBAYER;
548 rv = ov_fmt_bayer;
549 break;
550 default:
551 pr_err("Unsupported colorspace\n");
552 return -EFAULT;
553 }
554 /*FIXME sometimes the sensor go to a bad state
555 stk_sensor_write_regvals(dev, ov_initvals); */
556 stk_sensor_outb(dev, REG_COM7, com7);
557 msleep(50);
558 stk_sensor_write_regvals(dev, rv);
559 flip = (dev->vsettings.vflip?MVFP_FLIP:0)
560 | (dev->vsettings.hflip?MVFP_MIRROR:0);
561 stk_sensor_outb(dev, REG_MVFP, flip);
562 if (dev->vsettings.palette == V4L2_PIX_FMT_SBGGR8
563 && !dev->vsettings.vflip)
564 stk_sensor_outb(dev, REG_TSLB, 0x08);
565 stk_sensor_outb(dev, REG_ADVFH, dummylines >> 8);
566 stk_sensor_outb(dev, REG_ADVFL, dummylines & 0xff);
567 msleep(50);
568 switch (dev->vsettings.mode) {
569 case MODE_VGA:
570 if (stk_sensor_set_hw(dev, 302, 1582, 6, 486))
571 pr_err("stk_sensor_set_hw failed (VGA)\n");
572 break;
573 case MODE_SXGA:
574 case MODE_CIF:
575 case MODE_QVGA:
576 case MODE_QCIF:
577 /*FIXME These settings seem ignored by the sensor
578 if (stk_sensor_set_hw(dev, 220, 1500, 10, 1034))
579 pr_err("stk_sensor_set_hw failed (SXGA)\n");
580 */
581 break;
582 }
583 msleep(10);
584 return 0;
585}
586
587int stk_sensor_set_brightness(struct stk_camera *dev, int br)
588{
589 if (br < 0 || br > 0xff)
590 return -EINVAL;
591 stk_sensor_outb(dev, REG_AEB, max(0x00, br - 6));
592 stk_sensor_outb(dev, REG_AEW, min(0xff, br + 6));
593 return 0;
594}
595