tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk-provider.h>
19#include <linux/clkdev.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define CLK_SOURCE_I2S0 0x1d8
30#define CLK_SOURCE_I2S1 0x100
31#define CLK_SOURCE_I2S2 0x104
32#define CLK_SOURCE_NDFLASH 0x160
33#define CLK_SOURCE_I2S3 0x3bc
34#define CLK_SOURCE_I2S4 0x3c0
35#define CLK_SOURCE_SPDIF_OUT 0x108
36#define CLK_SOURCE_SPDIF_IN 0x10c
37#define CLK_SOURCE_PWM 0x110
38#define CLK_SOURCE_ADX 0x638
39#define CLK_SOURCE_ADX1 0x670
40#define CLK_SOURCE_AMX 0x63c
41#define CLK_SOURCE_AMX1 0x674
42#define CLK_SOURCE_HDA 0x428
43#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
44#define CLK_SOURCE_SBC1 0x134
45#define CLK_SOURCE_SBC2 0x118
46#define CLK_SOURCE_SBC3 0x11c
47#define CLK_SOURCE_SBC4 0x1b4
48#define CLK_SOURCE_SBC5 0x3c8
49#define CLK_SOURCE_SBC6 0x3cc
50#define CLK_SOURCE_SATA_OOB 0x420
51#define CLK_SOURCE_SATA 0x424
52#define CLK_SOURCE_NDSPEED 0x3f8
53#define CLK_SOURCE_VFIR 0x168
54#define CLK_SOURCE_SDMMC1 0x150
55#define CLK_SOURCE_SDMMC2 0x154
56#define CLK_SOURCE_SDMMC3 0x1bc
57#define CLK_SOURCE_SDMMC4 0x164
58#define CLK_SOURCE_CVE 0x140
59#define CLK_SOURCE_TVO 0x188
60#define CLK_SOURCE_TVDAC 0x194
61#define CLK_SOURCE_VDE 0x1c8
62#define CLK_SOURCE_CSITE 0x1d4
63#define CLK_SOURCE_LA 0x1f8
64#define CLK_SOURCE_TRACE 0x634
65#define CLK_SOURCE_OWR 0x1cc
66#define CLK_SOURCE_NOR 0x1d0
67#define CLK_SOURCE_MIPI 0x174
68#define CLK_SOURCE_I2C1 0x124
69#define CLK_SOURCE_I2C2 0x198
70#define CLK_SOURCE_I2C3 0x1b8
71#define CLK_SOURCE_I2C4 0x3c4
72#define CLK_SOURCE_I2C5 0x128
73#define CLK_SOURCE_I2C6 0x65c
74#define CLK_SOURCE_UARTA 0x178
75#define CLK_SOURCE_UARTB 0x17c
76#define CLK_SOURCE_UARTC 0x1a0
77#define CLK_SOURCE_UARTD 0x1c0
78#define CLK_SOURCE_UARTE 0x1c4
79#define CLK_SOURCE_3D 0x158
80#define CLK_SOURCE_2D 0x15c
81#define CLK_SOURCE_MPE 0x170
82#define CLK_SOURCE_UARTE 0x1c4
83#define CLK_SOURCE_VI_SENSOR 0x1a8
84#define CLK_SOURCE_VI 0x148
85#define CLK_SOURCE_EPP 0x16c
86#define CLK_SOURCE_MSENC 0x1f0
87#define CLK_SOURCE_TSEC 0x1f4
88#define CLK_SOURCE_HOST1X 0x180
89#define CLK_SOURCE_HDMI 0x18c
90#define CLK_SOURCE_DISP1 0x138
91#define CLK_SOURCE_DISP2 0x13c
92#define CLK_SOURCE_CILAB 0x614
93#define CLK_SOURCE_CILCD 0x618
94#define CLK_SOURCE_CILE 0x61c
95#define CLK_SOURCE_DSIALP 0x620
96#define CLK_SOURCE_DSIBLP 0x624
97#define CLK_SOURCE_TSENSOR 0x3b8
98#define CLK_SOURCE_D_AUDIO 0x3d0
99#define CLK_SOURCE_DAM0 0x3d8
100#define CLK_SOURCE_DAM1 0x3dc
101#define CLK_SOURCE_DAM2 0x3e0
102#define CLK_SOURCE_ACTMON 0x3e8
103#define CLK_SOURCE_EXTERN1 0x3ec
104#define CLK_SOURCE_EXTERN2 0x3f0
105#define CLK_SOURCE_EXTERN3 0x3f4
106#define CLK_SOURCE_I2CSLOW 0x3fc
107#define CLK_SOURCE_SE 0x42c
108#define CLK_SOURCE_MSELECT 0x3b4
109#define CLK_SOURCE_DFLL_REF 0x62c
110#define CLK_SOURCE_DFLL_SOC 0x630
111#define CLK_SOURCE_SOC_THERM 0x644
112#define CLK_SOURCE_XUSB_HOST_SRC 0x600
113#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
114#define CLK_SOURCE_XUSB_FS_SRC 0x608
115#define CLK_SOURCE_XUSB_SS_SRC 0x610
116#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
117#define CLK_SOURCE_ISP 0x144
118#define CLK_SOURCE_SOR0 0x414
119#define CLK_SOURCE_DPAUX 0x418
120#define CLK_SOURCE_SATA_OOB 0x420
121#define CLK_SOURCE_SATA 0x424
122#define CLK_SOURCE_ENTROPY 0x628
123#define CLK_SOURCE_VI_SENSOR2 0x658
124#define CLK_SOURCE_HDMI_AUDIO 0x668
125#define CLK_SOURCE_VIC03 0x678
126#define CLK_SOURCE_CLK72MHZ 0x66c
127#define CLK_SOURCE_DBGAPB 0x718
128#define CLK_SOURCE_NVENC 0x6a0
129#define CLK_SOURCE_NVDEC 0x698
130#define CLK_SOURCE_NVJPG 0x69c
131#define CLK_SOURCE_APE 0x6c0
132#define CLK_SOURCE_SDMMC_LEGACY 0x694
133#define CLK_SOURCE_QSPI 0x6c4
134#define CLK_SOURCE_VI_I2C 0x6c8
135#define CLK_SOURCE_MIPIBIF 0x660
136#define CLK_SOURCE_UARTAPE 0x710
137#define CLK_SOURCE_TSECB 0x6d8
138#define CLK_SOURCE_MAUD 0x6d4
139#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
140#define CLK_SOURCE_DMIC1 0x64c
141#define CLK_SOURCE_DMIC2 0x650
142#define CLK_SOURCE_DMIC3 0x6bc
143
144#define MASK(x) (BIT(x) - 1)
145
146#define MUX(_name, _parents, _offset, \
147 _clk_num, _gate_flags, _clk_id) \
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
149 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
150 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
151 NULL)
152
153#define MUX_FLAGS(_name, _parents, _offset,\
154 _clk_num, _gate_flags, _clk_id, flags)\
155 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
156 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
157 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
158 NULL)
159
160#define MUX8(_name, _parents, _offset, \
161 _clk_num, _gate_flags, _clk_id) \
162 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
163 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
164 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
165 NULL)
166
167#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \
168 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
169 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
170 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
171 _parents##_idx, 0, _lock)
172
173#define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \
174 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
175 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
176 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
177 _parents##_idx, 0, NULL)
178
179#define INT(_name, _parents, _offset, \
180 _clk_num, _gate_flags, _clk_id) \
181 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
182 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
183 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
184 _clk_id, _parents##_idx, 0, NULL)
185
186#define INT_FLAGS(_name, _parents, _offset,\
187 _clk_num, _gate_flags, _clk_id, flags)\
188 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
189 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
190 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
191 _clk_id, _parents##_idx, flags, NULL)
192
193#define INT8(_name, _parents, _offset,\
194 _clk_num, _gate_flags, _clk_id) \
195 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
196 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
197 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
198 _clk_id, _parents##_idx, 0, NULL)
199
200#define UART(_name, _parents, _offset,\
201 _clk_num, _clk_id) \
202 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
203 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
204 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
205 _parents##_idx, 0, NULL)
206
207#define UART8(_name, _parents, _offset,\
208 _clk_num, _clk_id) \
209 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
210 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
211 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
212 _parents##_idx, 0, NULL)
213
214#define I2C(_name, _parents, _offset,\
215 _clk_num, _clk_id) \
216 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
217 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
218 _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
219 _parents##_idx, 0, NULL)
220
221#define XUSB(_name, _parents, _offset, \
222 _clk_num, _gate_flags, _clk_id) \
223 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
224 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
225 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
226 _clk_id, _parents##_idx, 0, NULL)
227
228#define AUDIO(_name, _offset, _clk_num,\
229 _gate_flags, _clk_id) \
230 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
231 _offset, 16, 0xE01F, 0, 0, 8, 1, \
232 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
233 _clk_id, mux_d_audio_clk_idx, 0, NULL)
234
235#define NODIV(_name, _parents, _offset, \
236 _mux_shift, _mux_mask, _clk_num, \
237 _gate_flags, _clk_id, _lock) \
238 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
239 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
240 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
241 _clk_id, _parents##_idx, 0, _lock)
242
243#define GATE(_name, _parent_name, \
244 _clk_num, _gate_flags, _clk_id, _flags) \
245 { \
246 .name = _name, \
247 .clk_id = _clk_id, \
248 .p.parent_name = _parent_name, \
249 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
250 _clk_num, _gate_flags, NULL, NULL), \
251 .flags = _flags \
252 }
253
254#define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \
255 { \
256 .name = _name, \
257 .clk_id = _clk_id, \
258 .p.parent_name = _parent_name, \
259 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \
260 TEGRA_DIVIDER_ROUND_UP, 0, 0, \
261 NULL, NULL), \
262 .offset = _offset, \
263 .flags = _flags, \
264 }
265
266#define PLLP_BASE 0xa0
267#define PLLP_MISC 0xac
268#define PLLP_MISC1 0x680
269#define PLLP_OUTA 0xa4
270#define PLLP_OUTB 0xa8
271#define PLLP_OUTC 0x67c
272
273#define PLL_BASE_LOCK BIT(27)
274#define PLL_MISC_LOCK_ENABLE 18
275
276static DEFINE_SPINLOCK(PLLP_OUTA_lock);
277static DEFINE_SPINLOCK(PLLP_OUTB_lock);
278static DEFINE_SPINLOCK(PLLP_OUTC_lock);
279static DEFINE_SPINLOCK(sor0_lock);
280
281#define MUX_I2S_SPDIF(_id) \
282static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
283 #_id, "pll_p",\
284 "clk_m"};
285MUX_I2S_SPDIF(audio0)
286MUX_I2S_SPDIF(audio1)
287MUX_I2S_SPDIF(audio2)
288MUX_I2S_SPDIF(audio3)
289MUX_I2S_SPDIF(audio4)
290MUX_I2S_SPDIF(audio)
291
292#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
293#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
294#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
295#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
296#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
297#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
298
299static const char *mux_pllp_pllc_pllm_clkm[] = {
300 "pll_p", "pll_c", "pll_m", "clk_m"
301};
302#define mux_pllp_pllc_pllm_clkm_idx NULL
303
304static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
305#define mux_pllp_pllc_pllm_idx NULL
306
307static const char *mux_pllp_pllc_clk32_clkm[] = {
308 "pll_p", "pll_c", "clk_32k", "clk_m"
309};
310#define mux_pllp_pllc_clk32_clkm_idx NULL
311
312static const char *mux_plla_pllc_pllp_clkm[] = {
313 "pll_a_out0", "pll_c", "pll_p", "clk_m"
314};
315#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
316
317static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
318 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
319};
320static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
321 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
322};
323
324static const char *mux_pllp_clkm[] = {
325 "pll_p", "clk_m"
326};
327static u32 mux_pllp_clkm_idx[] = {
328 [0] = 0, [1] = 3,
329};
330
331static const char *mux_pllp_clkm_2[] = {
332 "pll_p", "clk_m"
333};
334static u32 mux_pllp_clkm_2_idx[] = {
335 [0] = 2, [1] = 6,
336};
337
338static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
339 "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
340};
341static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
342 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
343};
344
345static const char *
346mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
347 "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
348 "pll_a_out0", "pll_c4_out0"
349};
350static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
351 [0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
352};
353
354static const char *mux_pllc_pllp_plla[] = {
355 "pll_c", "pll_p", "pll_a_out0"
356};
357static u32 mux_pllc_pllp_plla_idx[] = {
358 [0] = 1, [1] = 2, [2] = 3,
359};
360
361static const char *mux_clkm_pllc_pllp_plla[] = {
362 "clk_m", "pll_c", "pll_p", "pll_a_out0"
363};
364#define mux_clkm_pllc_pllp_plla_idx NULL
365
366static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
367 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
368};
369static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
370 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
371};
372
373static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
374 "pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
375};
376static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
377 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
378};
379
380static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
381 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
382};
383#define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
384 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
385
386static const char *
387mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
388 "pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
389 "pll_c4_out2", "clk_m"
390};
391#define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
392
393static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
394 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
395};
396#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
397
398static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
399 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
400 "pll_d2_out0", "clk_m"
401};
402#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
403
404static const char *mux_pllm_pllc_pllp_plla[] = {
405 "pll_m", "pll_c", "pll_p", "pll_a_out0"
406};
407#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
408
409static const char *mux_pllp_pllc_clkm[] = {
410 "pll_p", "pll_c", "clk_m"
411};
412static u32 mux_pllp_pllc_clkm_idx[] = {
413 [0] = 0, [1] = 1, [2] = 3,
414};
415
416static const char *mux_pllp_pllc_clkm_1[] = {
417 "pll_p", "pll_c", "clk_m"
418};
419static u32 mux_pllp_pllc_clkm_1_idx[] = {
420 [0] = 0, [1] = 2, [2] = 5,
421};
422
423static const char *mux_pllp_pllc_plla_clkm[] = {
424 "pll_p", "pll_c", "pll_a_out0", "clk_m"
425};
426static u32 mux_pllp_pllc_plla_clkm_idx[] = {
427 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
428};
429
430static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
431 "pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
432};
433static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
434 [0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
435};
436
437static const char *
438mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
439 "pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
440 "clk_m", "pll_c4_out0"
441};
442static u32
443mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
444 [0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
445};
446
447static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
448 "pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
449};
450static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
451 [0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
452};
453
454static const char *mux_pllp_pllc2_c_c3_clkm[] = {
455 "pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
456};
457static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
458 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
459};
460
461static const char *mux_pllp_clkm_clk32_plle[] = {
462 "pll_p", "clk_m", "clk_32k", "pll_e"
463};
464static u32 mux_pllp_clkm_clk32_plle_idx[] = {
465 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
466};
467
468static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
469 "pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
470};
471#define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
472
473static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
474 "pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
475 "pll_c4_out2"
476};
477static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
478 [0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
479};
480
481static const char *mux_clkm_pllp_pllre[] = {
482 "clk_m", "pll_p_out_xusb", "pll_re_out"
483};
484static u32 mux_clkm_pllp_pllre_idx[] = {
485 [0] = 0, [1] = 1, [2] = 5,
486};
487
488static const char *mux_pllp_pllc_clkm_clk32[] = {
489 "pll_p", "pll_c", "clk_m", "clk_32k"
490};
491#define mux_pllp_pllc_clkm_clk32_idx NULL
492
493static const char *mux_plla_clk32_pllp_clkm_plle[] = {
494 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
495};
496#define mux_plla_clk32_pllp_clkm_plle_idx NULL
497
498static const char *mux_clkm_pllp_pllc_pllre[] = {
499 "clk_m", "pll_p", "pll_c", "pll_re_out"
500};
501static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
502 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
503};
504
505static const char *mux_clkm_48M_pllp_480M[] = {
506 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
507};
508static u32 mux_clkm_48M_pllp_480M_idx[] = {
509 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
510};
511
512static const char *mux_clkm_pllre_clk32_480M[] = {
513 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
514};
515#define mux_clkm_pllre_clk32_480M_idx NULL
516
517static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
518 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
519};
520static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
521 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
522};
523
524static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
525 "pll_p_out3", "pll_p", "pll_c", "clk_m"
526};
527static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
528 [0] = 0, [1] = 1, [2] = 2, [3] = 6,
529};
530
531static const char *mux_ss_div2_60M[] = {
532 "xusb_ss_div2", "pll_u_60M"
533};
534#define mux_ss_div2_60M_idx NULL
535
536static const char *mux_ss_div2_60M_ss[] = {
537 "xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
538};
539#define mux_ss_div2_60M_ss_idx NULL
540
541static const char *mux_ss_clkm[] = {
542 "xusb_ss_src", "clk_m"
543};
544#define mux_ss_clkm_idx NULL
545
546static const char *mux_d_audio_clk[] = {
547 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
548 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
549};
550static u32 mux_d_audio_clk_idx[] = {
551 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
552 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
553};
554
555static const char *mux_pllp_plld_pllc_clkm[] = {
556 "pll_p", "pll_d_out0", "pll_c", "clk_m"
557};
558#define mux_pllp_plld_pllc_clkm_idx NULL
559static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
560 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
561};
562static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
563 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
564};
565
566static const char *mux_pllp_clkm1[] = {
567 "pll_p", "clk_m",
568};
569#define mux_pllp_clkm1_idx NULL
570
571static const char *mux_pllp3_pllc_clkm[] = {
572 "pll_p_out3", "pll_c", "pll_c2", "clk_m",
573};
574#define mux_pllp3_pllc_clkm_idx NULL
575
576static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
577 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
578};
579#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
580
581static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
582 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
583};
584static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
585 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
586};
587
588/* SOR1 mux'es */
589static const char *mux_pllp_plld_plld2_clkm[] = {
590 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
591};
592static u32 mux_pllp_plld_plld2_clkm_idx[] = {
593 [0] = 0, [1] = 2, [2] = 5, [3] = 6
594};
595
596static const char *mux_pllp_pllre_clkm[] = {
597 "pll_p", "pll_re_out1", "clk_m"
598};
599
600static u32 mux_pllp_pllre_clkm_idx[] = {
601 [0] = 0, [1] = 2, [2] = 3,
602};
603
604static const char *mux_clkm_plldp_sor0lvds[] = {
605 "clk_m", "pll_dp", "sor0_lvds",
606};
607#define mux_clkm_plldp_sor0lvds_idx NULL
608
609static const char * const mux_dmic1[] = {
610 "pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m"
611};
612#define mux_dmic1_idx NULL
613
614static const char * const mux_dmic2[] = {
615 "pll_a_out0", "dmic2_sync_clk", "pll_p", "clk_m"
616};
617#define mux_dmic2_idx NULL
618
619static const char * const mux_dmic3[] = {
620 "pll_a_out0", "dmic3_sync_clk", "pll_p", "clk_m"
621};
622#define mux_dmic3_idx NULL
623
624static struct tegra_periph_init_data periph_clks[] = {
625 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
626 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
627 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
628 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
629 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
630 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
631 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
632 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
633 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
634 I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
635 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
636 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
637 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
638 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
639 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
640 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
641 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
642 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
643 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
644 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
645 INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
646 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
647 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
648 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
649 INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
650 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
651 INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
652 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
653 INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
654 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
655 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
656 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
657 INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
658 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
659 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
660 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
661 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
662 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
663 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
664 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
665 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
666 MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
667 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
668 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
669 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
670 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
671 MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
672 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
673 MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
674 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
675 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
676 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
677 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
678 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
679 MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
680 MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
681 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
682 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
683 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
684 MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
685 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
686 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
687 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
688 MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
689 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
690 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
691 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
692 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
693 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
694 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
695 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
696 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
697 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
698 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
699 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
700 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
701 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
702 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
703 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
704 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
705 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
706 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
707 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
708 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
709 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
710 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
711 MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
712 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
713 MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
714 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
715 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
716 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
717 MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
718 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
719 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
720 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
721 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
722 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
723 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
724 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
725 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
726 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
727 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
728 MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
729 MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
730 MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
731 MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
732 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
733 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
734 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
735 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
736 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
737 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
738 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
739 MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
740 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
741 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
742 MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9),
743 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
744 MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
745 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
746 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
747 MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
748 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
749 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
750 MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
751 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
752 NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
753 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
754 NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
755 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
756 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
757 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
758 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
759 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
760 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
761 UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
762 UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
763 UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
764 UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
765 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
766 XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
767 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
768 XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
769 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
770 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
771 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
772 NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
773 NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
774 NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
775 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
776 XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
777 MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
778 MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
779 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
780 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
781 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
782 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
783 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
784 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
785 MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
786 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
787 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
788 MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
789 MUX8("dmic1", mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1),
790 MUX8("dmic2", mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2),
791 MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3),
792};
793
794static struct tegra_periph_init_data gate_clks[] = {
795 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
796 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
797 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
798 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
799 GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
800 GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
801 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
802 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
803 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
804 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
805 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
806 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
807 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
808 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
809 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
810 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
811 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
812 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
813 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
814 GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
815 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
816 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
817 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
818 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
819 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
820 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
821 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
822 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
823 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
824 GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
825 GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
826 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
827 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
828 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
829 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
830 GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
831 GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
832 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
833 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
834 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
835 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
836 GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
837 GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
838 GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
839 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
840 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
841 GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
842 GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
843};
844
845static struct tegra_periph_init_data div_clks[] = {
846 DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
847};
848
849struct pll_out_data {
850 char *div_name;
851 char *pll_out_name;
852 u32 offset;
853 int clk_id;
854 u8 div_shift;
855 u8 div_flags;
856 u8 rst_shift;
857 spinlock_t *lock;
858};
859
860#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
861 {\
862 .div_name = "pll_p_out" #_num "_div",\
863 .pll_out_name = "pll_p_out" #_num,\
864 .offset = _offset,\
865 .div_shift = _div_shift,\
866 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
867 TEGRA_DIVIDER_ROUND_UP,\
868 .rst_shift = _rst_shift,\
869 .clk_id = tegra_clk_ ## _id,\
870 .lock = &_offset ##_lock,\
871 }
872
873static struct pll_out_data pllp_out_clks[] = {
874 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
875 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
876 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
877 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
878 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
879 PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
880};
881
882static void __init periph_clk_init(void __iomem *clk_base,
883 struct tegra_clk *tegra_clks)
884{
885 int i;
886 struct clk *clk;
887 struct clk **dt_clk;
888
889 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
890 const struct tegra_clk_periph_regs *bank;
891 struct tegra_periph_init_data *data;
892
893 data = periph_clks + i;
894
895 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
896 if (!dt_clk)
897 continue;
898
899 bank = get_reg_bank(data->periph.gate.clk_num);
900 if (!bank)
901 continue;
902
903 data->periph.gate.regs = bank;
904 clk = tegra_clk_register_periph_data(clk_base, data);
905 *dt_clk = clk;
906 }
907}
908
909static void __init gate_clk_init(void __iomem *clk_base,
910 struct tegra_clk *tegra_clks)
911{
912 int i;
913 struct clk *clk;
914 struct clk **dt_clk;
915
916 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
917 struct tegra_periph_init_data *data;
918
919 data = gate_clks + i;
920
921 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
922 if (!dt_clk)
923 continue;
924
925 clk = tegra_clk_register_periph_gate(data->name,
926 data->p.parent_name, data->periph.gate.flags,
927 clk_base, data->flags,
928 data->periph.gate.clk_num,
929 periph_clk_enb_refcnt);
930 *dt_clk = clk;
931 }
932}
933
934static void __init div_clk_init(void __iomem *clk_base,
935 struct tegra_clk *tegra_clks)
936{
937 int i;
938 struct clk *clk;
939 struct clk **dt_clk;
940
941 for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
942 struct tegra_periph_init_data *data;
943
944 data = div_clks + i;
945
946 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
947 if (!dt_clk)
948 continue;
949
950 clk = tegra_clk_register_divider(data->name,
951 data->p.parent_name, clk_base + data->offset,
952 data->flags, data->periph.divider.flags,
953 data->periph.divider.shift,
954 data->periph.divider.width,
955 data->periph.divider.frac_width,
956 data->periph.divider.lock);
957 *dt_clk = clk;
958 }
959}
960
961static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
962 struct tegra_clk *tegra_clks,
963 struct tegra_clk_pll_params *pll_params)
964{
965 struct clk *clk;
966 struct clk **dt_clk;
967 int i;
968
969 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
970 if (dt_clk) {
971 /* PLLP */
972 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
973 pmc_base, 0, pll_params, NULL);
974 clk_register_clkdev(clk, "pll_p", NULL);
975 *dt_clk = clk;
976 }
977
978 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
979 struct pll_out_data *data;
980
981 data = pllp_out_clks + i;
982
983 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
984 if (!dt_clk)
985 continue;
986
987 clk = tegra_clk_register_divider(data->div_name, "pll_p",
988 clk_base + data->offset, 0, data->div_flags,
989 data->div_shift, 8, 1, data->lock);
990 clk = tegra_clk_register_pll_out(data->pll_out_name,
991 data->div_name, clk_base + data->offset,
992 data->rst_shift + 1, data->rst_shift,
993 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
994 data->lock);
995 *dt_clk = clk;
996 }
997
998 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
999 tegra_clks);
1000 if (dt_clk) {
1001 /*
1002 * Tegra210 has control on enabling/disabling PLLP branches to
1003 * CPU, register a gate clock "pll_p_out_cpu" for this gating
1004 * function and parent "pll_p_out4" to it, so when we are
1005 * re-parenting CPU off from "pll_p_out4" the PLLP branching to
1006 * CPU can be disabled automatically.
1007 */
1008 clk = tegra_clk_register_divider("pll_p_out4_div",
1009 "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
1010 8, 1, &PLLP_OUTB_lock);
1011
1012 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
1013 if (dt_clk) {
1014 clk = tegra_clk_register_pll_out("pll_p_out4",
1015 "pll_p_out4_div", clk_base + PLLP_OUTB,
1016 17, 16, CLK_IGNORE_UNUSED |
1017 CLK_SET_RATE_PARENT, 0,
1018 &PLLP_OUTB_lock);
1019 *dt_clk = clk;
1020 }
1021 }
1022
1023 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
1024 if (dt_clk) {
1025 /* PLLP_OUT_HSIO */
1026 clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
1027 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1028 clk_base + PLLP_MISC1, 29, 0, NULL);
1029 *dt_clk = clk;
1030 }
1031
1032 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
1033 if (dt_clk) {
1034 /* PLLP_OUT_XUSB */
1035 clk = clk_register_gate(NULL, "pll_p_out_xusb",
1036 "pll_p_out_hsio", CLK_SET_RATE_PARENT |
1037 CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
1038 NULL);
1039 clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
1040 *dt_clk = clk;
1041 }
1042}
1043
1044void __init tegra_periph_clk_init(void __iomem *clk_base,
1045 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
1046 struct tegra_clk_pll_params *pll_params)
1047{
1048 init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
1049 periph_clk_init(clk_base, tegra_clks);
1050 gate_clk_init(clk_base, tegra_clks);
1051 div_clk_init(clk_base, tegra_clks);
1052}