tjh.dev
Linux kernel mirror (for testing)
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linux
1/*
2 * intel-mid.c: Intel MID platform setup code
3 *
4 * (C) Copyright 2008, 2012 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
6 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14#define pr_fmt(fmt) "intel_mid: " fmt
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/regulator/machine.h>
20#include <linux/scatterlist.h>
21#include <linux/sfi.h>
22#include <linux/irq.h>
23#include <linux/export.h>
24#include <linux/notifier.h>
25
26#include <asm/setup.h>
27#include <asm/mpspec_def.h>
28#include <asm/hw_irq.h>
29#include <asm/apic.h>
30#include <asm/io_apic.h>
31#include <asm/intel-mid.h>
32#include <asm/intel_mid_vrtc.h>
33#include <asm/io.h>
34#include <asm/i8259.h>
35#include <asm/intel_scu_ipc.h>
36#include <asm/apb_timer.h>
37#include <asm/reboot.h>
38
39/*
40 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
41 * cmdline option x86_intel_mid_timer can be used to override the configuration
42 * to prefer one or the other.
43 * at runtime, there are basically three timer configurations:
44 * 1. per cpu apbt clock only
45 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
46 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
47 *
48 * by default (without cmdline option), platform code first detects cpu type
49 * to see if we are on lincroft or penwell, then set up both lapic or apbt
50 * clocks accordingly.
51 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
52 * config #3 is supported but not recommended on medfield.
53 *
54 * rating and feature summary:
55 * lapic (with C3STOP) --------- 100
56 * apbt (always-on) ------------ 110
57 * lapic (always-on,ARAT) ------ 150
58 */
59
60enum intel_mid_timer_options intel_mid_timer_options;
61
62enum intel_mid_cpu_type __intel_mid_cpu_chip;
63EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
64
65static void intel_mid_power_off(void)
66{
67 /* Shut down South Complex via PWRMU */
68 intel_mid_pwr_power_off();
69
70 /* Only for Tangier, the rest will ignore this command */
71 intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);
72};
73
74static void intel_mid_reboot(void)
75{
76 intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
77}
78
79static void __init intel_mid_setup_bp_timer(void)
80{
81 apbt_time_init();
82 setup_boot_APIC_clock();
83}
84
85static void __init intel_mid_time_init(void)
86{
87 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
88
89 switch (intel_mid_timer_options) {
90 case INTEL_MID_TIMER_APBT_ONLY:
91 break;
92 case INTEL_MID_TIMER_LAPIC_APBT:
93 /* Use apbt and local apic */
94 x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer;
95 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
96 return;
97 default:
98 if (!boot_cpu_has(X86_FEATURE_ARAT))
99 break;
100 /* Lapic only, no apbt */
101 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
102 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
103 return;
104 }
105
106 x86_init.timers.setup_percpu_clockev = apbt_time_init;
107}
108
109static void intel_mid_arch_setup(void)
110{
111 if (boot_cpu_data.x86 != 6) {
112 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
113 boot_cpu_data.x86, boot_cpu_data.x86_model);
114 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
115 goto out;
116 }
117
118 switch (boot_cpu_data.x86_model) {
119 case 0x35:
120 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
121 break;
122 case 0x3C:
123 case 0x4A:
124 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
125 x86_platform.legacy.rtc = 1;
126 break;
127 case 0x27:
128 default:
129 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
130 break;
131 }
132
133out:
134 /*
135 * Intel MID platforms are using explicitly defined regulators.
136 *
137 * Let the regulator core know that we do not have any additional
138 * regulators left. This lets it substitute unprovided regulators with
139 * dummy ones:
140 */
141 regulator_has_full_constraints();
142}
143
144/*
145 * Moorestown does not have external NMI source nor port 0x61 to report
146 * NMI status. The possible NMI sources are from pmu as a result of NMI
147 * watchdog or lock debug. Reading io port 0x61 results in 0xff which
148 * misled NMI handler.
149 */
150static unsigned char intel_mid_get_nmi_reason(void)
151{
152 return 0;
153}
154
155/*
156 * Moorestown specific x86_init function overrides and early setup
157 * calls.
158 */
159void __init x86_intel_mid_early_setup(void)
160{
161 x86_init.resources.probe_roms = x86_init_noop;
162 x86_init.resources.reserve_resources = x86_init_noop;
163
164 x86_init.timers.timer_init = intel_mid_time_init;
165 x86_init.timers.setup_percpu_clockev = x86_init_noop;
166 x86_init.timers.wallclock_init = intel_mid_rtc_init;
167
168 x86_init.irqs.pre_vector_init = x86_init_noop;
169
170 x86_init.oem.arch_setup = intel_mid_arch_setup;
171
172 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
173
174 x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
175
176 x86_init.pci.arch_init = intel_mid_pci_init;
177 x86_init.pci.fixup_irqs = x86_init_noop;
178
179 legacy_pic = &null_legacy_pic;
180
181 /*
182 * Do nothing for now as everything needed done in
183 * x86_intel_mid_early_setup() below.
184 */
185 x86_init.acpi.reduced_hw_early_init = x86_init_noop;
186
187 pm_power_off = intel_mid_power_off;
188 machine_ops.emergency_restart = intel_mid_reboot;
189
190 /* Avoid searching for BIOS MP tables */
191 x86_init.mpparse.find_smp_config = x86_init_noop;
192 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
193 set_bit(MP_BUS_ISA, mp_bus_not_pci);
194}
195
196/*
197 * if user does not want to use per CPU apb timer, just give it a lower rating
198 * than local apic timer and skip the late per cpu timer init.
199 */
200static inline int __init setup_x86_intel_mid_timer(char *arg)
201{
202 if (!arg)
203 return -EINVAL;
204
205 if (strcmp("apbt_only", arg) == 0)
206 intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY;
207 else if (strcmp("lapic_and_apbt", arg) == 0)
208 intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
209 else {
210 pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
211 arg);
212 return -EINVAL;
213 }
214 return 0;
215}
216__setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);