Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _PARISC_PGTABLE_H
3#define _PARISC_PGTABLE_H
4
5#include <asm-generic/4level-fixup.h>
6
7#include <asm/fixmap.h>
8
9#ifndef __ASSEMBLY__
10/*
11 * we simulate an x86-style page table for the linux mm code
12 */
13
14#include <linux/bitops.h>
15#include <linux/spinlock.h>
16#include <linux/mm_types.h>
17#include <asm/processor.h>
18#include <asm/cache.h>
19
20extern spinlock_t pa_tlb_lock;
21
22/*
23 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
24 * memory. For the return value to be meaningful, ADDR must be >=
25 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
26 * require a hash-, or multi-level tree-lookup or something of that
27 * sort) but it guarantees to return TRUE only if accessing the page
28 * at that address does not cause an error. Note that there may be
29 * addresses for which kern_addr_valid() returns FALSE even though an
30 * access would not cause an error (e.g., this is typically true for
31 * memory mapped I/O regions.
32 *
33 * XXX Need to implement this for parisc.
34 */
35#define kern_addr_valid(addr) (1)
36
37/* Purge data and instruction TLB entries. Must be called holding
38 * the pa_tlb_lock. The TLB purge instructions are slow on SMP
39 * machines since the purge must be broadcast to all CPUs.
40 */
41
42static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
43{
44 mtsp(mm->context, 1);
45 pdtlb(addr);
46 pitlb(addr);
47}
48
49/* Certain architectures need to do special things when PTEs
50 * within a page table are directly modified. Thus, the following
51 * hook is made available.
52 */
53#define set_pte(pteptr, pteval) \
54 do{ \
55 *(pteptr) = (pteval); \
56 } while(0)
57
58#define set_pte_at(mm, addr, ptep, pteval) \
59 do { \
60 pte_t old_pte; \
61 unsigned long flags; \
62 spin_lock_irqsave(&pa_tlb_lock, flags); \
63 old_pte = *ptep; \
64 set_pte(ptep, pteval); \
65 purge_tlb_entries(mm, addr); \
66 spin_unlock_irqrestore(&pa_tlb_lock, flags); \
67 } while (0)
68
69#endif /* !__ASSEMBLY__ */
70
71#include <asm/page.h>
72
73#define pte_ERROR(e) \
74 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
75#define pmd_ERROR(e) \
76 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
77#define pgd_ERROR(e) \
78 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
79
80/* This is the size of the initially mapped kernel memory */
81#if defined(CONFIG_64BIT)
82#define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */
83#else
84#define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */
85#endif
86#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
87
88#if CONFIG_PGTABLE_LEVELS == 3
89#define PGD_ORDER 1 /* Number of pages per pgd */
90#define PMD_ORDER 1 /* Number of pages per pmd */
91#define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
92#else
93#define PGD_ORDER 1 /* Number of pages per pgd */
94#define PGD_ALLOC_ORDER PGD_ORDER
95#endif
96
97/* Definitions for 3rd level (we use PLD here for Page Lower directory
98 * because PTE_SHIFT is used lower down to mean shift that has to be
99 * done to get usable bits out of the PTE) */
100#define PLD_SHIFT PAGE_SHIFT
101#define PLD_SIZE PAGE_SIZE
102#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
103#define PTRS_PER_PTE (1UL << BITS_PER_PTE)
104
105/* Definitions for 2nd level */
106#define pgtable_cache_init() do { } while (0)
107
108#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
109#define PMD_SIZE (1UL << PMD_SHIFT)
110#define PMD_MASK (~(PMD_SIZE-1))
111#if CONFIG_PGTABLE_LEVELS == 3
112#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
113#else
114#define __PAGETABLE_PMD_FOLDED 1
115#define BITS_PER_PMD 0
116#endif
117#define PTRS_PER_PMD (1UL << BITS_PER_PMD)
118
119/* Definitions for 1st level */
120#define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD)
121#if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
122#define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
123#else
124#define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
125#endif
126#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
127#define PGDIR_MASK (~(PGDIR_SIZE-1))
128#define PTRS_PER_PGD (1UL << BITS_PER_PGD)
129#define USER_PTRS_PER_PGD PTRS_PER_PGD
130
131#ifdef CONFIG_64BIT
132#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
133#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
134#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
135#else
136#define MAX_ADDRBITS (BITS_PER_LONG)
137#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
138#define SPACEID_SHIFT 0
139#endif
140
141/* This calculates the number of initial pages we need for the initial
142 * page tables */
143#if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
144# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
145#else
146# define PT_INITIAL (1) /* all initial PTEs fit into one page */
147#endif
148
149/*
150 * pgd entries used up by user/kernel:
151 */
152
153#define FIRST_USER_ADDRESS 0UL
154
155/* NB: The tlb miss handlers make certain assumptions about the order */
156/* of the following bits, so be careful (One example, bits 25-31 */
157/* are moved together in one instruction). */
158
159#define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
160#define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
161#define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
162#define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
163#define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
164#define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
165#define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
166#define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
167#define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
168#define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
169#define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */
170#define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
171
172/* N.B. The bits are defined in terms of a 32 bit word above, so the */
173/* following macro is ok for both 32 and 64 bit. */
174
175#define xlate_pabit(x) (31 - x)
176
177/* this defines the shift to the usable bits in the PTE it is set so
178 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
179 * to zero */
180#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
181
182/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
183#define PFN_PTE_SHIFT 12
184
185#define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
186#define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
187#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
188#define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
189#define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
190#define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
191#define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
192#define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
193#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
194#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
195#define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
196#define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT))
197#define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
198
199#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
200#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
201#define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
202#define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
203#define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
204#define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
205
206/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
207 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
208 * for a few meta-information bits, so we shift the address to be
209 * able to effectively address 40/42/44-bits of physical address space
210 * depending on 4k/16k/64k PAGE_SIZE */
211#define _PxD_PRESENT_BIT 31
212#define _PxD_ATTACHED_BIT 30
213#define _PxD_VALID_BIT 29
214
215#define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
216#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
217#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
218#define PxD_FLAG_MASK (0xf)
219#define PxD_FLAG_SHIFT (4)
220#define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT)
221
222#ifndef __ASSEMBLY__
223
224#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER)
225#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE)
226/* Others seem to make this executable, I don't know if that's correct
227 or not. The stack is mapped this way though so this is necessary
228 in the short term - dhd@linuxcare.com, 2000-08-08 */
229#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ)
230#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE)
231#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC)
232#define PAGE_COPY PAGE_EXECREAD
233#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
234#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
235#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
236#define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
237#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
238#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
239#define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ)
240
241
242/*
243 * We could have an execute only page using "gateway - promote to priv
244 * level 3", but that is kind of silly. So, the way things are defined
245 * now, we must always have read permission for pages with execute
246 * permission. For the fun of it we'll go ahead and support write only
247 * pages.
248 */
249
250 /*xwr*/
251#define __P000 PAGE_NONE
252#define __P001 PAGE_READONLY
253#define __P010 __P000 /* copy on write */
254#define __P011 __P001 /* copy on write */
255#define __P100 PAGE_EXECREAD
256#define __P101 PAGE_EXECREAD
257#define __P110 __P100 /* copy on write */
258#define __P111 __P101 /* copy on write */
259
260#define __S000 PAGE_NONE
261#define __S001 PAGE_READONLY
262#define __S010 PAGE_WRITEONLY
263#define __S011 PAGE_SHARED
264#define __S100 PAGE_EXECREAD
265#define __S101 PAGE_EXECREAD
266#define __S110 PAGE_RWX
267#define __S111 PAGE_RWX
268
269
270extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
271
272/* initial page tables for 0-8MB for kernel */
273
274extern pte_t pg0[];
275
276/* zero page used for uninitialized stuff */
277
278extern unsigned long *empty_zero_page;
279
280/*
281 * ZERO_PAGE is a global shared page that is always zero: used
282 * for zero-mapped memory areas etc..
283 */
284
285#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
286
287#define pte_none(x) (pte_val(x) == 0)
288#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
289#define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0))
290
291#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
292#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
293#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
294#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
295
296#if CONFIG_PGTABLE_LEVELS == 3
297/* The first entry of the permanent pmd is not there if it contains
298 * the gateway marker */
299#define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
300#else
301#define pmd_none(x) (!pmd_val(x))
302#endif
303#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
304#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
305static inline void pmd_clear(pmd_t *pmd) {
306#if CONFIG_PGTABLE_LEVELS == 3
307 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
308 /* This is the entry pointing to the permanent pmd
309 * attached to the pgd; cannot clear it */
310 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
311 else
312#endif
313 __pmd_val_set(*pmd, 0);
314}
315
316
317
318#if CONFIG_PGTABLE_LEVELS == 3
319#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd)))
320#define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd))
321
322/* For 64 bit we have three level tables */
323
324#define pgd_none(x) (!pgd_val(x))
325#define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
326#define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
327static inline void pgd_clear(pgd_t *pgd) {
328#if CONFIG_PGTABLE_LEVELS == 3
329 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
330 /* This is the permanent pmd attached to the pgd; cannot
331 * free it */
332 return;
333#endif
334 __pgd_val_set(*pgd, 0);
335}
336#else
337/*
338 * The "pgd_xxx()" functions here are trivial for a folded two-level
339 * setup: the pgd is never bad, and a pmd always exists (as it's folded
340 * into the pgd entry)
341 */
342static inline int pgd_none(pgd_t pgd) { return 0; }
343static inline int pgd_bad(pgd_t pgd) { return 0; }
344static inline int pgd_present(pgd_t pgd) { return 1; }
345static inline void pgd_clear(pgd_t * pgdp) { }
346#endif
347
348/*
349 * The following only work if pte_present() is true.
350 * Undefined behaviour if not..
351 */
352static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
353static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
354static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
355static inline int pte_special(pte_t pte) { return 0; }
356
357static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
358static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
359static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
360static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
361static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
362static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
363static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
364
365/*
366 * Huge pte definitions.
367 */
368#ifdef CONFIG_HUGETLB_PAGE
369#define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE)
370#define pte_mkhuge(pte) (__pte(pte_val(pte) | \
371 (parisc_requires_coherency() ? 0 : _PAGE_HUGE)))
372#else
373#define pte_huge(pte) (0)
374#define pte_mkhuge(pte) (pte)
375#endif
376
377
378/*
379 * Conversion functions: convert a page and protection to a page entry,
380 * and a page entry and page directory to the page they refer to.
381 */
382#define __mk_pte(addr,pgprot) \
383({ \
384 pte_t __pte; \
385 \
386 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
387 \
388 __pte; \
389})
390
391#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
392
393static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
394{
395 pte_t pte;
396 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
397 return pte;
398}
399
400static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
401{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
402
403/* Permanent address of a page. On parisc we don't have highmem. */
404
405#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
406
407#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
408
409#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd)))
410
411#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
412#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
413
414#define pgd_index(address) ((address) >> PGDIR_SHIFT)
415
416/* to find an entry in a page-table-directory */
417#define pgd_offset(mm, address) \
418((mm)->pgd + ((address) >> PGDIR_SHIFT))
419
420/* to find an entry in a kernel page-table-directory */
421#define pgd_offset_k(address) pgd_offset(&init_mm, address)
422
423/* Find an entry in the second-level page table.. */
424
425#if CONFIG_PGTABLE_LEVELS == 3
426#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
427#define pmd_offset(dir,address) \
428((pmd_t *) pgd_page_vaddr(*(dir)) + pmd_index(address))
429#else
430#define pmd_offset(dir,addr) ((pmd_t *) dir)
431#endif
432
433/* Find an entry in the third-level page table.. */
434#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
435#define pte_offset_kernel(pmd, address) \
436 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
437#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
438#define pte_unmap(pte) do { } while (0)
439
440#define pte_unmap(pte) do { } while (0)
441#define pte_unmap_nested(pte) do { } while (0)
442
443extern void paging_init (void);
444
445/* Used for deferring calls to flush_dcache_page() */
446
447#define PG_dcache_dirty PG_arch_1
448
449extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
450
451/* Encode and de-code a swap entry */
452
453#define __swp_type(x) ((x).val & 0x1f)
454#define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
455 (((x).val >> 8) & ~0x7) )
456#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
457 ((offset & 0x7) << 6) | \
458 ((offset & ~0x7) << 8) })
459#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
460#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
461
462static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
463{
464 pte_t pte;
465 unsigned long flags;
466
467 if (!pte_young(*ptep))
468 return 0;
469
470 spin_lock_irqsave(&pa_tlb_lock, flags);
471 pte = *ptep;
472 if (!pte_young(pte)) {
473 spin_unlock_irqrestore(&pa_tlb_lock, flags);
474 return 0;
475 }
476 set_pte(ptep, pte_mkold(pte));
477 purge_tlb_entries(vma->vm_mm, addr);
478 spin_unlock_irqrestore(&pa_tlb_lock, flags);
479 return 1;
480}
481
482struct mm_struct;
483static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
484{
485 pte_t old_pte;
486 unsigned long flags;
487
488 spin_lock_irqsave(&pa_tlb_lock, flags);
489 old_pte = *ptep;
490 set_pte(ptep, __pte(0));
491 purge_tlb_entries(mm, addr);
492 spin_unlock_irqrestore(&pa_tlb_lock, flags);
493
494 return old_pte;
495}
496
497static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
498{
499 unsigned long flags;
500 spin_lock_irqsave(&pa_tlb_lock, flags);
501 set_pte(ptep, pte_wrprotect(*ptep));
502 purge_tlb_entries(mm, addr);
503 spin_unlock_irqrestore(&pa_tlb_lock, flags);
504}
505
506#define pte_same(A,B) (pte_val(A) == pte_val(B))
507
508struct seq_file;
509extern void arch_report_meminfo(struct seq_file *m);
510
511#endif /* !__ASSEMBLY__ */
512
513
514/* TLB page size encoding - see table 3-1 in parisc20.pdf */
515#define _PAGE_SIZE_ENCODING_4K 0
516#define _PAGE_SIZE_ENCODING_16K 1
517#define _PAGE_SIZE_ENCODING_64K 2
518#define _PAGE_SIZE_ENCODING_256K 3
519#define _PAGE_SIZE_ENCODING_1M 4
520#define _PAGE_SIZE_ENCODING_4M 5
521#define _PAGE_SIZE_ENCODING_16M 6
522#define _PAGE_SIZE_ENCODING_64M 7
523
524#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
525# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
526#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
527# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
528#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
529# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
530#endif
531
532
533#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
534
535/* We provide our own get_unmapped_area to provide cache coherency */
536
537#define HAVE_ARCH_UNMAPPED_AREA
538#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
539
540#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
541#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
542#define __HAVE_ARCH_PTEP_SET_WRPROTECT
543#define __HAVE_ARCH_PTE_SAME
544#include <asm-generic/pgtable.h>
545
546#endif /* _PARISC_PGTABLE_H */