Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
3 *
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASSEMBLY__
20#error "Only include this from assembly code"
21#endif
22
23#ifndef __ASM_ASSEMBLER_H
24#define __ASM_ASSEMBLER_H
25
26#include <asm/asm-offsets.h>
27#include <asm/cpufeature.h>
28#include <asm/debug-monitors.h>
29#include <asm/page.h>
30#include <asm/pgtable-hwdef.h>
31#include <asm/ptrace.h>
32#include <asm/thread_info.h>
33
34 .macro save_and_disable_daif, flags
35 mrs \flags, daif
36 msr daifset, #0xf
37 .endm
38
39 .macro disable_daif
40 msr daifset, #0xf
41 .endm
42
43 .macro enable_daif
44 msr daifclr, #0xf
45 .endm
46
47 .macro restore_daif, flags:req
48 msr daif, \flags
49 .endm
50
51 /* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */
52 .macro inherit_daif, pstate:req, tmp:req
53 and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
54 msr daif, \tmp
55 .endm
56
57 /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
58 .macro enable_da_f
59 msr daifclr, #(8 | 4 | 1)
60 .endm
61
62/*
63 * Enable and disable interrupts.
64 */
65 .macro disable_irq
66 msr daifset, #2
67 .endm
68
69 .macro enable_irq
70 msr daifclr, #2
71 .endm
72
73 .macro save_and_disable_irq, flags
74 mrs \flags, daif
75 msr daifset, #2
76 .endm
77
78 .macro restore_irq, flags
79 msr daif, \flags
80 .endm
81
82 .macro enable_dbg
83 msr daifclr, #8
84 .endm
85
86 .macro disable_step_tsk, flgs, tmp
87 tbz \flgs, #TIF_SINGLESTEP, 9990f
88 mrs \tmp, mdscr_el1
89 bic \tmp, \tmp, #DBG_MDSCR_SS
90 msr mdscr_el1, \tmp
91 isb // Synchronise with enable_dbg
929990:
93 .endm
94
95 /* call with daif masked */
96 .macro enable_step_tsk, flgs, tmp
97 tbz \flgs, #TIF_SINGLESTEP, 9990f
98 mrs \tmp, mdscr_el1
99 orr \tmp, \tmp, #DBG_MDSCR_SS
100 msr mdscr_el1, \tmp
1019990:
102 .endm
103
104/*
105 * SMP data memory barrier
106 */
107 .macro smp_dmb, opt
108 dmb \opt
109 .endm
110
111/*
112 * RAS Error Synchronization barrier
113 */
114 .macro esb
115 hint #16
116 .endm
117
118/*
119 * Value prediction barrier
120 */
121 .macro csdb
122 hint #20
123 .endm
124
125/*
126 * Sanitise a 64-bit bounded index wrt speculation, returning zero if out
127 * of bounds.
128 */
129 .macro mask_nospec64, idx, limit, tmp
130 sub \tmp, \idx, \limit
131 bic \tmp, \tmp, \idx
132 and \idx, \idx, \tmp, asr #63
133 csdb
134 .endm
135
136/*
137 * NOP sequence
138 */
139 .macro nops, num
140 .rept \num
141 nop
142 .endr
143 .endm
144
145/*
146 * Emit an entry into the exception table
147 */
148 .macro _asm_extable, from, to
149 .pushsection __ex_table, "a"
150 .align 3
151 .long (\from - .), (\to - .)
152 .popsection
153 .endm
154
155#define USER(l, x...) \
1569999: x; \
157 _asm_extable 9999b, l
158
159/*
160 * Register aliases.
161 */
162lr .req x30 // link register
163
164/*
165 * Vector entry
166 */
167 .macro ventry label
168 .align 7
169 b \label
170 .endm
171
172/*
173 * Select code when configured for BE.
174 */
175#ifdef CONFIG_CPU_BIG_ENDIAN
176#define CPU_BE(code...) code
177#else
178#define CPU_BE(code...)
179#endif
180
181/*
182 * Select code when configured for LE.
183 */
184#ifdef CONFIG_CPU_BIG_ENDIAN
185#define CPU_LE(code...)
186#else
187#define CPU_LE(code...) code
188#endif
189
190/*
191 * Define a macro that constructs a 64-bit value by concatenating two
192 * 32-bit registers. Note that on big endian systems the order of the
193 * registers is swapped.
194 */
195#ifndef CONFIG_CPU_BIG_ENDIAN
196 .macro regs_to_64, rd, lbits, hbits
197#else
198 .macro regs_to_64, rd, hbits, lbits
199#endif
200 orr \rd, \lbits, \hbits, lsl #32
201 .endm
202
203/*
204 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
205 * <symbol> is within the range +/- 4 GB of the PC.
206 */
207 /*
208 * @dst: destination register (64 bit wide)
209 * @sym: name of the symbol
210 */
211 .macro adr_l, dst, sym
212 adrp \dst, \sym
213 add \dst, \dst, :lo12:\sym
214 .endm
215
216 /*
217 * @dst: destination register (32 or 64 bit wide)
218 * @sym: name of the symbol
219 * @tmp: optional 64-bit scratch register to be used if <dst> is a
220 * 32-bit wide register, in which case it cannot be used to hold
221 * the address
222 */
223 .macro ldr_l, dst, sym, tmp=
224 .ifb \tmp
225 adrp \dst, \sym
226 ldr \dst, [\dst, :lo12:\sym]
227 .else
228 adrp \tmp, \sym
229 ldr \dst, [\tmp, :lo12:\sym]
230 .endif
231 .endm
232
233 /*
234 * @src: source register (32 or 64 bit wide)
235 * @sym: name of the symbol
236 * @tmp: mandatory 64-bit scratch register to calculate the address
237 * while <src> needs to be preserved.
238 */
239 .macro str_l, src, sym, tmp
240 adrp \tmp, \sym
241 str \src, [\tmp, :lo12:\sym]
242 .endm
243
244 /*
245 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
246 * @sym: The name of the per-cpu variable
247 * @tmp: scratch register
248 */
249 .macro adr_this_cpu, dst, sym, tmp
250 adrp \tmp, \sym
251 add \dst, \tmp, #:lo12:\sym
252alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
253 mrs \tmp, tpidr_el1
254alternative_else
255 mrs \tmp, tpidr_el2
256alternative_endif
257 add \dst, \dst, \tmp
258 .endm
259
260 /*
261 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
262 * @sym: The name of the per-cpu variable
263 * @tmp: scratch register
264 */
265 .macro ldr_this_cpu dst, sym, tmp
266 adr_l \dst, \sym
267alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
268 mrs \tmp, tpidr_el1
269alternative_else
270 mrs \tmp, tpidr_el2
271alternative_endif
272 ldr \dst, [\dst, \tmp]
273 .endm
274
275/*
276 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
277 */
278 .macro vma_vm_mm, rd, rn
279 ldr \rd, [\rn, #VMA_VM_MM]
280 .endm
281
282/*
283 * mmid - get context id from mm pointer (mm->context.id)
284 */
285 .macro mmid, rd, rn
286 ldr \rd, [\rn, #MM_CONTEXT_ID]
287 .endm
288/*
289 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
290 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
291 */
292 .macro read_ctr, reg
293alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
294 mrs \reg, ctr_el0 // read CTR
295 nop
296alternative_else
297 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
298alternative_endif
299 .endm
300
301
302/*
303 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
304 * from the CTR register.
305 */
306 .macro raw_dcache_line_size, reg, tmp
307 mrs \tmp, ctr_el0 // read CTR
308 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
309 mov \reg, #4 // bytes per word
310 lsl \reg, \reg, \tmp // actual cache line size
311 .endm
312
313/*
314 * dcache_line_size - get the safe D-cache line size across all CPUs
315 */
316 .macro dcache_line_size, reg, tmp
317 read_ctr \tmp
318 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
319 mov \reg, #4 // bytes per word
320 lsl \reg, \reg, \tmp // actual cache line size
321 .endm
322
323/*
324 * raw_icache_line_size - get the minimum I-cache line size on this CPU
325 * from the CTR register.
326 */
327 .macro raw_icache_line_size, reg, tmp
328 mrs \tmp, ctr_el0 // read CTR
329 and \tmp, \tmp, #0xf // cache line size encoding
330 mov \reg, #4 // bytes per word
331 lsl \reg, \reg, \tmp // actual cache line size
332 .endm
333
334/*
335 * icache_line_size - get the safe I-cache line size across all CPUs
336 */
337 .macro icache_line_size, reg, tmp
338 read_ctr \tmp
339 and \tmp, \tmp, #0xf // cache line size encoding
340 mov \reg, #4 // bytes per word
341 lsl \reg, \reg, \tmp // actual cache line size
342 .endm
343
344/*
345 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
346 */
347 .macro tcr_set_idmap_t0sz, valreg, tmpreg
348 ldr_l \tmpreg, idmap_t0sz
349 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
350 .endm
351
352/*
353 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
354 * ID_AA64MMFR0_EL1.PARange value
355 *
356 * tcr: register with the TCR_ELx value to be updated
357 * pos: IPS or PS bitfield position
358 * tmp{0,1}: temporary registers
359 */
360 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
361 mrs \tmp0, ID_AA64MMFR0_EL1
362 // Narrow PARange to fit the PS field in TCR_ELx
363 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
364 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
365 cmp \tmp0, \tmp1
366 csel \tmp0, \tmp1, \tmp0, hi
367 bfi \tcr, \tmp0, \pos, #3
368 .endm
369
370/*
371 * Macro to perform a data cache maintenance for the interval
372 * [kaddr, kaddr + size)
373 *
374 * op: operation passed to dc instruction
375 * domain: domain used in dsb instruciton
376 * kaddr: starting virtual address of the region
377 * size: size of the region
378 * Corrupts: kaddr, size, tmp1, tmp2
379 */
380 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
381 dcache_line_size \tmp1, \tmp2
382 add \size, \kaddr, \size
383 sub \tmp2, \tmp1, #1
384 bic \kaddr, \kaddr, \tmp2
3859998:
386 .if (\op == cvau || \op == cvac)
387alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
388 dc \op, \kaddr
389alternative_else
390 dc civac, \kaddr
391alternative_endif
392 .elseif (\op == cvap)
393alternative_if ARM64_HAS_DCPOP
394 sys 3, c7, c12, 1, \kaddr // dc cvap
395alternative_else
396 dc cvac, \kaddr
397alternative_endif
398 .else
399 dc \op, \kaddr
400 .endif
401 add \kaddr, \kaddr, \tmp1
402 cmp \kaddr, \size
403 b.lo 9998b
404 dsb \domain
405 .endm
406
407/*
408 * Macro to perform an instruction cache maintenance for the interval
409 * [start, end)
410 *
411 * start, end: virtual addresses describing the region
412 * label: A label to branch to on user fault.
413 * Corrupts: tmp1, tmp2
414 */
415 .macro invalidate_icache_by_line start, end, tmp1, tmp2, label
416 icache_line_size \tmp1, \tmp2
417 sub \tmp2, \tmp1, #1
418 bic \tmp2, \start, \tmp2
4199997:
420USER(\label, ic ivau, \tmp2) // invalidate I line PoU
421 add \tmp2, \tmp2, \tmp1
422 cmp \tmp2, \end
423 b.lo 9997b
424 dsb ish
425 isb
426 .endm
427
428/*
429 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
430 */
431 .macro reset_pmuserenr_el0, tmpreg
432 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
433 sbfx \tmpreg, \tmpreg, #8, #4
434 cmp \tmpreg, #1 // Skip if no PMU present
435 b.lt 9000f
436 msr pmuserenr_el0, xzr // Disable PMU access from EL0
4379000:
438 .endm
439
440/*
441 * copy_page - copy src to dest using temp registers t1-t8
442 */
443 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
4449998: ldp \t1, \t2, [\src]
445 ldp \t3, \t4, [\src, #16]
446 ldp \t5, \t6, [\src, #32]
447 ldp \t7, \t8, [\src, #48]
448 add \src, \src, #64
449 stnp \t1, \t2, [\dest]
450 stnp \t3, \t4, [\dest, #16]
451 stnp \t5, \t6, [\dest, #32]
452 stnp \t7, \t8, [\dest, #48]
453 add \dest, \dest, #64
454 tst \src, #(PAGE_SIZE - 1)
455 b.ne 9998b
456 .endm
457
458/*
459 * Annotate a function as position independent, i.e., safe to be called before
460 * the kernel virtual mapping is activated.
461 */
462#define ENDPIPROC(x) \
463 .globl __pi_##x; \
464 .type __pi_##x, %function; \
465 .set __pi_##x, x; \
466 .size __pi_##x, . - x; \
467 ENDPROC(x)
468
469/*
470 * Annotate a function as being unsuitable for kprobes.
471 */
472#ifdef CONFIG_KPROBES
473#define NOKPROBE(x) \
474 .pushsection "_kprobe_blacklist", "aw"; \
475 .quad x; \
476 .popsection;
477#else
478#define NOKPROBE(x)
479#endif
480 /*
481 * Emit a 64-bit absolute little endian symbol reference in a way that
482 * ensures that it will be resolved at build time, even when building a
483 * PIE binary. This requires cooperation from the linker script, which
484 * must emit the lo32/hi32 halves individually.
485 */
486 .macro le64sym, sym
487 .long \sym\()_lo32
488 .long \sym\()_hi32
489 .endm
490
491 /*
492 * mov_q - move an immediate constant into a 64-bit register using
493 * between 2 and 4 movz/movk instructions (depending on the
494 * magnitude and sign of the operand)
495 */
496 .macro mov_q, reg, val
497 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
498 movz \reg, :abs_g1_s:\val
499 .else
500 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
501 movz \reg, :abs_g2_s:\val
502 .else
503 movz \reg, :abs_g3:\val
504 movk \reg, :abs_g2_nc:\val
505 .endif
506 movk \reg, :abs_g1_nc:\val
507 .endif
508 movk \reg, :abs_g0_nc:\val
509 .endm
510
511/*
512 * Return the current thread_info.
513 */
514 .macro get_thread_info, rd
515 mrs \rd, sp_el0
516 .endm
517
518/*
519 * Arrange a physical address in a TTBR register, taking care of 52-bit
520 * addresses.
521 *
522 * phys: physical address, preserved
523 * ttbr: returns the TTBR value
524 */
525 .macro phys_to_ttbr, ttbr, phys
526#ifdef CONFIG_ARM64_PA_BITS_52
527 orr \ttbr, \phys, \phys, lsr #46
528 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
529#else
530 mov \ttbr, \phys
531#endif
532 .endm
533
534 .macro phys_to_pte, pte, phys
535#ifdef CONFIG_ARM64_PA_BITS_52
536 /*
537 * We assume \phys is 64K aligned and this is guaranteed by only
538 * supporting this configuration with 64K pages.
539 */
540 orr \pte, \phys, \phys, lsr #36
541 and \pte, \pte, #PTE_ADDR_MASK
542#else
543 mov \pte, \phys
544#endif
545 .endm
546
547 .macro pte_to_phys, phys, pte
548#ifdef CONFIG_ARM64_PA_BITS_52
549 ubfiz \phys, \pte, #(48 - 16 - 12), #16
550 bfxil \phys, \pte, #16, #32
551 lsl \phys, \phys, #16
552#else
553 and \phys, \pte, #PTE_ADDR_MASK
554#endif
555 .endm
556
557/**
558 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
559 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
560 */
561 .macro pre_disable_mmu_workaround
562#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
563 isb
564#endif
565 .endm
566
567 /*
568 * frame_push - Push @regcount callee saved registers to the stack,
569 * starting at x19, as well as x29/x30, and set x29 to
570 * the new value of sp. Add @extra bytes of stack space
571 * for locals.
572 */
573 .macro frame_push, regcount:req, extra
574 __frame st, \regcount, \extra
575 .endm
576
577 /*
578 * frame_pop - Pop the callee saved registers from the stack that were
579 * pushed in the most recent call to frame_push, as well
580 * as x29/x30 and any extra stack space that may have been
581 * allocated.
582 */
583 .macro frame_pop
584 __frame ld
585 .endm
586
587 .macro __frame_regs, reg1, reg2, op, num
588 .if .Lframe_regcount == \num
589 \op\()r \reg1, [sp, #(\num + 1) * 8]
590 .elseif .Lframe_regcount > \num
591 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
592 .endif
593 .endm
594
595 .macro __frame, op, regcount, extra=0
596 .ifc \op, st
597 .if (\regcount) < 0 || (\regcount) > 10
598 .error "regcount should be in the range [0 ... 10]"
599 .endif
600 .if ((\extra) % 16) != 0
601 .error "extra should be a multiple of 16 bytes"
602 .endif
603 .ifdef .Lframe_regcount
604 .if .Lframe_regcount != -1
605 .error "frame_push/frame_pop may not be nested"
606 .endif
607 .endif
608 .set .Lframe_regcount, \regcount
609 .set .Lframe_extra, \extra
610 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
611 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
612 mov x29, sp
613 .endif
614
615 __frame_regs x19, x20, \op, 1
616 __frame_regs x21, x22, \op, 3
617 __frame_regs x23, x24, \op, 5
618 __frame_regs x25, x26, \op, 7
619 __frame_regs x27, x28, \op, 9
620
621 .ifc \op, ld
622 .if .Lframe_regcount == -1
623 .error "frame_push/frame_pop may not be nested"
624 .endif
625 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
626 .set .Lframe_regcount, -1
627 .endif
628 .endm
629
630/*
631 * Check whether to yield to another runnable task from kernel mode NEON code
632 * (which runs with preemption disabled).
633 *
634 * if_will_cond_yield_neon
635 * // pre-yield patchup code
636 * do_cond_yield_neon
637 * // post-yield patchup code
638 * endif_yield_neon <label>
639 *
640 * where <label> is optional, and marks the point where execution will resume
641 * after a yield has been performed. If omitted, execution resumes right after
642 * the endif_yield_neon invocation. Note that the entire sequence, including
643 * the provided patchup code, will be omitted from the image if CONFIG_PREEMPT
644 * is not defined.
645 *
646 * As a convenience, in the case where no patchup code is required, the above
647 * sequence may be abbreviated to
648 *
649 * cond_yield_neon <label>
650 *
651 * Note that the patchup code does not support assembler directives that change
652 * the output section, any use of such directives is undefined.
653 *
654 * The yield itself consists of the following:
655 * - Check whether the preempt count is exactly 1, in which case disabling
656 * preemption once will make the task preemptible. If this is not the case,
657 * yielding is pointless.
658 * - Check whether TIF_NEED_RESCHED is set, and if so, disable and re-enable
659 * kernel mode NEON (which will trigger a reschedule), and branch to the
660 * yield fixup code.
661 *
662 * This macro sequence may clobber all CPU state that is not guaranteed by the
663 * AAPCS to be preserved across an ordinary function call.
664 */
665
666 .macro cond_yield_neon, lbl
667 if_will_cond_yield_neon
668 do_cond_yield_neon
669 endif_yield_neon \lbl
670 .endm
671
672 .macro if_will_cond_yield_neon
673#ifdef CONFIG_PREEMPT
674 get_thread_info x0
675 ldr w1, [x0, #TSK_TI_PREEMPT]
676 ldr x0, [x0, #TSK_TI_FLAGS]
677 cmp w1, #PREEMPT_DISABLE_OFFSET
678 csel x0, x0, xzr, eq
679 tbnz x0, #TIF_NEED_RESCHED, .Lyield_\@ // needs rescheduling?
680 /* fall through to endif_yield_neon */
681 .subsection 1
682.Lyield_\@ :
683#else
684 .section ".discard.cond_yield_neon", "ax"
685#endif
686 .endm
687
688 .macro do_cond_yield_neon
689 bl kernel_neon_end
690 bl kernel_neon_begin
691 .endm
692
693 .macro endif_yield_neon, lbl
694 .ifnb \lbl
695 b \lbl
696 .else
697 b .Lyield_out_\@
698 .endif
699 .previous
700.Lyield_out_\@ :
701 .endm
702
703#endif /* __ASM_ASSEMBLER_H */