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1* Texas Instruments - dp83867 Giga bit ethernet phy
2
3Required properties:
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
6 for applicable values. Required only if interface type is
7 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
8 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
9 for applicable values. Required only if interface type is
10 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
11 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
12 for applicable values
13
14Optional property:
15 - ti,min-output-impedance - MAC Interface Impedance control to set
16 the programmable output impedance to
17 minimum value (35 ohms).
18 - ti,max-output-impedance - MAC Interface Impedance control to set
19 the programmable output impedance to
20 maximum value (70 ohms).
21 - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
22 board has RX_DV/RX_CTRL pin strapped in
23 mode 1 or 2. To ensure PHY operation,
24 there are specific actions that
25 software needs to take when this pin is
26 strapped in these modes. See data manual
27 for details.
28 - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
29 for applicable values.
30
31Note: ti,min-output-impedance and ti,max-output-impedance are mutually
32 exclusive. When both properties are present ti,max-output-impedance
33 takes precedence.
34
35Default child nodes are standard Ethernet PHY device
36nodes as described in Documentation/devicetree/bindings/net/phy.txt
37
38Example:
39
40 ethernet-phy@0 {
41 reg = <0>;
42 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
43 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
44 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
45 };
46
47Datasheet can be found:
48http://www.ti.com/product/DP83867IR/datasheet