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1Renesas R-Car LVDS Encoder
2==========================
3
4These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
5Gen2, R-Car Gen3 and RZ/G SoCs.
6
7Required properties:
8
9- compatible : Shall contain one of
10 - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
11 - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
12 - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
13 - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
14 - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
15 - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
16 - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
17 - "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders
18 - "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders
19 - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
20
21- reg: Base address and length for the memory-mapped registers
22- clocks: A list of phandles + clock-specifier pairs, one for each entry in
23 the clock-names property.
24- clock-names: Name of the clocks. This property is model-dependent.
25 - The functional clock, which mandatory for all models, shall be listed
26 first, and shall be named "fck".
27 - On R8A77990 and R8A77995, the LVDS encoder can use the EXTAL or
28 DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
29 named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
30 numerical index.
31 - When the clocks property only contains the functional clock, the
32 clock-names property may be omitted.
33- resets: A phandle + reset specifier for the module reset
34
35Required nodes:
36
37The LVDS encoder has two video ports. Their connections are modelled using the
38OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
39
40- Video port 0 corresponds to the parallel RGB input
41- Video port 1 corresponds to the LVDS output
42
43Each port shall have a single endpoint.
44
45
46Example:
47
48 lvds0: lvds@feb90000 {
49 compatible = "renesas,r8a7790-lvds";
50 reg = <0 0xfeb90000 0 0x1c>;
51 clocks = <&cpg CPG_MOD 726>;
52 resets = <&cpg 726>;
53
54 ports {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 port@0 {
59 reg = <0>;
60 lvds0_in: endpoint {
61 remote-endpoint = <&du_out_lvds0>;
62 };
63 };
64 port@1 {
65 reg = <1>;
66 lvds0_out: endpoint {
67 };
68 };
69 };
70 };