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1Device Tree Clock bindings for arch-at91
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Slow Clock controller:
8
9Required properties:
10- compatible : shall be one of the following:
11 "atmel,at91sam9x5-sckc" or
12 "atmel,sama5d4-sckc":
13 at91 SCKC (Slow Clock Controller)
14 This node contains the slow clock definitions.
15
16 "atmel,at91sam9x5-clk-slow-osc":
17 at91 slow oscillator
18
19 "atmel,at91sam9x5-clk-slow-rc-osc":
20 at91 internal slow RC oscillator
21- reg : defines the IO memory reserved for the SCKC.
22- #size-cells : shall be 0 (reg is used to encode clk id).
23- #address-cells : shall be 1 (reg is used to encode clk id).
24
25
26For example:
27 sckc: sckc@fffffe50 {
28 compatible = "atmel,sama5d3-pmc";
29 reg = <0xfffffe50 0x4>
30 #size-cells = <0>;
31 #address-cells = <1>;
32
33 /* put at91 slow clocks here */
34 };
35
36Power Management Controller (PMC):
37
38Required properties:
39- compatible : shall be "atmel,<chip>-pmc", "syscon":
40 <chip> can be: at91rm9200, at91sam9260, at91sam9261,
41 at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
42 at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
43 sama5d2, sama5d3 or sama5d4.
44- #clock-cells : from common clock binding; shall be set to 2. The first entry
45 is the type of the clock (core, system, peripheral or generated) and the
46 second entry its index as provided by the datasheet
47- clocks : Must contain an entry for each entry in clock-names.
48- clock-names: Must include the following entries: "slow_clk", "main_xtal"
49
50Optional properties:
51- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
52 provided on XIN.
53
54For example:
55 pmc: pmc@f0018000 {
56 compatible = "atmel,sama5d4-pmc", "syscon";
57 reg = <0xf0018000 0x120>;
58 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
59 #clock-cells = <2>;
60 clocks = <&clk32k>, <&main_xtal>;
61 clock-names = "slow_clk", "main_xtal";
62 };