tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010 OMICRON electronics GmbH
4 * Copyright 2018 NXP
5 */
6#ifndef __PTP_QORIQ_H__
7#define __PTP_QORIQ_H__
8
9#include <linux/io.h>
10#include <linux/ptp_clock_kernel.h>
11
12/*
13 * qoriq ptp registers
14 */
15struct ctrl_regs {
16 u32 tmr_ctrl; /* Timer control register */
17 u32 tmr_tevent; /* Timestamp event register */
18 u32 tmr_temask; /* Timer event mask register */
19 u32 tmr_pevent; /* Timestamp event register */
20 u32 tmr_pemask; /* Timer event mask register */
21 u32 tmr_stat; /* Timestamp status register */
22 u32 tmr_cnt_h; /* Timer counter high register */
23 u32 tmr_cnt_l; /* Timer counter low register */
24 u32 tmr_add; /* Timer drift compensation addend register */
25 u32 tmr_acc; /* Timer accumulator register */
26 u32 tmr_prsc; /* Timer prescale */
27 u8 res1[4];
28 u32 tmroff_h; /* Timer offset high */
29 u32 tmroff_l; /* Timer offset low */
30};
31
32struct alarm_regs {
33 u32 tmr_alarm1_h; /* Timer alarm 1 high register */
34 u32 tmr_alarm1_l; /* Timer alarm 1 high register */
35 u32 tmr_alarm2_h; /* Timer alarm 2 high register */
36 u32 tmr_alarm2_l; /* Timer alarm 2 high register */
37};
38
39struct fiper_regs {
40 u32 tmr_fiper1; /* Timer fixed period interval */
41 u32 tmr_fiper2; /* Timer fixed period interval */
42 u32 tmr_fiper3; /* Timer fixed period interval */
43};
44
45struct etts_regs {
46 u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
47 u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
48 u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
49 u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
50};
51
52struct qoriq_ptp_registers {
53 struct ctrl_regs __iomem *ctrl_regs;
54 struct alarm_regs __iomem *alarm_regs;
55 struct fiper_regs __iomem *fiper_regs;
56 struct etts_regs __iomem *etts_regs;
57};
58
59/* Offset definitions for the four register groups */
60#define CTRL_REGS_OFFSET 0x0
61#define ALARM_REGS_OFFSET 0x40
62#define FIPER_REGS_OFFSET 0x80
63#define ETTS_REGS_OFFSET 0xa0
64
65#define FMAN_CTRL_REGS_OFFSET 0x80
66#define FMAN_ALARM_REGS_OFFSET 0xb8
67#define FMAN_FIPER_REGS_OFFSET 0xd0
68#define FMAN_ETTS_REGS_OFFSET 0xe0
69
70
71/* Bit definitions for the TMR_CTRL register */
72#define ALM1P (1<<31) /* Alarm1 output polarity */
73#define ALM2P (1<<30) /* Alarm2 output polarity */
74#define FIPERST (1<<28) /* FIPER start indication */
75#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
76#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
77#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
78#define TCLK_PERIOD_MASK (0x3ff)
79#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
80#define FRD (1<<14) /* FIPER Realignment Disable */
81#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
82#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
83#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
84#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
85#define COPH (1<<7) /* Generated clock output phase. */
86#define CIPH (1<<6) /* External oscillator input clock phase */
87#define TMSR (1<<5) /* Timer soft reset. */
88#define BYP (1<<3) /* Bypass drift compensated clock */
89#define TE (1<<2) /* 1588 timer enable. */
90#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
91#define CKSEL_MASK (0x3)
92
93/* Bit definitions for the TMR_TEVENT register */
94#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
95#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
96#define ALM2 (1<<17) /* Current time = alarm time register 2 */
97#define ALM1 (1<<16) /* Current time = alarm time register 1 */
98#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
99#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
100#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
101
102/* Bit definitions for the TMR_TEMASK register */
103#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
104#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
105#define ALM2EN (1<<17) /* Timer ALM2 event enable */
106#define ALM1EN (1<<16) /* Timer ALM1 event enable */
107#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
108#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
109
110/* Bit definitions for the TMR_PEVENT register */
111#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
112#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
113#define RXP (1<<0) /* PTP frame has been received */
114
115/* Bit definitions for the TMR_PEMASK register */
116#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
117#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
118#define RXPEN (1<<0) /* Receive PTP packet event enable */
119
120/* Bit definitions for the TMR_STAT register */
121#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
122#define STAT_VEC_MASK (0x3f)
123
124/* Bit definitions for the TMR_PRSC register */
125#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
126#define PRSC_OCK_MASK (0xffff)
127
128
129#define DRIVER "ptp_qoriq"
130#define N_EXT_TS 2
131
132#define DEFAULT_CKSEL 1
133#define DEFAULT_TMR_PRSC 2
134#define DEFAULT_FIPER1_PERIOD 1000000000
135#define DEFAULT_FIPER2_PERIOD 100000
136
137struct qoriq_ptp {
138 void __iomem *base;
139 struct qoriq_ptp_registers regs;
140 spinlock_t lock; /* protects regs */
141 struct ptp_clock *clock;
142 struct ptp_clock_info caps;
143 struct resource *rsrc;
144 int irq;
145 int phc_index;
146 u64 alarm_interval; /* for periodic alarm */
147 u64 alarm_value;
148 u32 tclk_period; /* nanoseconds */
149 u32 tmr_prsc;
150 u32 tmr_add;
151 u32 cksel;
152 u32 tmr_fiper1;
153 u32 tmr_fiper2;
154};
155
156static inline u32 qoriq_read(unsigned __iomem *addr)
157{
158 u32 val;
159
160 val = ioread32be(addr);
161 return val;
162}
163
164static inline void qoriq_write(unsigned __iomem *addr, u32 val)
165{
166 iowrite32be(val, addr);
167}
168
169#endif