tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a7794/r8a7745 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Renesas Solutions Corp.
7 * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
8 */
9
10#include <linux/kernel.h>
11
12#include "core.h"
13#include "sh_pfc.h"
14
15#define CPU_ALL_PORT(fn, sfx) \
16 PORT_GP_32(0, fn, sfx), \
17 PORT_GP_26(1, fn, sfx), \
18 PORT_GP_32(2, fn, sfx), \
19 PORT_GP_32(3, fn, sfx), \
20 PORT_GP_32(4, fn, sfx), \
21 PORT_GP_28(5, fn, sfx), \
22 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
23 PORT_GP_1(6, 24, fn, sfx), \
24 PORT_GP_1(6, 25, fn, sfx)
25
26enum {
27 PINMUX_RESERVED = 0,
28
29 PINMUX_DATA_BEGIN,
30 GP_ALL(DATA),
31 PINMUX_DATA_END,
32
33 PINMUX_FUNCTION_BEGIN,
34 GP_ALL(FN),
35
36 /* GPSR0 */
37 FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
38 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
39 FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
40 FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
41 FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
42 FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
43 FN_IP2_17_16,
44
45 /* GPSR1 */
46 FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
47 FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
48 FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
49 FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
50 FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
51
52 /* GPSR2 */
53 FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
54 FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
55 FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
56 FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
57 FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
58 FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
59 FN_IP6_5_4, FN_IP6_7_6,
60
61 /* GPSR3 */
62 FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
63 FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
64 FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
65 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
66 FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
67 FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
68 FN_IP8_22_20,
69
70 /* GPSR4 */
71 FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
72 FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
73 FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
74 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
75 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
76 FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
77 FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
78
79 /* GPSR5 */
80 FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
81 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
82 FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
83 FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
84 FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
85 FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
86
87 /* GPSR6 */
88 FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
89 FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
90 FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
91 FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
92 FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
93
94 /* IPSR0 */
95 FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
96 FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
97 FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
98 FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
99 FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
100 FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
101 FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
102 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
103
104 /* IPSR1 */
105 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
106 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
107 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
108 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
109 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
110 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
111 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
112 FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
113 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
114 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
115 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
116 FN_A1, FN_SCIFB1_TXD,
117 FN_A3, FN_SCIFB0_SCK,
118 FN_A4, FN_SCIFB0_TXD,
119 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
120 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
121
122 /* IPSR2 */
123 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
124 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
125 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
126 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
127 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
128 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
129 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
130 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
131 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
132 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
133 FN_TPUTO2_B,
134 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
135 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
136 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
137 FN_A20, FN_SPCLK,
138
139 /* IPSR3 */
140 FN_A21, FN_MOSI_IO0,
141 FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
142 FN_A23, FN_IO2, FN_ATAWR1_N,
143 FN_A24, FN_IO3, FN_EX_WAIT2,
144 FN_A25, FN_SSL, FN_ATARD1_N,
145 FN_CS0_N, FN_VI1_DATA8,
146 FN_CS1_N_A26, FN_VI1_DATA9,
147 FN_EX_CS0_N, FN_VI1_DATA10,
148 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
149 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
150 FN_SCIFB2_TXD,
151 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
152 FN_SCIFB2_SCK,
153 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
154 FN_SCIFB2_CTS_N,
155 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
156 FN_SCIFB2_RTS_N,
157 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
158 FN_RD_N, FN_ATACS11_N,
159 FN_RD_WR_N, FN_ATAG1_N,
160
161 /* IPSR4 */
162 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
163 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
164 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
165 FN_DU0_DR2, FN_LCDOUT18,
166 FN_DU0_DR3, FN_LCDOUT19,
167 FN_DU0_DR4, FN_LCDOUT20,
168 FN_DU0_DR5, FN_LCDOUT21,
169 FN_DU0_DR6, FN_LCDOUT22,
170 FN_DU0_DR7, FN_LCDOUT23,
171 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
172 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
173 FN_DU0_DG2, FN_LCDOUT10,
174 FN_DU0_DG3, FN_LCDOUT11,
175 FN_DU0_DG4, FN_LCDOUT12,
176
177 /* IPSR5 */
178 FN_DU0_DG5, FN_LCDOUT13,
179 FN_DU0_DG6, FN_LCDOUT14,
180 FN_DU0_DG7, FN_LCDOUT15,
181 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
182 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
183 FN_DU0_DB2, FN_LCDOUT2,
184 FN_DU0_DB3, FN_LCDOUT3,
185 FN_DU0_DB4, FN_LCDOUT4,
186 FN_DU0_DB5, FN_LCDOUT5,
187 FN_DU0_DB6, FN_LCDOUT6,
188 FN_DU0_DB7, FN_LCDOUT7,
189 FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
190 FN_DU0_DOTCLKOUT0, FN_QCLK,
191 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
192 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
193
194 /* IPSR6 */
195 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
196 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
197 FN_DU0_DISP, FN_QPOLA,
198 FN_DU0_CDE, FN_QPOLB,
199 FN_VI0_CLK, FN_AVB_RX_CLK,
200 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
201 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
202 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
203 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
204 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
205 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
206 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
207 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
208 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
209 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
210 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
211 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
212 FN_AVB_TX_EN,
213 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
214 FN_ADIDATA,
215
216 /* IPSR7 */
217 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
218 FN_ADICS_SAMP,
219 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
220 FN_ADICLK,
221 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
222 FN_ADICHS0,
223 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
224 FN_ADICHS1,
225 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
226 FN_ADICHS2,
227 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
228 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
229 FN_SSI_WS5_B,
230 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
231 FN_SSI_SDATA5_B,
232 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
233 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
234 FN_SSI_WS6_B,
235 FN_DREQ0_N, FN_SCIFB1_RXD,
236
237 /* IPSR8 */
238 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
239 FN_SSI_SDATA6_B,
240 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
241 FN_SSI_SCK78_B,
242 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
243 FN_SSI_WS78_B,
244 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
245 FN_AVB_MAGIC, FN_SSI_SDATA7_B,
246 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
247 FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
248 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
249 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
250 FN_CAN1_RX_D, FN_TPUTO0_B,
251 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
252 FN_CAN1_TX_D,
253 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
254 FN_TPUTO1_B,
255 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
256 FN_BPFCLK_C,
257 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
258 FN_FMCLK_C,
259
260 /* IPSR9 */
261 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
262 FN_FMIN_C,
263 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
264 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
265 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
266 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
267 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
268 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
269 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
270 FN_SPEEDIN_B,
271 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
272 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
273 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
274
275 /* IPSR10 */
276 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
277 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
278 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
279 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
280 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
281 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
282 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
283 FN_SSI_SCK4_B,
284 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
285 FN_SSI_WS4_B,
286 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
287 FN_SSI_SDATA4_B,
288 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
289 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
290
291 /* IPSR11 */
292 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
293 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
294 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
295 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
296 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
297 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
298 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
299 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
300 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
301 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
302 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
303 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
304
305 /* IPSR12 */
306 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
307 FN_DREQ1_N_B,
308 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
309 FN_CAN1_RX_C, FN_DACK1_B,
310 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
311 FN_CAN1_TX_C, FN_DREQ2_N,
312 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
313 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
314 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
315 FN_DACK2, FN_ETH_MDIO_B,
316 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
317 FN_ETH_CRS_DV_B,
318 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
319 FN_ETH_RX_ER_B,
320 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
321 FN_ETH_RXD0_B,
322 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
323
324 /* IPSR13 */
325 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
326 FN_ATACS00_N, FN_ETH_LINK_B,
327 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
328 FN_ATACS10_N, FN_ETH_REFCLK_B,
329 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
330 FN_ETH_TXD1_B,
331 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
332 FN_ETH_TX_EN_B,
333 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
334 FN_ATADIR0_N, FN_ETH_MAGIC_B,
335 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
336 FN_TS_SDATA_C, FN_ETH_TXD0_B,
337 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
338 FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
339 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
340 FN_TS_SDEN_C, FN_FMCLK_E,
341 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
342 FN_TS_SPSYNC_C, FN_FMIN_E,
343
344 /* MOD_SEL */
345 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
346 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
347 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
348 FN_SEL_DARC_4,
349 FN_SEL_ETH_0, FN_SEL_ETH_1,
350 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
351 FN_SEL_I2C00_4,
352 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
353 FN_SEL_I2C01_4,
354 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
355 FN_SEL_I2C02_4,
356 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
357 FN_SEL_I2C03_4,
358 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
359 FN_SEL_I2C04_4,
360 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
361
362 /* MOD_SEL2 */
363 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
364 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
365 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
366 FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
367 FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
368 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
369 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
370 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
371 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
372 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
373 FN_SEL_TMU_0, FN_SEL_TMU_1,
374 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
375 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
376 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
377 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
378
379 /* MOD_SEL3 */
380 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
381 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
382 FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
383 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
384 FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
385 FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
386 FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
387 FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
388 FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
389 FN_SEL_SSI9_1,
390 PINMUX_FUNCTION_END,
391
392 PINMUX_MARK_BEGIN,
393 A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
394
395 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
396
397 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
398 SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
399
400 SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
401 SD1_DATA2_MARK, SD1_DATA3_MARK,
402
403 /* IPSR0 */
404 SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
405 MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
406 SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
407 SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
408 MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
409 CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
410 CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
411 SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
412 SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
413 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
414
415 /* IPSR1 */
416 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
417 D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
418 D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
419 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
420 D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
421 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
422 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
423 D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
424 D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
425 D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
426 A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
427 A1_MARK, SCIFB1_TXD_MARK,
428 A3_MARK, SCIFB0_SCK_MARK,
429 A4_MARK, SCIFB0_TXD_MARK,
430 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
431 A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
432
433 /* IPSR2 */
434 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
435 A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
436 A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
437 A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
438 A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
439 A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
440 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
441 A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
442 A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
443 A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
444 CAN_CLK_C_MARK, TPUTO2_B_MARK,
445 A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
446 A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
447 A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
448 A20_MARK, SPCLK_MARK,
449
450 /* IPSR3 */
451 A21_MARK, MOSI_IO0_MARK,
452 A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
453 A23_MARK, IO2_MARK, ATAWR1_N_MARK,
454 A24_MARK, IO3_MARK, EX_WAIT2_MARK,
455 A25_MARK, SSL_MARK, ATARD1_N_MARK,
456 CS0_N_MARK, VI1_DATA8_MARK,
457 CS1_N_A26_MARK, VI1_DATA9_MARK,
458 EX_CS0_N_MARK, VI1_DATA10_MARK,
459 EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
460 EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
461 TPUTO3_MARK, SCIFB2_TXD_MARK,
462 EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
463 BPFCLK_MARK, SCIFB2_SCK_MARK,
464 EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
465 FMCLK_MARK, SCIFB2_CTS_N_MARK,
466 EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
467 FMIN_MARK, SCIFB2_RTS_N_MARK,
468 BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
469 RD_N_MARK, ATACS11_N_MARK,
470 RD_WR_N_MARK, ATAG1_N_MARK,
471
472 /* IPSR4 */
473 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
474 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
475 DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
476 DU0_DR2_MARK, LCDOUT18_MARK,
477 DU0_DR3_MARK, LCDOUT19_MARK,
478 DU0_DR4_MARK, LCDOUT20_MARK,
479 DU0_DR5_MARK, LCDOUT21_MARK,
480 DU0_DR6_MARK, LCDOUT22_MARK,
481 DU0_DR7_MARK, LCDOUT23_MARK,
482 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
483 DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
484 DU0_DG2_MARK, LCDOUT10_MARK,
485 DU0_DG3_MARK, LCDOUT11_MARK,
486 DU0_DG4_MARK, LCDOUT12_MARK,
487
488 /* IPSR5 */
489 DU0_DG5_MARK, LCDOUT13_MARK,
490 DU0_DG6_MARK, LCDOUT14_MARK,
491 DU0_DG7_MARK, LCDOUT15_MARK,
492 DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
493 CAN0_RX_C_MARK,
494 DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
495 CAN0_TX_C_MARK,
496 DU0_DB2_MARK, LCDOUT2_MARK,
497 DU0_DB3_MARK, LCDOUT3_MARK,
498 DU0_DB4_MARK, LCDOUT4_MARK,
499 DU0_DB5_MARK, LCDOUT5_MARK,
500 DU0_DB6_MARK, LCDOUT6_MARK,
501 DU0_DB7_MARK, LCDOUT7_MARK,
502 DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
503 DU0_DOTCLKOUT0_MARK, QCLK_MARK,
504 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
505 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
506
507 /* IPSR6 */
508 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
509 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
510 DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
511 VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
512 VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
513 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
514 VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
515 VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
516 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
517 VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
518 VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
519 VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
520 AVB_RXD7_MARK,
521 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
522 AVB_RX_ER_MARK,
523 VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
524 AVB_COL_MARK,
525 VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
526 AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
527 ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
528 AVB_TX_CLK_MARK, ADIDATA_MARK,
529
530 /* IPSR7 */
531 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
532 AVB_TXD0_MARK, ADICS_SAMP_MARK,
533 ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
534 AVB_TXD1_MARK, ADICLK_MARK,
535 ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
536 AVB_TXD2_MARK, ADICHS0_MARK,
537 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
538 AVB_TXD3_MARK, ADICHS1_MARK,
539 ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
540 AVB_TXD4_MARK, ADICHS2_MARK,
541 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
542 SSI_SCK5_B_MARK,
543 ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
544 AVB_TXD6_MARK, SSI_WS5_B_MARK,
545 ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
546 AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
547 ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
548 SSI_SCK6_B_MARK,
549 ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
550 AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
551 DREQ0_N_MARK, SCIFB1_RXD_MARK,
552
553 /* IPSR8 */
554 ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
555 AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
556 I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
557 HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
558 AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
559 SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
560 HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
561 AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
562 HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
563 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
564 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
565 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
566 CAN1_TX_D_MARK,
567 I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
568 TS_SDATA_D_MARK, TPUTO1_B_MARK,
569 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
570 BPFCLK_C_MARK,
571 MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
572 TS_SDEN_D_MARK, FMCLK_C_MARK,
573
574 /* IPSR9 */
575 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
576 TS_SPSYNC_D_MARK, FMIN_C_MARK,
577 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
578 MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
579 MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
580 FMCLK_B_MARK,
581 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
582 FMIN_B_MARK,
583 HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
584 HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
585 HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
586 SPEEDIN_B_MARK,
587 HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
588 SSI_SCK1_B_MARK,
589 HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
590 SSI_WS1_B_MARK,
591 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
592 CAN_TXCLK_MARK,
593
594 /* IPSR10 */
595 SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
596 SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
597 SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
598 SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
599 SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
600 SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
601 SSI_SDATA9_B_MARK,
602 SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
603 AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
604 SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
605 AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
606 I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
607 SSI_SDATA4_B_MARK,
608 I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
609 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
610
611 /* IPSR11 */
612 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
613 SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
614 SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
615 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
616 DU1_EXVSYNC_DU1_VSYNC_MARK,
617 SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
618 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
619 SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
620 SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
621 SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
622 CAN_CLK_D_MARK,
623 SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
624 SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
625 SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
626
627 /* IPSR12 */
628 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
629 DREQ1_N_B_MARK,
630 SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
631 CAN1_RX_C_MARK, DACK1_B_MARK,
632 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
633 CAN1_TX_C_MARK, DREQ2_N_MARK,
634 SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
635 SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
636 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
637 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
638 DACK2_MARK, ETH_MDIO_B_MARK,
639 SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
640 CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
641 SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
642 CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
643 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
644 ETH_RXD0_B_MARK,
645 SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
646 ETH_RXD1_B_MARK,
647
648 /* IPSR13 */
649 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
650 ATACS00_N_MARK, ETH_LINK_B_MARK,
651 SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
652 VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
653 SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
654 EX_WAIT1_MARK, ETH_TXD1_B_MARK,
655 SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
656 ATARD0_N_MARK, ETH_TX_EN_B_MARK,
657 SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
658 ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
659 AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
660 TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
661 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
662 TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
663 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
664 TS_SDEN_C_MARK, FMCLK_E_MARK,
665 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
666 TS_SPSYNC_C_MARK, FMIN_E_MARK,
667 PINMUX_MARK_END,
668};
669
670static const u16 pinmux_data[] = {
671 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
672
673 PINMUX_SINGLE(A2),
674 PINMUX_SINGLE(WE0_N),
675 PINMUX_SINGLE(WE1_N),
676 PINMUX_SINGLE(DACK0),
677 PINMUX_SINGLE(USB0_PWEN),
678 PINMUX_SINGLE(USB0_OVC),
679 PINMUX_SINGLE(USB1_PWEN),
680 PINMUX_SINGLE(USB1_OVC),
681 PINMUX_SINGLE(SD0_CLK),
682 PINMUX_SINGLE(SD0_CMD),
683 PINMUX_SINGLE(SD0_DATA0),
684 PINMUX_SINGLE(SD0_DATA1),
685 PINMUX_SINGLE(SD0_DATA2),
686 PINMUX_SINGLE(SD0_DATA3),
687 PINMUX_SINGLE(SD0_CD),
688 PINMUX_SINGLE(SD0_WP),
689 PINMUX_SINGLE(SD1_CLK),
690 PINMUX_SINGLE(SD1_CMD),
691 PINMUX_SINGLE(SD1_DATA0),
692 PINMUX_SINGLE(SD1_DATA1),
693 PINMUX_SINGLE(SD1_DATA2),
694 PINMUX_SINGLE(SD1_DATA3),
695
696 /* IPSR0 */
697 PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
698 PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
699 PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
700 PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
701 PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
702 PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
703 PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
704 PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
705 PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
706 PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
707 PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
708 PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
709 PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
710 PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
711 PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
712 PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
713 PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
714 PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
715 PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
716 PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
717 PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
718 PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
719 PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
720 PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
721 PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
722 PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
723 PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
724 PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
725 PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
726 PINMUX_IPSR_GPSR(IP0_23_22, D0),
727 PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
728 PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
729 PINMUX_IPSR_GPSR(IP0_24, D1),
730 PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
731 PINMUX_IPSR_GPSR(IP0_25, D2),
732 PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
733 PINMUX_IPSR_GPSR(IP0_27_26, D3),
734 PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
735 PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
736 PINMUX_IPSR_GPSR(IP0_29_28, D4),
737 PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
738 PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
739 PINMUX_IPSR_GPSR(IP0_31_30, D5),
740 PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
741 PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
742
743 /* IPSR1 */
744 PINMUX_IPSR_GPSR(IP1_1_0, D6),
745 PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
746 PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
747 PINMUX_IPSR_GPSR(IP1_3_2, D7),
748 PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
749 PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
750 PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
751 PINMUX_IPSR_GPSR(IP1_5_4, D8),
752 PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
753 PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
754 PINMUX_IPSR_GPSR(IP1_7_6, D9),
755 PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
756 PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
757 PINMUX_IPSR_GPSR(IP1_10_8, D10),
758 PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
759 PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
760 PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
761 PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
762 PINMUX_IPSR_GPSR(IP1_12_11, D11),
763 PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
764 PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
765 PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
766 PINMUX_IPSR_GPSR(IP1_14_13, D12),
767 PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
768 PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
769 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
770 PINMUX_IPSR_GPSR(IP1_17_15, D13),
771 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
772 PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
773 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
774 PINMUX_IPSR_GPSR(IP1_19_18, D14),
775 PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
776 PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
777 PINMUX_IPSR_GPSR(IP1_21_20, D15),
778 PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
779 PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
780 PINMUX_IPSR_GPSR(IP1_23_22, A0),
781 PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
782 PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
783 PINMUX_IPSR_GPSR(IP1_24, A1),
784 PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
785 PINMUX_IPSR_GPSR(IP1_26, A3),
786 PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
787 PINMUX_IPSR_GPSR(IP1_27, A4),
788 PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
789 PINMUX_IPSR_GPSR(IP1_29_28, A5),
790 PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
791 PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
792 PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
793 PINMUX_IPSR_GPSR(IP1_31_30, A6),
794 PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
795 PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
796 PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
797
798 /* IPSR2 */
799 PINMUX_IPSR_GPSR(IP2_1_0, A7),
800 PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
801 PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
802 PINMUX_IPSR_GPSR(IP2_3_2, A8),
803 PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
804 PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
805 PINMUX_IPSR_GPSR(IP2_5_4, A9),
806 PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
807 PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
808 PINMUX_IPSR_GPSR(IP2_7_6, A10),
809 PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
810 PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
811 PINMUX_IPSR_GPSR(IP2_9_8, A11),
812 PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
813 PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
814 PINMUX_IPSR_GPSR(IP2_11_10, A12),
815 PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
816 PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
817 PINMUX_IPSR_GPSR(IP2_13_12, A13),
818 PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
819 PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
820 PINMUX_IPSR_GPSR(IP2_15_14, A14),
821 PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
822 PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
823 PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
824 PINMUX_IPSR_GPSR(IP2_17_16, A15),
825 PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
826 PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
827 PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
828 PINMUX_IPSR_GPSR(IP2_20_18, A16),
829 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
830 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
831 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
832 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
833 PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
834 PINMUX_IPSR_GPSR(IP2_23_21, A17),
835 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
836 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
837 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
838 PINMUX_IPSR_GPSR(IP2_26_24, A18),
839 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
840 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
841 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
842 PINMUX_IPSR_GPSR(IP2_29_27, A19),
843 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
844 PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
845 PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
846 PINMUX_IPSR_GPSR(IP2_31_30, A20),
847 PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
848
849 /* IPSR3 */
850 PINMUX_IPSR_GPSR(IP3_1_0, A21),
851 PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
852 PINMUX_IPSR_GPSR(IP3_3_2, A22),
853 PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
854 PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
855 PINMUX_IPSR_GPSR(IP3_5_4, A23),
856 PINMUX_IPSR_GPSR(IP3_5_4, IO2),
857 PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
858 PINMUX_IPSR_GPSR(IP3_7_6, A24),
859 PINMUX_IPSR_GPSR(IP3_7_6, IO3),
860 PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
861 PINMUX_IPSR_GPSR(IP3_9_8, A25),
862 PINMUX_IPSR_GPSR(IP3_9_8, SSL),
863 PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
864 PINMUX_IPSR_GPSR(IP3_10, CS0_N),
865 PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
866 PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
867 PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
868 PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
869 PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
870 PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
871 PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
872 PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
873 PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
874 PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
875 PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
876 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
877 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
878 PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
879 PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
880 PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
881 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
882 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
883 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
884 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
885 PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
886 PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
887 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
888 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
889 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
890 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
891 PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
892 PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
893 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
894 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
895 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
896 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
897 PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
898 PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
899 PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
900 PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
901 PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
902 PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
903 PINMUX_IPSR_GPSR(IP3_30, RD_N),
904 PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
905 PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
906 PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
907
908 /* IPSR4 */
909 PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
910 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
911 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
912 PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
913 PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
914 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
915 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
916 PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
917 PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
918 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
919 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
920 PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
921 PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
922 PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
923 PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
924 PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
925 PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
926 PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
927 PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
928 PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
929 PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
930 PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
931 PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
932 PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
933 PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
934 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
935 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
936 PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
937 PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
938 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
939 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
940 PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
941 PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
942 PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
943 PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
944 PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
945 PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
946
947 /* IPSR5 */
948 PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
949 PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
950 PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
951 PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
952 PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
953 PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
954 PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
955 PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
956 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
957 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
958 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
959 PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
960 PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
961 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
962 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
963 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
964 PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
965 PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
966 PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
967 PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
968 PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
969 PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
970 PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
971 PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
972 PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
973 PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
974 PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
975 PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
976 PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
977 PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
978 PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
979 PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
980 PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
981 PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
982 PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
983 PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
984
985 /* IPSR6 */
986 PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
987 PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
988 PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
989 PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
990 PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
991 PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
992 PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
993 PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
994 PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
995 PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
996 PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
997 PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
998 PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
999 PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
1000 PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
1001 PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
1002 PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
1003 PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
1004 PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
1005 PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
1006 PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
1007 PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
1008 PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
1009 PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
1010 PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
1011 PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
1012 PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
1013 PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1014 PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1015 PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1016 PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
1017 PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
1018 PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1019 PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1020 PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1021 PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1022 PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1023 PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1024 PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1025 PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1026 PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1027 PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1028 PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1029 PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1030 PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1031 PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1032 PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1033 PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1034 PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1035 PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
1036 PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1037 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1038
1039 /* IPSR7 */
1040 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1041 PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1042 PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1043 PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
1044 PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1045 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1046 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1047 PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1048 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1049 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1050 PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1051 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1052 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1053 PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1054 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1055 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1056 PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1057 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1058 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1059 PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1060 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1061 PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1062 PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1063 PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1064 PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1065 PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1066 PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1067 PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1068 PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1069 PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1070 PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1071 PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1072 PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1073 PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1074 PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1075 PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1076 PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1077 PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1078 PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
1079 PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1080 PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1081 PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1082 PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1083 PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1084 PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
1085 PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1086 PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1087 PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1088 PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1089 PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1090 PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1091 PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1092 PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1093 PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1094 PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1095 PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1096 PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1097 PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1098 PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1099 PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1100
1101 /* IPSR8 */
1102 PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1103 PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1104 PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1105 PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1106 PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1107 PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1108 PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1109 PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1110 PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1111 PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1112 PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1113 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1114 PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1115 PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1116 PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1117 PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1118 PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1119 PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1120 PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1121 PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1122 PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1123 PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1124 PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1125 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1126 PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1127 PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1128 PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1129 PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1130 PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1131 PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1132 PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1133 PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1134 PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1135 PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1136 PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1137 PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1138 PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1139 PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1140 PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1141 PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1142 PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1143 PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1144 PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1145 PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1146 PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1147 PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1148 PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1149 PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1150 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1151 PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1152 PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1153 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1154 PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1155 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1156 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1157 PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1158 PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1159 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1160 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1161 PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1162 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1163 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1164 PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1165 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1166 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1167
1168 /* IPSR9 */
1169 PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1170 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1171 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1172 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1173 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1174 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1175 PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1176 PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1177 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1178 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1179 PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1180 PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1181 PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1182 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1183 PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1184 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1185 PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1186 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1187 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1188 PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1189 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1190 PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1191 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1192 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1193 PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1194 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1195 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1196 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1197 PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1198 PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1199 PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1200 PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1201 PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1202 PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1203 PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1204 PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1205 PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1206 PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1207 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1208 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1209 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1210 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1211 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1212 PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1213 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1214 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1215 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1216 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1217 PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1218 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1219 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1220 PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1221 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1222 PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1223 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1224
1225 /* IPSR10 */
1226 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1227 PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
1228 PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1229 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1230 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1231 PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
1232 PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1233 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1234 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1235 PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
1236 PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1237 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1238 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1239 PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
1240 PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1241 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1242 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1243 PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1244 PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1245 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1246 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1247 PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1248 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1249 PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1250 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1251 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1252 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1253 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1254 PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1255 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1256 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1257 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1258 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1259 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1260 PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1261 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1262 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1263 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1264 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1265 PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1266 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1267 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1268 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1269 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1270 PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1271 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1272 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1273 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1274 PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1275
1276 /* IPSR11 */
1277 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1278 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1279 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1280 PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1281 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1282 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1283 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1284 PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1285 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1286 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1287 PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1288 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1289 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1290 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1291 PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1292 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1293 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1294 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1295 PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1296 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1297 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1298 PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
1299 PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1300 PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1301 PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1302 PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
1303 PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1304 PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1305 PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1306 PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1307 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1308 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1309 PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1310 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1311 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1312 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1313 PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1314 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1315 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1316 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1317 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1318 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1319 PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1320 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1321
1322 /* IPSR12 */
1323 PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1324 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1325 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1326 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1327 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1328 PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1329 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1330 PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1331 PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1332 PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1333 PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1334 PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1335 PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1336 PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1337 PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1338 PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1339 PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1340 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1341 PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1342 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1343 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1344 PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1345 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1346 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1347 PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1348 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1349 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1350 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1351 PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1352 PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1353 PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1354 PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1355 PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1356 PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1357 PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1358 PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
1359 PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1360 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1361 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1362 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1363 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1364 PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
1365 PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1366 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1367 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1368 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1369 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1370 PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1371 PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
1372 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1373 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1374 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1375 PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1376 PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
1377 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1378
1379 /* IPSR13 */
1380 PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1381 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1382 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1383 PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1384 PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1385 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1386 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1387 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1388 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1389 PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1390 PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1391 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1392 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1393 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1394 PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1395 PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1396 PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1397 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1398 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1399 PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1400 PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1401 PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1402 PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1403 PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1404 PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1405 PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1406 PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1407 PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1408 PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1409 PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1410 PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1411 PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1412 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1413 PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1414 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1415 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1416 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1417 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1418 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1419 PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1420 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1421 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1422 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1423 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1424 PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1425 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1426 PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1427 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1428 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1429 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1430 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1431 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1432 PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1433 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1434 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1435};
1436
1437static const struct sh_pfc_pin pinmux_pins[] = {
1438 PINMUX_GPIO_GP_ALL(),
1439};
1440
1441/* - Audio Clock ------------------------------------------------------------ */
1442static const unsigned int audio_clka_pins[] = {
1443 /* CLKA */
1444 RCAR_GP_PIN(5, 20),
1445};
1446static const unsigned int audio_clka_mux[] = {
1447 AUDIO_CLKA_MARK,
1448};
1449static const unsigned int audio_clka_b_pins[] = {
1450 /* CLKA */
1451 RCAR_GP_PIN(3, 25),
1452};
1453static const unsigned int audio_clka_b_mux[] = {
1454 AUDIO_CLKA_B_MARK,
1455};
1456static const unsigned int audio_clka_c_pins[] = {
1457 /* CLKA */
1458 RCAR_GP_PIN(4, 20),
1459};
1460static const unsigned int audio_clka_c_mux[] = {
1461 AUDIO_CLKA_C_MARK,
1462};
1463static const unsigned int audio_clka_d_pins[] = {
1464 /* CLKA */
1465 RCAR_GP_PIN(5, 0),
1466};
1467static const unsigned int audio_clka_d_mux[] = {
1468 AUDIO_CLKA_D_MARK,
1469};
1470static const unsigned int audio_clkb_pins[] = {
1471 /* CLKB */
1472 RCAR_GP_PIN(5, 21),
1473};
1474static const unsigned int audio_clkb_mux[] = {
1475 AUDIO_CLKB_MARK,
1476};
1477static const unsigned int audio_clkb_b_pins[] = {
1478 /* CLKB */
1479 RCAR_GP_PIN(3, 26),
1480};
1481static const unsigned int audio_clkb_b_mux[] = {
1482 AUDIO_CLKB_B_MARK,
1483};
1484static const unsigned int audio_clkb_c_pins[] = {
1485 /* CLKB */
1486 RCAR_GP_PIN(4, 21),
1487};
1488static const unsigned int audio_clkb_c_mux[] = {
1489 AUDIO_CLKB_C_MARK,
1490};
1491static const unsigned int audio_clkc_pins[] = {
1492 /* CLKC */
1493 RCAR_GP_PIN(5, 22),
1494};
1495static const unsigned int audio_clkc_mux[] = {
1496 AUDIO_CLKC_MARK,
1497};
1498static const unsigned int audio_clkc_b_pins[] = {
1499 /* CLKC */
1500 RCAR_GP_PIN(3, 29),
1501};
1502static const unsigned int audio_clkc_b_mux[] = {
1503 AUDIO_CLKC_B_MARK,
1504};
1505static const unsigned int audio_clkc_c_pins[] = {
1506 /* CLKC */
1507 RCAR_GP_PIN(4, 22),
1508};
1509static const unsigned int audio_clkc_c_mux[] = {
1510 AUDIO_CLKC_C_MARK,
1511};
1512static const unsigned int audio_clkout_pins[] = {
1513 /* CLKOUT */
1514 RCAR_GP_PIN(5, 23),
1515};
1516static const unsigned int audio_clkout_mux[] = {
1517 AUDIO_CLKOUT_MARK,
1518};
1519static const unsigned int audio_clkout_b_pins[] = {
1520 /* CLKOUT */
1521 RCAR_GP_PIN(3, 12),
1522};
1523static const unsigned int audio_clkout_b_mux[] = {
1524 AUDIO_CLKOUT_B_MARK,
1525};
1526static const unsigned int audio_clkout_c_pins[] = {
1527 /* CLKOUT */
1528 RCAR_GP_PIN(4, 23),
1529};
1530static const unsigned int audio_clkout_c_mux[] = {
1531 AUDIO_CLKOUT_C_MARK,
1532};
1533/* - AVB -------------------------------------------------------------------- */
1534static const unsigned int avb_link_pins[] = {
1535 RCAR_GP_PIN(3, 26),
1536};
1537static const unsigned int avb_link_mux[] = {
1538 AVB_LINK_MARK,
1539};
1540static const unsigned int avb_magic_pins[] = {
1541 RCAR_GP_PIN(3, 27),
1542};
1543static const unsigned int avb_magic_mux[] = {
1544 AVB_MAGIC_MARK,
1545};
1546static const unsigned int avb_phy_int_pins[] = {
1547 RCAR_GP_PIN(3, 28),
1548};
1549static const unsigned int avb_phy_int_mux[] = {
1550 AVB_PHY_INT_MARK,
1551};
1552static const unsigned int avb_mdio_pins[] = {
1553 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1554};
1555static const unsigned int avb_mdio_mux[] = {
1556 AVB_MDC_MARK, AVB_MDIO_MARK,
1557};
1558static const unsigned int avb_mii_pins[] = {
1559 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1560 RCAR_GP_PIN(3, 17),
1561
1562 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1563 RCAR_GP_PIN(3, 5),
1564
1565 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1566 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1567 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1568};
1569static const unsigned int avb_mii_mux[] = {
1570 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1571 AVB_TXD3_MARK,
1572
1573 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1574 AVB_RXD3_MARK,
1575
1576 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1577 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1578 AVB_TX_CLK_MARK, AVB_COL_MARK,
1579};
1580static const unsigned int avb_gmii_pins[] = {
1581 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1582 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1583 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1584
1585 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1586 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1587 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1588
1589 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1590 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1591 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1592 RCAR_GP_PIN(3, 11),
1593};
1594static const unsigned int avb_gmii_mux[] = {
1595 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1596 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1597 AVB_TXD6_MARK, AVB_TXD7_MARK,
1598
1599 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1600 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1601 AVB_RXD6_MARK, AVB_RXD7_MARK,
1602
1603 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1604 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1605 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1606 AVB_COL_MARK,
1607};
1608
1609/* - CAN -------------------------------------------------------------------- */
1610static const unsigned int can0_data_pins[] = {
1611 /* TX, RX */
1612 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1613};
1614
1615static const unsigned int can0_data_mux[] = {
1616 CAN0_TX_MARK, CAN0_RX_MARK,
1617};
1618
1619static const unsigned int can0_data_b_pins[] = {
1620 /* TX, RX */
1621 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1622};
1623
1624static const unsigned int can0_data_b_mux[] = {
1625 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1626};
1627
1628static const unsigned int can0_data_c_pins[] = {
1629 /* TX, RX */
1630 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1631};
1632
1633static const unsigned int can0_data_c_mux[] = {
1634 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1635};
1636
1637static const unsigned int can0_data_d_pins[] = {
1638 /* TX, RX */
1639 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1640};
1641
1642static const unsigned int can0_data_d_mux[] = {
1643 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1644};
1645
1646static const unsigned int can1_data_pins[] = {
1647 /* TX, RX */
1648 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
1649};
1650
1651static const unsigned int can1_data_mux[] = {
1652 CAN1_TX_MARK, CAN1_RX_MARK,
1653};
1654
1655static const unsigned int can1_data_b_pins[] = {
1656 /* TX, RX */
1657 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1658};
1659
1660static const unsigned int can1_data_b_mux[] = {
1661 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1662};
1663
1664static const unsigned int can1_data_c_pins[] = {
1665 /* TX, RX */
1666 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1667};
1668
1669static const unsigned int can1_data_c_mux[] = {
1670 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1671};
1672
1673static const unsigned int can1_data_d_pins[] = {
1674 /* TX, RX */
1675 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1676};
1677
1678static const unsigned int can1_data_d_mux[] = {
1679 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1680};
1681
1682static const unsigned int can_clk_pins[] = {
1683 /* CLK */
1684 RCAR_GP_PIN(3, 31),
1685};
1686
1687static const unsigned int can_clk_mux[] = {
1688 CAN_CLK_MARK,
1689};
1690
1691static const unsigned int can_clk_b_pins[] = {
1692 /* CLK */
1693 RCAR_GP_PIN(1, 23),
1694};
1695
1696static const unsigned int can_clk_b_mux[] = {
1697 CAN_CLK_B_MARK,
1698};
1699
1700static const unsigned int can_clk_c_pins[] = {
1701 /* CLK */
1702 RCAR_GP_PIN(1, 0),
1703};
1704
1705static const unsigned int can_clk_c_mux[] = {
1706 CAN_CLK_C_MARK,
1707};
1708
1709static const unsigned int can_clk_d_pins[] = {
1710 /* CLK */
1711 RCAR_GP_PIN(5, 0),
1712};
1713
1714static const unsigned int can_clk_d_mux[] = {
1715 CAN_CLK_D_MARK,
1716};
1717
1718/* - DU --------------------------------------------------------------------- */
1719static const unsigned int du0_rgb666_pins[] = {
1720 /* R[7:2], G[7:2], B[7:2] */
1721 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1722 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1723 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1724 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1725 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1726 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1727};
1728static const unsigned int du0_rgb666_mux[] = {
1729 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1730 DU0_DR3_MARK, DU0_DR2_MARK,
1731 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1732 DU0_DG3_MARK, DU0_DG2_MARK,
1733 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1734 DU0_DB3_MARK, DU0_DB2_MARK,
1735};
1736static const unsigned int du0_rgb888_pins[] = {
1737 /* R[7:0], G[7:0], B[7:0] */
1738 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1739 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1740 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
1741 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1742 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1743 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1744 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1745 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1746 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1747};
1748static const unsigned int du0_rgb888_mux[] = {
1749 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1750 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1751 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1752 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1753 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1754 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1755};
1756static const unsigned int du0_clk0_out_pins[] = {
1757 /* DOTCLKOUT0 */
1758 RCAR_GP_PIN(2, 25),
1759};
1760static const unsigned int du0_clk0_out_mux[] = {
1761 DU0_DOTCLKOUT0_MARK
1762};
1763static const unsigned int du0_clk1_out_pins[] = {
1764 /* DOTCLKOUT1 */
1765 RCAR_GP_PIN(2, 26),
1766};
1767static const unsigned int du0_clk1_out_mux[] = {
1768 DU0_DOTCLKOUT1_MARK
1769};
1770static const unsigned int du0_clk_in_pins[] = {
1771 /* CLKIN */
1772 RCAR_GP_PIN(2, 24),
1773};
1774static const unsigned int du0_clk_in_mux[] = {
1775 DU0_DOTCLKIN_MARK
1776};
1777static const unsigned int du0_sync_pins[] = {
1778 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1779 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1780};
1781static const unsigned int du0_sync_mux[] = {
1782 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1783};
1784static const unsigned int du0_oddf_pins[] = {
1785 /* EXODDF/ODDF/DISP/CDE */
1786 RCAR_GP_PIN(2, 29),
1787};
1788static const unsigned int du0_oddf_mux[] = {
1789 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1790};
1791static const unsigned int du0_cde_pins[] = {
1792 /* CDE */
1793 RCAR_GP_PIN(2, 31),
1794};
1795static const unsigned int du0_cde_mux[] = {
1796 DU0_CDE_MARK,
1797};
1798static const unsigned int du0_disp_pins[] = {
1799 /* DISP */
1800 RCAR_GP_PIN(2, 30),
1801};
1802static const unsigned int du0_disp_mux[] = {
1803 DU0_DISP_MARK
1804};
1805static const unsigned int du1_rgb666_pins[] = {
1806 /* R[7:2], G[7:2], B[7:2] */
1807 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
1808 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1809 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1810 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1811 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1812 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1813};
1814static const unsigned int du1_rgb666_mux[] = {
1815 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1816 DU1_DR3_MARK, DU1_DR2_MARK,
1817 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1818 DU1_DG3_MARK, DU1_DG2_MARK,
1819 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1820 DU1_DB3_MARK, DU1_DB2_MARK,
1821};
1822static const unsigned int du1_rgb888_pins[] = {
1823 /* R[7:0], G[7:0], B[7:0] */
1824 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
1825 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1826 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1827 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1828 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1829 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
1830 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1831 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1832 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1833};
1834static const unsigned int du1_rgb888_mux[] = {
1835 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1836 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1837 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1838 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1839 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1840 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1841};
1842static const unsigned int du1_clk0_out_pins[] = {
1843 /* DOTCLKOUT0 */
1844 RCAR_GP_PIN(4, 25),
1845};
1846static const unsigned int du1_clk0_out_mux[] = {
1847 DU1_DOTCLKOUT0_MARK
1848};
1849static const unsigned int du1_clk1_out_pins[] = {
1850 /* DOTCLKOUT1 */
1851 RCAR_GP_PIN(4, 26),
1852};
1853static const unsigned int du1_clk1_out_mux[] = {
1854 DU1_DOTCLKOUT1_MARK
1855};
1856static const unsigned int du1_clk_in_pins[] = {
1857 /* DOTCLKIN */
1858 RCAR_GP_PIN(4, 24),
1859};
1860static const unsigned int du1_clk_in_mux[] = {
1861 DU1_DOTCLKIN_MARK
1862};
1863static const unsigned int du1_sync_pins[] = {
1864 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1865 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
1866};
1867static const unsigned int du1_sync_mux[] = {
1868 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1869};
1870static const unsigned int du1_oddf_pins[] = {
1871 /* EXODDF/ODDF/DISP/CDE */
1872 RCAR_GP_PIN(4, 29),
1873};
1874static const unsigned int du1_oddf_mux[] = {
1875 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1876};
1877static const unsigned int du1_cde_pins[] = {
1878 /* CDE */
1879 RCAR_GP_PIN(4, 31),
1880};
1881static const unsigned int du1_cde_mux[] = {
1882 DU1_CDE_MARK
1883};
1884static const unsigned int du1_disp_pins[] = {
1885 /* DISP */
1886 RCAR_GP_PIN(4, 30),
1887};
1888static const unsigned int du1_disp_mux[] = {
1889 DU1_DISP_MARK
1890};
1891/* - ETH -------------------------------------------------------------------- */
1892static const unsigned int eth_link_pins[] = {
1893 /* LINK */
1894 RCAR_GP_PIN(3, 18),
1895};
1896static const unsigned int eth_link_mux[] = {
1897 ETH_LINK_MARK,
1898};
1899static const unsigned int eth_magic_pins[] = {
1900 /* MAGIC */
1901 RCAR_GP_PIN(3, 22),
1902};
1903static const unsigned int eth_magic_mux[] = {
1904 ETH_MAGIC_MARK,
1905};
1906static const unsigned int eth_mdio_pins[] = {
1907 /* MDC, MDIO */
1908 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1909};
1910static const unsigned int eth_mdio_mux[] = {
1911 ETH_MDC_MARK, ETH_MDIO_MARK,
1912};
1913static const unsigned int eth_rmii_pins[] = {
1914 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1915 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1916 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1917 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1918};
1919static const unsigned int eth_rmii_mux[] = {
1920 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1921 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1922};
1923static const unsigned int eth_link_b_pins[] = {
1924 /* LINK */
1925 RCAR_GP_PIN(5, 15),
1926};
1927static const unsigned int eth_link_b_mux[] = {
1928 ETH_LINK_B_MARK,
1929};
1930static const unsigned int eth_magic_b_pins[] = {
1931 /* MAGIC */
1932 RCAR_GP_PIN(5, 19),
1933};
1934static const unsigned int eth_magic_b_mux[] = {
1935 ETH_MAGIC_B_MARK,
1936};
1937static const unsigned int eth_mdio_b_pins[] = {
1938 /* MDC, MDIO */
1939 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1940};
1941static const unsigned int eth_mdio_b_mux[] = {
1942 ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1943};
1944static const unsigned int eth_rmii_b_pins[] = {
1945 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1946 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1947 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1948 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1949};
1950static const unsigned int eth_rmii_b_mux[] = {
1951 ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1952 ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1953};
1954/* - HSCIF0 ----------------------------------------------------------------- */
1955static const unsigned int hscif0_data_pins[] = {
1956 /* RX, TX */
1957 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1958};
1959static const unsigned int hscif0_data_mux[] = {
1960 HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1961};
1962static const unsigned int hscif0_clk_pins[] = {
1963 /* SCK */
1964 RCAR_GP_PIN(3, 29),
1965};
1966static const unsigned int hscif0_clk_mux[] = {
1967 HSCIF0_HSCK_MARK,
1968};
1969static const unsigned int hscif0_ctrl_pins[] = {
1970 /* RTS, CTS */
1971 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1972};
1973static const unsigned int hscif0_ctrl_mux[] = {
1974 HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1975};
1976static const unsigned int hscif0_data_b_pins[] = {
1977 /* RX, TX */
1978 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1979};
1980static const unsigned int hscif0_data_b_mux[] = {
1981 HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1982};
1983static const unsigned int hscif0_clk_b_pins[] = {
1984 /* SCK */
1985 RCAR_GP_PIN(1, 0),
1986};
1987static const unsigned int hscif0_clk_b_mux[] = {
1988 HSCIF0_HSCK_B_MARK,
1989};
1990/* - HSCIF1 ----------------------------------------------------------------- */
1991static const unsigned int hscif1_data_pins[] = {
1992 /* RX, TX */
1993 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1994};
1995static const unsigned int hscif1_data_mux[] = {
1996 HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1997};
1998static const unsigned int hscif1_clk_pins[] = {
1999 /* SCK */
2000 RCAR_GP_PIN(4, 10),
2001};
2002static const unsigned int hscif1_clk_mux[] = {
2003 HSCIF1_HSCK_MARK,
2004};
2005static const unsigned int hscif1_ctrl_pins[] = {
2006 /* RTS, CTS */
2007 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2008};
2009static const unsigned int hscif1_ctrl_mux[] = {
2010 HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
2011};
2012static const unsigned int hscif1_data_b_pins[] = {
2013 /* RX, TX */
2014 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2015};
2016static const unsigned int hscif1_data_b_mux[] = {
2017 HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
2018};
2019static const unsigned int hscif1_ctrl_b_pins[] = {
2020 /* RTS, CTS */
2021 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2022};
2023static const unsigned int hscif1_ctrl_b_mux[] = {
2024 HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
2025};
2026/* - HSCIF2 ----------------------------------------------------------------- */
2027static const unsigned int hscif2_data_pins[] = {
2028 /* RX, TX */
2029 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2030};
2031static const unsigned int hscif2_data_mux[] = {
2032 HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
2033};
2034static const unsigned int hscif2_clk_pins[] = {
2035 /* SCK */
2036 RCAR_GP_PIN(0, 10),
2037};
2038static const unsigned int hscif2_clk_mux[] = {
2039 HSCIF2_HSCK_MARK,
2040};
2041static const unsigned int hscif2_ctrl_pins[] = {
2042 /* RTS, CTS */
2043 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2044};
2045static const unsigned int hscif2_ctrl_mux[] = {
2046 HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
2047};
2048/* - I2C0 ------------------------------------------------------------------- */
2049static const unsigned int i2c0_pins[] = {
2050 /* SCL, SDA */
2051 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2052};
2053static const unsigned int i2c0_mux[] = {
2054 I2C0_SCL_MARK, I2C0_SDA_MARK,
2055};
2056static const unsigned int i2c0_b_pins[] = {
2057 /* SCL, SDA */
2058 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2059};
2060static const unsigned int i2c0_b_mux[] = {
2061 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2062};
2063static const unsigned int i2c0_c_pins[] = {
2064 /* SCL, SDA */
2065 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2066};
2067static const unsigned int i2c0_c_mux[] = {
2068 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2069};
2070static const unsigned int i2c0_d_pins[] = {
2071 /* SCL, SDA */
2072 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2073};
2074static const unsigned int i2c0_d_mux[] = {
2075 I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
2076};
2077static const unsigned int i2c0_e_pins[] = {
2078 /* SCL, SDA */
2079 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2080};
2081static const unsigned int i2c0_e_mux[] = {
2082 I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
2083};
2084/* - I2C1 ------------------------------------------------------------------- */
2085static const unsigned int i2c1_pins[] = {
2086 /* SCL, SDA */
2087 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2088};
2089static const unsigned int i2c1_mux[] = {
2090 I2C1_SCL_MARK, I2C1_SDA_MARK,
2091};
2092static const unsigned int i2c1_b_pins[] = {
2093 /* SCL, SDA */
2094 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2095};
2096static const unsigned int i2c1_b_mux[] = {
2097 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2098};
2099static const unsigned int i2c1_c_pins[] = {
2100 /* SCL, SDA */
2101 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2102};
2103static const unsigned int i2c1_c_mux[] = {
2104 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2105};
2106static const unsigned int i2c1_d_pins[] = {
2107 /* SCL, SDA */
2108 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2109};
2110static const unsigned int i2c1_d_mux[] = {
2111 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2112};
2113static const unsigned int i2c1_e_pins[] = {
2114 /* SCL, SDA */
2115 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2116};
2117static const unsigned int i2c1_e_mux[] = {
2118 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2119};
2120/* - I2C2 ------------------------------------------------------------------- */
2121static const unsigned int i2c2_pins[] = {
2122 /* SCL, SDA */
2123 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2124};
2125static const unsigned int i2c2_mux[] = {
2126 I2C2_SCL_MARK, I2C2_SDA_MARK,
2127};
2128static const unsigned int i2c2_b_pins[] = {
2129 /* SCL, SDA */
2130 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2131};
2132static const unsigned int i2c2_b_mux[] = {
2133 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2134};
2135static const unsigned int i2c2_c_pins[] = {
2136 /* SCL, SDA */
2137 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2138};
2139static const unsigned int i2c2_c_mux[] = {
2140 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2141};
2142static const unsigned int i2c2_d_pins[] = {
2143 /* SCL, SDA */
2144 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2145};
2146static const unsigned int i2c2_d_mux[] = {
2147 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2148};
2149static const unsigned int i2c2_e_pins[] = {
2150 /* SCL, SDA */
2151 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2152};
2153static const unsigned int i2c2_e_mux[] = {
2154 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2155};
2156/* - I2C3 ------------------------------------------------------------------- */
2157static const unsigned int i2c3_pins[] = {
2158 /* SCL, SDA */
2159 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2160};
2161static const unsigned int i2c3_mux[] = {
2162 I2C3_SCL_MARK, I2C3_SDA_MARK,
2163};
2164static const unsigned int i2c3_b_pins[] = {
2165 /* SCL, SDA */
2166 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2167};
2168static const unsigned int i2c3_b_mux[] = {
2169 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2170};
2171static const unsigned int i2c3_c_pins[] = {
2172 /* SCL, SDA */
2173 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2174};
2175static const unsigned int i2c3_c_mux[] = {
2176 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2177};
2178static const unsigned int i2c3_d_pins[] = {
2179 /* SCL, SDA */
2180 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2181};
2182static const unsigned int i2c3_d_mux[] = {
2183 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2184};
2185static const unsigned int i2c3_e_pins[] = {
2186 /* SCL, SDA */
2187 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2188};
2189static const unsigned int i2c3_e_mux[] = {
2190 I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
2191};
2192/* - I2C4 ------------------------------------------------------------------- */
2193static const unsigned int i2c4_pins[] = {
2194 /* SCL, SDA */
2195 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2196};
2197static const unsigned int i2c4_mux[] = {
2198 I2C4_SCL_MARK, I2C4_SDA_MARK,
2199};
2200static const unsigned int i2c4_b_pins[] = {
2201 /* SCL, SDA */
2202 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2203};
2204static const unsigned int i2c4_b_mux[] = {
2205 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2206};
2207static const unsigned int i2c4_c_pins[] = {
2208 /* SCL, SDA */
2209 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2210};
2211static const unsigned int i2c4_c_mux[] = {
2212 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2213};
2214static const unsigned int i2c4_d_pins[] = {
2215 /* SCL, SDA */
2216 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2217};
2218static const unsigned int i2c4_d_mux[] = {
2219 I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2220};
2221static const unsigned int i2c4_e_pins[] = {
2222 /* SCL, SDA */
2223 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2224};
2225static const unsigned int i2c4_e_mux[] = {
2226 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2227};
2228/* - I2C5 ------------------------------------------------------------------- */
2229static const unsigned int i2c5_pins[] = {
2230 /* SCL, SDA */
2231 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2232};
2233static const unsigned int i2c5_mux[] = {
2234 I2C5_SCL_MARK, I2C5_SDA_MARK,
2235};
2236static const unsigned int i2c5_b_pins[] = {
2237 /* SCL, SDA */
2238 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2239};
2240static const unsigned int i2c5_b_mux[] = {
2241 I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
2242};
2243static const unsigned int i2c5_c_pins[] = {
2244 /* SCL, SDA */
2245 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2246};
2247static const unsigned int i2c5_c_mux[] = {
2248 I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
2249};
2250static const unsigned int i2c5_d_pins[] = {
2251 /* SCL, SDA */
2252 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2253};
2254static const unsigned int i2c5_d_mux[] = {
2255 I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
2256};
2257/* - INTC ------------------------------------------------------------------- */
2258static const unsigned int intc_irq0_pins[] = {
2259 /* IRQ0 */
2260 RCAR_GP_PIN(4, 4),
2261};
2262static const unsigned int intc_irq0_mux[] = {
2263 IRQ0_MARK,
2264};
2265static const unsigned int intc_irq1_pins[] = {
2266 /* IRQ1 */
2267 RCAR_GP_PIN(4, 18),
2268};
2269static const unsigned int intc_irq1_mux[] = {
2270 IRQ1_MARK,
2271};
2272static const unsigned int intc_irq2_pins[] = {
2273 /* IRQ2 */
2274 RCAR_GP_PIN(4, 19),
2275};
2276static const unsigned int intc_irq2_mux[] = {
2277 IRQ2_MARK,
2278};
2279static const unsigned int intc_irq3_pins[] = {
2280 /* IRQ3 */
2281 RCAR_GP_PIN(0, 7),
2282};
2283static const unsigned int intc_irq3_mux[] = {
2284 IRQ3_MARK,
2285};
2286static const unsigned int intc_irq4_pins[] = {
2287 /* IRQ4 */
2288 RCAR_GP_PIN(0, 0),
2289};
2290static const unsigned int intc_irq4_mux[] = {
2291 IRQ4_MARK,
2292};
2293static const unsigned int intc_irq5_pins[] = {
2294 /* IRQ5 */
2295 RCAR_GP_PIN(4, 1),
2296};
2297static const unsigned int intc_irq5_mux[] = {
2298 IRQ5_MARK,
2299};
2300static const unsigned int intc_irq6_pins[] = {
2301 /* IRQ6 */
2302 RCAR_GP_PIN(0, 10),
2303};
2304static const unsigned int intc_irq6_mux[] = {
2305 IRQ6_MARK,
2306};
2307static const unsigned int intc_irq7_pins[] = {
2308 /* IRQ7 */
2309 RCAR_GP_PIN(6, 15),
2310};
2311static const unsigned int intc_irq7_mux[] = {
2312 IRQ7_MARK,
2313};
2314static const unsigned int intc_irq8_pins[] = {
2315 /* IRQ8 */
2316 RCAR_GP_PIN(5, 0),
2317};
2318static const unsigned int intc_irq8_mux[] = {
2319 IRQ8_MARK,
2320};
2321static const unsigned int intc_irq9_pins[] = {
2322 /* IRQ9 */
2323 RCAR_GP_PIN(5, 10),
2324};
2325static const unsigned int intc_irq9_mux[] = {
2326 IRQ9_MARK,
2327};
2328/* - MMCIF ------------------------------------------------------------------ */
2329static const unsigned int mmc_data1_pins[] = {
2330 /* D[0] */
2331 RCAR_GP_PIN(6, 18),
2332};
2333static const unsigned int mmc_data1_mux[] = {
2334 MMC_D0_MARK,
2335};
2336static const unsigned int mmc_data4_pins[] = {
2337 /* D[0:3] */
2338 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2339 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2340};
2341static const unsigned int mmc_data4_mux[] = {
2342 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2343};
2344static const unsigned int mmc_data8_pins[] = {
2345 /* D[0:7] */
2346 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2347 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2348 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2349 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2350};
2351static const unsigned int mmc_data8_mux[] = {
2352 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2353 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2354};
2355static const unsigned int mmc_ctrl_pins[] = {
2356 /* CLK, CMD */
2357 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2358};
2359static const unsigned int mmc_ctrl_mux[] = {
2360 MMC_CLK_MARK, MMC_CMD_MARK,
2361};
2362/* - MSIOF0 ----------------------------------------------------------------- */
2363static const unsigned int msiof0_clk_pins[] = {
2364 /* SCK */
2365 RCAR_GP_PIN(4, 4),
2366};
2367static const unsigned int msiof0_clk_mux[] = {
2368 MSIOF0_SCK_MARK,
2369};
2370static const unsigned int msiof0_sync_pins[] = {
2371 /* SYNC */
2372 RCAR_GP_PIN(4, 5),
2373};
2374static const unsigned int msiof0_sync_mux[] = {
2375 MSIOF0_SYNC_MARK,
2376};
2377static const unsigned int msiof0_ss1_pins[] = {
2378 /* SS1 */
2379 RCAR_GP_PIN(4, 6),
2380};
2381static const unsigned int msiof0_ss1_mux[] = {
2382 MSIOF0_SS1_MARK,
2383};
2384static const unsigned int msiof0_ss2_pins[] = {
2385 /* SS2 */
2386 RCAR_GP_PIN(4, 7),
2387};
2388static const unsigned int msiof0_ss2_mux[] = {
2389 MSIOF0_SS2_MARK,
2390};
2391static const unsigned int msiof0_rx_pins[] = {
2392 /* RXD */
2393 RCAR_GP_PIN(4, 2),
2394};
2395static const unsigned int msiof0_rx_mux[] = {
2396 MSIOF0_RXD_MARK,
2397};
2398static const unsigned int msiof0_tx_pins[] = {
2399 /* TXD */
2400 RCAR_GP_PIN(4, 3),
2401};
2402static const unsigned int msiof0_tx_mux[] = {
2403 MSIOF0_TXD_MARK,
2404};
2405/* - MSIOF1 ----------------------------------------------------------------- */
2406static const unsigned int msiof1_clk_pins[] = {
2407 /* SCK */
2408 RCAR_GP_PIN(0, 26),
2409};
2410static const unsigned int msiof1_clk_mux[] = {
2411 MSIOF1_SCK_MARK,
2412};
2413static const unsigned int msiof1_sync_pins[] = {
2414 /* SYNC */
2415 RCAR_GP_PIN(0, 27),
2416};
2417static const unsigned int msiof1_sync_mux[] = {
2418 MSIOF1_SYNC_MARK,
2419};
2420static const unsigned int msiof1_ss1_pins[] = {
2421 /* SS1 */
2422 RCAR_GP_PIN(0, 28),
2423};
2424static const unsigned int msiof1_ss1_mux[] = {
2425 MSIOF1_SS1_MARK,
2426};
2427static const unsigned int msiof1_ss2_pins[] = {
2428 /* SS2 */
2429 RCAR_GP_PIN(0, 29),
2430};
2431static const unsigned int msiof1_ss2_mux[] = {
2432 MSIOF1_SS2_MARK,
2433};
2434static const unsigned int msiof1_rx_pins[] = {
2435 /* RXD */
2436 RCAR_GP_PIN(0, 24),
2437};
2438static const unsigned int msiof1_rx_mux[] = {
2439 MSIOF1_RXD_MARK,
2440};
2441static const unsigned int msiof1_tx_pins[] = {
2442 /* TXD */
2443 RCAR_GP_PIN(0, 25),
2444};
2445static const unsigned int msiof1_tx_mux[] = {
2446 MSIOF1_TXD_MARK,
2447};
2448static const unsigned int msiof1_clk_b_pins[] = {
2449 /* SCK */
2450 RCAR_GP_PIN(5, 3),
2451};
2452static const unsigned int msiof1_clk_b_mux[] = {
2453 MSIOF1_SCK_B_MARK,
2454};
2455static const unsigned int msiof1_sync_b_pins[] = {
2456 /* SYNC */
2457 RCAR_GP_PIN(5, 4),
2458};
2459static const unsigned int msiof1_sync_b_mux[] = {
2460 MSIOF1_SYNC_B_MARK,
2461};
2462static const unsigned int msiof1_ss1_b_pins[] = {
2463 /* SS1 */
2464 RCAR_GP_PIN(5, 5),
2465};
2466static const unsigned int msiof1_ss1_b_mux[] = {
2467 MSIOF1_SS1_B_MARK,
2468};
2469static const unsigned int msiof1_ss2_b_pins[] = {
2470 /* SS2 */
2471 RCAR_GP_PIN(5, 6),
2472};
2473static const unsigned int msiof1_ss2_b_mux[] = {
2474 MSIOF1_SS2_B_MARK,
2475};
2476static const unsigned int msiof1_rx_b_pins[] = {
2477 /* RXD */
2478 RCAR_GP_PIN(5, 1),
2479};
2480static const unsigned int msiof1_rx_b_mux[] = {
2481 MSIOF1_RXD_B_MARK,
2482};
2483static const unsigned int msiof1_tx_b_pins[] = {
2484 /* TXD */
2485 RCAR_GP_PIN(5, 2),
2486};
2487static const unsigned int msiof1_tx_b_mux[] = {
2488 MSIOF1_TXD_B_MARK,
2489};
2490/* - MSIOF2 ----------------------------------------------------------------- */
2491static const unsigned int msiof2_clk_pins[] = {
2492 /* SCK */
2493 RCAR_GP_PIN(1, 0),
2494};
2495static const unsigned int msiof2_clk_mux[] = {
2496 MSIOF2_SCK_MARK,
2497};
2498static const unsigned int msiof2_sync_pins[] = {
2499 /* SYNC */
2500 RCAR_GP_PIN(1, 1),
2501};
2502static const unsigned int msiof2_sync_mux[] = {
2503 MSIOF2_SYNC_MARK,
2504};
2505static const unsigned int msiof2_ss1_pins[] = {
2506 /* SS1 */
2507 RCAR_GP_PIN(1, 2),
2508};
2509static const unsigned int msiof2_ss1_mux[] = {
2510 MSIOF2_SS1_MARK,
2511};
2512static const unsigned int msiof2_ss2_pins[] = {
2513 /* SS2 */
2514 RCAR_GP_PIN(1, 3),
2515};
2516static const unsigned int msiof2_ss2_mux[] = {
2517 MSIOF2_SS2_MARK,
2518};
2519static const unsigned int msiof2_rx_pins[] = {
2520 /* RXD */
2521 RCAR_GP_PIN(0, 30),
2522};
2523static const unsigned int msiof2_rx_mux[] = {
2524 MSIOF2_RXD_MARK,
2525};
2526static const unsigned int msiof2_tx_pins[] = {
2527 /* TXD */
2528 RCAR_GP_PIN(0, 31),
2529};
2530static const unsigned int msiof2_tx_mux[] = {
2531 MSIOF2_TXD_MARK,
2532};
2533static const unsigned int msiof2_clk_b_pins[] = {
2534 /* SCK */
2535 RCAR_GP_PIN(3, 15),
2536};
2537static const unsigned int msiof2_clk_b_mux[] = {
2538 MSIOF2_SCK_B_MARK,
2539};
2540static const unsigned int msiof2_sync_b_pins[] = {
2541 /* SYNC */
2542 RCAR_GP_PIN(3, 16),
2543};
2544static const unsigned int msiof2_sync_b_mux[] = {
2545 MSIOF2_SYNC_B_MARK,
2546};
2547static const unsigned int msiof2_ss1_b_pins[] = {
2548 /* SS1 */
2549 RCAR_GP_PIN(3, 17),
2550};
2551static const unsigned int msiof2_ss1_b_mux[] = {
2552 MSIOF2_SS1_B_MARK,
2553};
2554static const unsigned int msiof2_ss2_b_pins[] = {
2555 /* SS2 */
2556 RCAR_GP_PIN(3, 18),
2557};
2558static const unsigned int msiof2_ss2_b_mux[] = {
2559 MSIOF2_SS2_B_MARK,
2560};
2561static const unsigned int msiof2_rx_b_pins[] = {
2562 /* RXD */
2563 RCAR_GP_PIN(3, 13),
2564};
2565static const unsigned int msiof2_rx_b_mux[] = {
2566 MSIOF2_RXD_B_MARK,
2567};
2568static const unsigned int msiof2_tx_b_pins[] = {
2569 /* TXD */
2570 RCAR_GP_PIN(3, 14),
2571};
2572static const unsigned int msiof2_tx_b_mux[] = {
2573 MSIOF2_TXD_B_MARK,
2574};
2575/* - PWM -------------------------------------------------------------------- */
2576static const unsigned int pwm0_pins[] = {
2577 RCAR_GP_PIN(1, 14),
2578};
2579static const unsigned int pwm0_mux[] = {
2580 PWM0_MARK,
2581};
2582static const unsigned int pwm0_b_pins[] = {
2583 RCAR_GP_PIN(5, 3),
2584};
2585static const unsigned int pwm0_b_mux[] = {
2586 PWM0_B_MARK,
2587};
2588static const unsigned int pwm1_pins[] = {
2589 RCAR_GP_PIN(4, 5),
2590};
2591static const unsigned int pwm1_mux[] = {
2592 PWM1_MARK,
2593};
2594static const unsigned int pwm1_b_pins[] = {
2595 RCAR_GP_PIN(5, 10),
2596};
2597static const unsigned int pwm1_b_mux[] = {
2598 PWM1_B_MARK,
2599};
2600static const unsigned int pwm1_c_pins[] = {
2601 RCAR_GP_PIN(1, 18),
2602};
2603static const unsigned int pwm1_c_mux[] = {
2604 PWM1_C_MARK,
2605};
2606static const unsigned int pwm2_pins[] = {
2607 RCAR_GP_PIN(4, 10),
2608};
2609static const unsigned int pwm2_mux[] = {
2610 PWM2_MARK,
2611};
2612static const unsigned int pwm2_b_pins[] = {
2613 RCAR_GP_PIN(5, 17),
2614};
2615static const unsigned int pwm2_b_mux[] = {
2616 PWM2_B_MARK,
2617};
2618static const unsigned int pwm2_c_pins[] = {
2619 RCAR_GP_PIN(0, 13),
2620};
2621static const unsigned int pwm2_c_mux[] = {
2622 PWM2_C_MARK,
2623};
2624static const unsigned int pwm3_pins[] = {
2625 RCAR_GP_PIN(4, 13),
2626};
2627static const unsigned int pwm3_mux[] = {
2628 PWM3_MARK,
2629};
2630static const unsigned int pwm3_b_pins[] = {
2631 RCAR_GP_PIN(0, 16),
2632};
2633static const unsigned int pwm3_b_mux[] = {
2634 PWM3_B_MARK,
2635};
2636static const unsigned int pwm4_pins[] = {
2637 RCAR_GP_PIN(1, 3),
2638};
2639static const unsigned int pwm4_mux[] = {
2640 PWM4_MARK,
2641};
2642static const unsigned int pwm4_b_pins[] = {
2643 RCAR_GP_PIN(0, 21),
2644};
2645static const unsigned int pwm4_b_mux[] = {
2646 PWM4_B_MARK,
2647};
2648static const unsigned int pwm5_pins[] = {
2649 RCAR_GP_PIN(3, 30),
2650};
2651static const unsigned int pwm5_mux[] = {
2652 PWM5_MARK,
2653};
2654static const unsigned int pwm5_b_pins[] = {
2655 RCAR_GP_PIN(4, 0),
2656};
2657static const unsigned int pwm5_b_mux[] = {
2658 PWM5_B_MARK,
2659};
2660static const unsigned int pwm5_c_pins[] = {
2661 RCAR_GP_PIN(0, 10),
2662};
2663static const unsigned int pwm5_c_mux[] = {
2664 PWM5_C_MARK,
2665};
2666static const unsigned int pwm6_pins[] = {
2667 RCAR_GP_PIN(4, 8),
2668};
2669static const unsigned int pwm6_mux[] = {
2670 PWM6_MARK,
2671};
2672static const unsigned int pwm6_b_pins[] = {
2673 RCAR_GP_PIN(0, 7),
2674};
2675static const unsigned int pwm6_b_mux[] = {
2676 PWM6_B_MARK,
2677};
2678/* - QSPI ------------------------------------------------------------------- */
2679static const unsigned int qspi_ctrl_pins[] = {
2680 /* SPCLK, SSL */
2681 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2682};
2683static const unsigned int qspi_ctrl_mux[] = {
2684 SPCLK_MARK, SSL_MARK,
2685};
2686static const unsigned int qspi_data2_pins[] = {
2687 /* MOSI_IO0, MISO_IO1 */
2688 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2689};
2690static const unsigned int qspi_data2_mux[] = {
2691 MOSI_IO0_MARK, MISO_IO1_MARK,
2692};
2693static const unsigned int qspi_data4_pins[] = {
2694 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2695 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2696 RCAR_GP_PIN(1, 8),
2697};
2698static const unsigned int qspi_data4_mux[] = {
2699 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2700};
2701/* - SCIF0 ------------------------------------------------------------------ */
2702static const unsigned int scif0_data_pins[] = {
2703 /* RX, TX */
2704 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2705};
2706static const unsigned int scif0_data_mux[] = {
2707 SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2708};
2709static const unsigned int scif0_data_b_pins[] = {
2710 /* RX, TX */
2711 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2712};
2713static const unsigned int scif0_data_b_mux[] = {
2714 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2715};
2716static const unsigned int scif0_data_c_pins[] = {
2717 /* RX, TX */
2718 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2719};
2720static const unsigned int scif0_data_c_mux[] = {
2721 SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2722};
2723static const unsigned int scif0_data_d_pins[] = {
2724 /* RX, TX */
2725 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2726};
2727static const unsigned int scif0_data_d_mux[] = {
2728 SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2729};
2730/* - SCIF1 ------------------------------------------------------------------ */
2731static const unsigned int scif1_data_pins[] = {
2732 /* RX, TX */
2733 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2734};
2735static const unsigned int scif1_data_mux[] = {
2736 SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2737};
2738static const unsigned int scif1_clk_pins[] = {
2739 /* SCK */
2740 RCAR_GP_PIN(4, 13),
2741};
2742static const unsigned int scif1_clk_mux[] = {
2743 SCIF1_SCK_MARK,
2744};
2745static const unsigned int scif1_data_b_pins[] = {
2746 /* RX, TX */
2747 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2748};
2749static const unsigned int scif1_data_b_mux[] = {
2750 SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2751};
2752static const unsigned int scif1_clk_b_pins[] = {
2753 /* SCK */
2754 RCAR_GP_PIN(5, 10),
2755};
2756static const unsigned int scif1_clk_b_mux[] = {
2757 SCIF1_SCK_B_MARK,
2758};
2759static const unsigned int scif1_data_c_pins[] = {
2760 /* RX, TX */
2761 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2762};
2763static const unsigned int scif1_data_c_mux[] = {
2764 SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2765};
2766static const unsigned int scif1_clk_c_pins[] = {
2767 /* SCK */
2768 RCAR_GP_PIN(0, 10),
2769};
2770static const unsigned int scif1_clk_c_mux[] = {
2771 SCIF1_SCK_C_MARK,
2772};
2773/* - SCIF2 ------------------------------------------------------------------ */
2774static const unsigned int scif2_data_pins[] = {
2775 /* RX, TX */
2776 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2777};
2778static const unsigned int scif2_data_mux[] = {
2779 SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2780};
2781static const unsigned int scif2_clk_pins[] = {
2782 /* SCK */
2783 RCAR_GP_PIN(4, 18),
2784};
2785static const unsigned int scif2_clk_mux[] = {
2786 SCIF2_SCK_MARK,
2787};
2788static const unsigned int scif2_data_b_pins[] = {
2789 /* RX, TX */
2790 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2791};
2792static const unsigned int scif2_data_b_mux[] = {
2793 SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2794};
2795static const unsigned int scif2_clk_b_pins[] = {
2796 /* SCK */
2797 RCAR_GP_PIN(5, 17),
2798};
2799static const unsigned int scif2_clk_b_mux[] = {
2800 SCIF2_SCK_B_MARK,
2801};
2802static const unsigned int scif2_data_c_pins[] = {
2803 /* RX, TX */
2804 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2805};
2806static const unsigned int scif2_data_c_mux[] = {
2807 SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2808};
2809static const unsigned int scif2_clk_c_pins[] = {
2810 /* SCK */
2811 RCAR_GP_PIN(3, 19),
2812};
2813static const unsigned int scif2_clk_c_mux[] = {
2814 SCIF2_SCK_C_MARK,
2815};
2816/* - SCIF3 ------------------------------------------------------------------ */
2817static const unsigned int scif3_data_pins[] = {
2818 /* RX, TX */
2819 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2820};
2821static const unsigned int scif3_data_mux[] = {
2822 SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2823};
2824static const unsigned int scif3_clk_pins[] = {
2825 /* SCK */
2826 RCAR_GP_PIN(4, 19),
2827};
2828static const unsigned int scif3_clk_mux[] = {
2829 SCIF3_SCK_MARK,
2830};
2831static const unsigned int scif3_data_b_pins[] = {
2832 /* RX, TX */
2833 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2834};
2835static const unsigned int scif3_data_b_mux[] = {
2836 SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2837};
2838static const unsigned int scif3_clk_b_pins[] = {
2839 /* SCK */
2840 RCAR_GP_PIN(3, 22),
2841};
2842static const unsigned int scif3_clk_b_mux[] = {
2843 SCIF3_SCK_B_MARK,
2844};
2845/* - SCIF4 ------------------------------------------------------------------ */
2846static const unsigned int scif4_data_pins[] = {
2847 /* RX, TX */
2848 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2849};
2850static const unsigned int scif4_data_mux[] = {
2851 SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2852};
2853static const unsigned int scif4_data_b_pins[] = {
2854 /* RX, TX */
2855 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2856};
2857static const unsigned int scif4_data_b_mux[] = {
2858 SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2859};
2860static const unsigned int scif4_data_c_pins[] = {
2861 /* RX, TX */
2862 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2863};
2864static const unsigned int scif4_data_c_mux[] = {
2865 SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2866};
2867static const unsigned int scif4_data_d_pins[] = {
2868 /* RX, TX */
2869 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2870};
2871static const unsigned int scif4_data_d_mux[] = {
2872 SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2873};
2874static const unsigned int scif4_data_e_pins[] = {
2875 /* RX, TX */
2876 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2877};
2878static const unsigned int scif4_data_e_mux[] = {
2879 SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2880};
2881/* - SCIF5 ------------------------------------------------------------------ */
2882static const unsigned int scif5_data_pins[] = {
2883 /* RX, TX */
2884 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2885};
2886static const unsigned int scif5_data_mux[] = {
2887 SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2888};
2889static const unsigned int scif5_data_b_pins[] = {
2890 /* RX, TX */
2891 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2892};
2893static const unsigned int scif5_data_b_mux[] = {
2894 SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2895};
2896static const unsigned int scif5_data_c_pins[] = {
2897 /* RX, TX */
2898 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2899};
2900static const unsigned int scif5_data_c_mux[] = {
2901 SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2902};
2903static const unsigned int scif5_data_d_pins[] = {
2904 /* RX, TX */
2905 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2906};
2907static const unsigned int scif5_data_d_mux[] = {
2908 SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2909};
2910/* - SCIFA0 ----------------------------------------------------------------- */
2911static const unsigned int scifa0_data_pins[] = {
2912 /* RXD, TXD */
2913 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2914};
2915static const unsigned int scifa0_data_mux[] = {
2916 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2917};
2918static const unsigned int scifa0_data_b_pins[] = {
2919 /* RXD, TXD */
2920 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2921};
2922static const unsigned int scifa0_data_b_mux[] = {
2923 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2924};
2925static const unsigned int scifa0_data_c_pins[] = {
2926 /* RXD, TXD */
2927 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2928};
2929static const unsigned int scifa0_data_c_mux[] = {
2930 SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2931};
2932static const unsigned int scifa0_data_d_pins[] = {
2933 /* RXD, TXD */
2934 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2935};
2936static const unsigned int scifa0_data_d_mux[] = {
2937 SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2938};
2939/* - SCIFA1 ----------------------------------------------------------------- */
2940static const unsigned int scifa1_data_pins[] = {
2941 /* RXD, TXD */
2942 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2943};
2944static const unsigned int scifa1_data_mux[] = {
2945 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2946};
2947static const unsigned int scifa1_clk_pins[] = {
2948 /* SCK */
2949 RCAR_GP_PIN(0, 13),
2950};
2951static const unsigned int scifa1_clk_mux[] = {
2952 SCIFA1_SCK_MARK,
2953};
2954static const unsigned int scifa1_data_b_pins[] = {
2955 /* RXD, TXD */
2956 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2957};
2958static const unsigned int scifa1_data_b_mux[] = {
2959 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2960};
2961static const unsigned int scifa1_clk_b_pins[] = {
2962 /* SCK */
2963 RCAR_GP_PIN(4, 27),
2964};
2965static const unsigned int scifa1_clk_b_mux[] = {
2966 SCIFA1_SCK_B_MARK,
2967};
2968static const unsigned int scifa1_data_c_pins[] = {
2969 /* RXD, TXD */
2970 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2971};
2972static const unsigned int scifa1_data_c_mux[] = {
2973 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2974};
2975static const unsigned int scifa1_clk_c_pins[] = {
2976 /* SCK */
2977 RCAR_GP_PIN(5, 4),
2978};
2979static const unsigned int scifa1_clk_c_mux[] = {
2980 SCIFA1_SCK_C_MARK,
2981};
2982/* - SCIFA2 ----------------------------------------------------------------- */
2983static const unsigned int scifa2_data_pins[] = {
2984 /* RXD, TXD */
2985 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2986};
2987static const unsigned int scifa2_data_mux[] = {
2988 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2989};
2990static const unsigned int scifa2_clk_pins[] = {
2991 /* SCK */
2992 RCAR_GP_PIN(1, 15),
2993};
2994static const unsigned int scifa2_clk_mux[] = {
2995 SCIFA2_SCK_MARK,
2996};
2997static const unsigned int scifa2_data_b_pins[] = {
2998 /* RXD, TXD */
2999 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
3000};
3001static const unsigned int scifa2_data_b_mux[] = {
3002 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3003};
3004static const unsigned int scifa2_clk_b_pins[] = {
3005 /* SCK */
3006 RCAR_GP_PIN(4, 30),
3007};
3008static const unsigned int scifa2_clk_b_mux[] = {
3009 SCIFA2_SCK_B_MARK,
3010};
3011/* - SCIFA3 ----------------------------------------------------------------- */
3012static const unsigned int scifa3_data_pins[] = {
3013 /* RXD, TXD */
3014 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3015};
3016static const unsigned int scifa3_data_mux[] = {
3017 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3018};
3019static const unsigned int scifa3_clk_pins[] = {
3020 /* SCK */
3021 RCAR_GP_PIN(4, 24),
3022};
3023static const unsigned int scifa3_clk_mux[] = {
3024 SCIFA3_SCK_MARK,
3025};
3026static const unsigned int scifa3_data_b_pins[] = {
3027 /* RXD, TXD */
3028 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
3029};
3030static const unsigned int scifa3_data_b_mux[] = {
3031 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3032};
3033static const unsigned int scifa3_clk_b_pins[] = {
3034 /* SCK */
3035 RCAR_GP_PIN(0, 0),
3036};
3037static const unsigned int scifa3_clk_b_mux[] = {
3038 SCIFA3_SCK_B_MARK,
3039};
3040/* - SCIFA4 ----------------------------------------------------------------- */
3041static const unsigned int scifa4_data_pins[] = {
3042 /* RXD, TXD */
3043 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
3044};
3045static const unsigned int scifa4_data_mux[] = {
3046 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3047};
3048static const unsigned int scifa4_data_b_pins[] = {
3049 /* RXD, TXD */
3050 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
3051};
3052static const unsigned int scifa4_data_b_mux[] = {
3053 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3054};
3055static const unsigned int scifa4_data_c_pins[] = {
3056 /* RXD, TXD */
3057 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3058};
3059static const unsigned int scifa4_data_c_mux[] = {
3060 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3061};
3062static const unsigned int scifa4_data_d_pins[] = {
3063 /* RXD, TXD */
3064 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3065};
3066static const unsigned int scifa4_data_d_mux[] = {
3067 SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
3068};
3069/* - SCIFA5 ----------------------------------------------------------------- */
3070static const unsigned int scifa5_data_pins[] = {
3071 /* RXD, TXD */
3072 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3073};
3074static const unsigned int scifa5_data_mux[] = {
3075 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3076};
3077static const unsigned int scifa5_data_b_pins[] = {
3078 /* RXD, TXD */
3079 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
3080};
3081static const unsigned int scifa5_data_b_mux[] = {
3082 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3083};
3084static const unsigned int scifa5_data_c_pins[] = {
3085 /* RXD, TXD */
3086 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
3087};
3088static const unsigned int scifa5_data_c_mux[] = {
3089 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3090};
3091static const unsigned int scifa5_data_d_pins[] = {
3092 /* RXD, TXD */
3093 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3094};
3095static const unsigned int scifa5_data_d_mux[] = {
3096 SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
3097};
3098/* - SCIFB0 ----------------------------------------------------------------- */
3099static const unsigned int scifb0_data_pins[] = {
3100 /* RXD, TXD */
3101 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
3102};
3103static const unsigned int scifb0_data_mux[] = {
3104 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3105};
3106static const unsigned int scifb0_clk_pins[] = {
3107 /* SCK */
3108 RCAR_GP_PIN(0, 19),
3109};
3110static const unsigned int scifb0_clk_mux[] = {
3111 SCIFB0_SCK_MARK,
3112};
3113static const unsigned int scifb0_ctrl_pins[] = {
3114 /* RTS, CTS */
3115 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
3116};
3117static const unsigned int scifb0_ctrl_mux[] = {
3118 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3119};
3120/* - SCIFB1 ----------------------------------------------------------------- */
3121static const unsigned int scifb1_data_pins[] = {
3122 /* RXD, TXD */
3123 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
3124};
3125static const unsigned int scifb1_data_mux[] = {
3126 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3127};
3128static const unsigned int scifb1_clk_pins[] = {
3129 /* SCK */
3130 RCAR_GP_PIN(0, 16),
3131};
3132static const unsigned int scifb1_clk_mux[] = {
3133 SCIFB1_SCK_MARK,
3134};
3135/* - SCIFB2 ----------------------------------------------------------------- */
3136static const unsigned int scifb2_data_pins[] = {
3137 /* RXD, TXD */
3138 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3139};
3140static const unsigned int scifb2_data_mux[] = {
3141 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3142};
3143static const unsigned int scifb2_clk_pins[] = {
3144 /* SCK */
3145 RCAR_GP_PIN(1, 15),
3146};
3147static const unsigned int scifb2_clk_mux[] = {
3148 SCIFB2_SCK_MARK,
3149};
3150static const unsigned int scifb2_ctrl_pins[] = {
3151 /* RTS, CTS */
3152 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
3153};
3154static const unsigned int scifb2_ctrl_mux[] = {
3155 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3156};
3157/* - SCIF Clock ------------------------------------------------------------- */
3158static const unsigned int scif_clk_pins[] = {
3159 /* SCIF_CLK */
3160 RCAR_GP_PIN(1, 23),
3161};
3162static const unsigned int scif_clk_mux[] = {
3163 SCIF_CLK_MARK,
3164};
3165static const unsigned int scif_clk_b_pins[] = {
3166 /* SCIF_CLK */
3167 RCAR_GP_PIN(3, 29),
3168};
3169static const unsigned int scif_clk_b_mux[] = {
3170 SCIF_CLK_B_MARK,
3171};
3172/* - SDHI0 ------------------------------------------------------------------ */
3173static const unsigned int sdhi0_data1_pins[] = {
3174 /* D0 */
3175 RCAR_GP_PIN(6, 2),
3176};
3177static const unsigned int sdhi0_data1_mux[] = {
3178 SD0_DATA0_MARK,
3179};
3180static const unsigned int sdhi0_data4_pins[] = {
3181 /* D[0:3] */
3182 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3183 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3184};
3185static const unsigned int sdhi0_data4_mux[] = {
3186 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3187};
3188static const unsigned int sdhi0_ctrl_pins[] = {
3189 /* CLK, CMD */
3190 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3191};
3192static const unsigned int sdhi0_ctrl_mux[] = {
3193 SD0_CLK_MARK, SD0_CMD_MARK,
3194};
3195static const unsigned int sdhi0_cd_pins[] = {
3196 /* CD */
3197 RCAR_GP_PIN(6, 6),
3198};
3199static const unsigned int sdhi0_cd_mux[] = {
3200 SD0_CD_MARK,
3201};
3202static const unsigned int sdhi0_wp_pins[] = {
3203 /* WP */
3204 RCAR_GP_PIN(6, 7),
3205};
3206static const unsigned int sdhi0_wp_mux[] = {
3207 SD0_WP_MARK,
3208};
3209/* - SDHI1 ------------------------------------------------------------------ */
3210static const unsigned int sdhi1_data1_pins[] = {
3211 /* D0 */
3212 RCAR_GP_PIN(6, 10),
3213};
3214static const unsigned int sdhi1_data1_mux[] = {
3215 SD1_DATA0_MARK,
3216};
3217static const unsigned int sdhi1_data4_pins[] = {
3218 /* D[0:3] */
3219 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3220 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3221};
3222static const unsigned int sdhi1_data4_mux[] = {
3223 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3224};
3225static const unsigned int sdhi1_ctrl_pins[] = {
3226 /* CLK, CMD */
3227 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3228};
3229static const unsigned int sdhi1_ctrl_mux[] = {
3230 SD1_CLK_MARK, SD1_CMD_MARK,
3231};
3232static const unsigned int sdhi1_cd_pins[] = {
3233 /* CD */
3234 RCAR_GP_PIN(6, 14),
3235};
3236static const unsigned int sdhi1_cd_mux[] = {
3237 SD1_CD_MARK,
3238};
3239static const unsigned int sdhi1_wp_pins[] = {
3240 /* WP */
3241 RCAR_GP_PIN(6, 15),
3242};
3243static const unsigned int sdhi1_wp_mux[] = {
3244 SD1_WP_MARK,
3245};
3246/* - SDHI2 ------------------------------------------------------------------ */
3247static const unsigned int sdhi2_data1_pins[] = {
3248 /* D0 */
3249 RCAR_GP_PIN(6, 18),
3250};
3251static const unsigned int sdhi2_data1_mux[] = {
3252 SD2_DATA0_MARK,
3253};
3254static const unsigned int sdhi2_data4_pins[] = {
3255 /* D[0:3] */
3256 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3257 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3258};
3259static const unsigned int sdhi2_data4_mux[] = {
3260 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3261};
3262static const unsigned int sdhi2_ctrl_pins[] = {
3263 /* CLK, CMD */
3264 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3265};
3266static const unsigned int sdhi2_ctrl_mux[] = {
3267 SD2_CLK_MARK, SD2_CMD_MARK,
3268};
3269static const unsigned int sdhi2_cd_pins[] = {
3270 /* CD */
3271 RCAR_GP_PIN(6, 22),
3272};
3273static const unsigned int sdhi2_cd_mux[] = {
3274 SD2_CD_MARK,
3275};
3276static const unsigned int sdhi2_wp_pins[] = {
3277 /* WP */
3278 RCAR_GP_PIN(6, 23),
3279};
3280static const unsigned int sdhi2_wp_mux[] = {
3281 SD2_WP_MARK,
3282};
3283/* - SSI -------------------------------------------------------------------- */
3284static const unsigned int ssi0_data_pins[] = {
3285 /* SDATA0 */
3286 RCAR_GP_PIN(5, 3),
3287};
3288static const unsigned int ssi0_data_mux[] = {
3289 SSI_SDATA0_MARK,
3290};
3291static const unsigned int ssi0129_ctrl_pins[] = {
3292 /* SCK0129, WS0129 */
3293 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3294};
3295static const unsigned int ssi0129_ctrl_mux[] = {
3296 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3297};
3298static const unsigned int ssi1_data_pins[] = {
3299 /* SDATA1 */
3300 RCAR_GP_PIN(5, 13),
3301};
3302static const unsigned int ssi1_data_mux[] = {
3303 SSI_SDATA1_MARK,
3304};
3305static const unsigned int ssi1_ctrl_pins[] = {
3306 /* SCK1, WS1 */
3307 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3308};
3309static const unsigned int ssi1_ctrl_mux[] = {
3310 SSI_SCK1_MARK, SSI_WS1_MARK,
3311};
3312static const unsigned int ssi1_data_b_pins[] = {
3313 /* SDATA1 */
3314 RCAR_GP_PIN(4, 13),
3315};
3316static const unsigned int ssi1_data_b_mux[] = {
3317 SSI_SDATA1_B_MARK,
3318};
3319static const unsigned int ssi1_ctrl_b_pins[] = {
3320 /* SCK1, WS1 */
3321 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3322};
3323static const unsigned int ssi1_ctrl_b_mux[] = {
3324 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3325};
3326static const unsigned int ssi2_data_pins[] = {
3327 /* SDATA2 */
3328 RCAR_GP_PIN(5, 16),
3329};
3330static const unsigned int ssi2_data_mux[] = {
3331 SSI_SDATA2_MARK,
3332};
3333static const unsigned int ssi2_ctrl_pins[] = {
3334 /* SCK2, WS2 */
3335 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3336};
3337static const unsigned int ssi2_ctrl_mux[] = {
3338 SSI_SCK2_MARK, SSI_WS2_MARK,
3339};
3340static const unsigned int ssi2_data_b_pins[] = {
3341 /* SDATA2 */
3342 RCAR_GP_PIN(4, 16),
3343};
3344static const unsigned int ssi2_data_b_mux[] = {
3345 SSI_SDATA2_B_MARK,
3346};
3347static const unsigned int ssi2_ctrl_b_pins[] = {
3348 /* SCK2, WS2 */
3349 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3350};
3351static const unsigned int ssi2_ctrl_b_mux[] = {
3352 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3353};
3354static const unsigned int ssi3_data_pins[] = {
3355 /* SDATA3 */
3356 RCAR_GP_PIN(5, 6),
3357};
3358static const unsigned int ssi3_data_mux[] = {
3359 SSI_SDATA3_MARK
3360};
3361static const unsigned int ssi34_ctrl_pins[] = {
3362 /* SCK34, WS34 */
3363 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3364};
3365static const unsigned int ssi34_ctrl_mux[] = {
3366 SSI_SCK34_MARK, SSI_WS34_MARK,
3367};
3368static const unsigned int ssi4_data_pins[] = {
3369 /* SDATA4 */
3370 RCAR_GP_PIN(5, 9),
3371};
3372static const unsigned int ssi4_data_mux[] = {
3373 SSI_SDATA4_MARK,
3374};
3375static const unsigned int ssi4_ctrl_pins[] = {
3376 /* SCK4, WS4 */
3377 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3378};
3379static const unsigned int ssi4_ctrl_mux[] = {
3380 SSI_SCK4_MARK, SSI_WS4_MARK,
3381};
3382static const unsigned int ssi4_data_b_pins[] = {
3383 /* SDATA4 */
3384 RCAR_GP_PIN(4, 22),
3385};
3386static const unsigned int ssi4_data_b_mux[] = {
3387 SSI_SDATA4_B_MARK,
3388};
3389static const unsigned int ssi4_ctrl_b_pins[] = {
3390 /* SCK4, WS4 */
3391 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3392};
3393static const unsigned int ssi4_ctrl_b_mux[] = {
3394 SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3395};
3396static const unsigned int ssi5_data_pins[] = {
3397 /* SDATA5 */
3398 RCAR_GP_PIN(4, 26),
3399};
3400static const unsigned int ssi5_data_mux[] = {
3401 SSI_SDATA5_MARK,
3402};
3403static const unsigned int ssi5_ctrl_pins[] = {
3404 /* SCK5, WS5 */
3405 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3406};
3407static const unsigned int ssi5_ctrl_mux[] = {
3408 SSI_SCK5_MARK, SSI_WS5_MARK,
3409};
3410static const unsigned int ssi5_data_b_pins[] = {
3411 /* SDATA5 */
3412 RCAR_GP_PIN(3, 21),
3413};
3414static const unsigned int ssi5_data_b_mux[] = {
3415 SSI_SDATA5_B_MARK,
3416};
3417static const unsigned int ssi5_ctrl_b_pins[] = {
3418 /* SCK5, WS5 */
3419 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3420};
3421static const unsigned int ssi5_ctrl_b_mux[] = {
3422 SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3423};
3424static const unsigned int ssi6_data_pins[] = {
3425 /* SDATA6 */
3426 RCAR_GP_PIN(4, 29),
3427};
3428static const unsigned int ssi6_data_mux[] = {
3429 SSI_SDATA6_MARK,
3430};
3431static const unsigned int ssi6_ctrl_pins[] = {
3432 /* SCK6, WS6 */
3433 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3434};
3435static const unsigned int ssi6_ctrl_mux[] = {
3436 SSI_SCK6_MARK, SSI_WS6_MARK,
3437};
3438static const unsigned int ssi6_data_b_pins[] = {
3439 /* SDATA6 */
3440 RCAR_GP_PIN(3, 24),
3441};
3442static const unsigned int ssi6_data_b_mux[] = {
3443 SSI_SDATA6_B_MARK,
3444};
3445static const unsigned int ssi6_ctrl_b_pins[] = {
3446 /* SCK6, WS6 */
3447 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3448};
3449static const unsigned int ssi6_ctrl_b_mux[] = {
3450 SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3451};
3452static const unsigned int ssi7_data_pins[] = {
3453 /* SDATA7 */
3454 RCAR_GP_PIN(5, 0),
3455};
3456static const unsigned int ssi7_data_mux[] = {
3457 SSI_SDATA7_MARK,
3458};
3459static const unsigned int ssi78_ctrl_pins[] = {
3460 /* SCK78, WS78 */
3461 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3462};
3463static const unsigned int ssi78_ctrl_mux[] = {
3464 SSI_SCK78_MARK, SSI_WS78_MARK,
3465};
3466static const unsigned int ssi7_data_b_pins[] = {
3467 /* SDATA7 */
3468 RCAR_GP_PIN(3, 27),
3469};
3470static const unsigned int ssi7_data_b_mux[] = {
3471 SSI_SDATA7_B_MARK,
3472};
3473static const unsigned int ssi78_ctrl_b_pins[] = {
3474 /* SCK78, WS78 */
3475 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3476};
3477static const unsigned int ssi78_ctrl_b_mux[] = {
3478 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3479};
3480static const unsigned int ssi8_data_pins[] = {
3481 /* SDATA8 */
3482 RCAR_GP_PIN(5, 10),
3483};
3484static const unsigned int ssi8_data_mux[] = {
3485 SSI_SDATA8_MARK,
3486};
3487static const unsigned int ssi8_data_b_pins[] = {
3488 /* SDATA8 */
3489 RCAR_GP_PIN(3, 28),
3490};
3491static const unsigned int ssi8_data_b_mux[] = {
3492 SSI_SDATA8_B_MARK,
3493};
3494static const unsigned int ssi9_data_pins[] = {
3495 /* SDATA9 */
3496 RCAR_GP_PIN(5, 19),
3497};
3498static const unsigned int ssi9_data_mux[] = {
3499 SSI_SDATA9_MARK,
3500};
3501static const unsigned int ssi9_ctrl_pins[] = {
3502 /* SCK9, WS9 */
3503 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3504};
3505static const unsigned int ssi9_ctrl_mux[] = {
3506 SSI_SCK9_MARK, SSI_WS9_MARK,
3507};
3508static const unsigned int ssi9_data_b_pins[] = {
3509 /* SDATA9 */
3510 RCAR_GP_PIN(4, 19),
3511};
3512static const unsigned int ssi9_data_b_mux[] = {
3513 SSI_SDATA9_B_MARK,
3514};
3515static const unsigned int ssi9_ctrl_b_pins[] = {
3516 /* SCK9, WS9 */
3517 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3518};
3519static const unsigned int ssi9_ctrl_b_mux[] = {
3520 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3521};
3522/* - TPU -------------------------------------------------------------------- */
3523static const unsigned int tpu_to0_pins[] = {
3524 RCAR_GP_PIN(3, 31),
3525};
3526static const unsigned int tpu_to0_mux[] = {
3527 TPUTO0_MARK,
3528};
3529static const unsigned int tpu_to0_b_pins[] = {
3530 RCAR_GP_PIN(3, 30),
3531};
3532static const unsigned int tpu_to0_b_mux[] = {
3533 TPUTO0_B_MARK,
3534};
3535static const unsigned int tpu_to0_c_pins[] = {
3536 RCAR_GP_PIN(1, 18),
3537};
3538static const unsigned int tpu_to0_c_mux[] = {
3539 TPUTO0_C_MARK,
3540};
3541static const unsigned int tpu_to1_pins[] = {
3542 RCAR_GP_PIN(4, 9),
3543};
3544static const unsigned int tpu_to1_mux[] = {
3545 TPUTO1_MARK,
3546};
3547static const unsigned int tpu_to1_b_pins[] = {
3548 RCAR_GP_PIN(4, 0),
3549};
3550static const unsigned int tpu_to1_b_mux[] = {
3551 TPUTO1_B_MARK,
3552};
3553static const unsigned int tpu_to1_c_pins[] = {
3554 RCAR_GP_PIN(4, 4),
3555};
3556static const unsigned int tpu_to1_c_mux[] = {
3557 TPUTO1_C_MARK,
3558};
3559static const unsigned int tpu_to2_pins[] = {
3560 RCAR_GP_PIN(1, 3),
3561};
3562static const unsigned int tpu_to2_mux[] = {
3563 TPUTO2_MARK,
3564};
3565static const unsigned int tpu_to2_b_pins[] = {
3566 RCAR_GP_PIN(1, 0),
3567};
3568static const unsigned int tpu_to2_b_mux[] = {
3569 TPUTO2_B_MARK,
3570};
3571static const unsigned int tpu_to2_c_pins[] = {
3572 RCAR_GP_PIN(0, 22),
3573};
3574static const unsigned int tpu_to2_c_mux[] = {
3575 TPUTO2_C_MARK,
3576};
3577static const unsigned int tpu_to3_pins[] = {
3578 RCAR_GP_PIN(1, 14),
3579};
3580static const unsigned int tpu_to3_mux[] = {
3581 TPUTO3_MARK,
3582};
3583static const unsigned int tpu_to3_b_pins[] = {
3584 RCAR_GP_PIN(1, 13),
3585};
3586static const unsigned int tpu_to3_b_mux[] = {
3587 TPUTO3_B_MARK,
3588};
3589static const unsigned int tpu_to3_c_pins[] = {
3590 RCAR_GP_PIN(0, 21),
3591};
3592static const unsigned int tpu_to3_c_mux[] = {
3593 TPUTO3_C_MARK,
3594};
3595/* - USB0 ------------------------------------------------------------------- */
3596static const unsigned int usb0_pins[] = {
3597 RCAR_GP_PIN(5, 24), /* PWEN */
3598 RCAR_GP_PIN(5, 25), /* OVC */
3599};
3600static const unsigned int usb0_mux[] = {
3601 USB0_PWEN_MARK,
3602 USB0_OVC_MARK,
3603};
3604/* - USB1 ------------------------------------------------------------------- */
3605static const unsigned int usb1_pins[] = {
3606 RCAR_GP_PIN(5, 26), /* PWEN */
3607 RCAR_GP_PIN(5, 27), /* OVC */
3608};
3609static const unsigned int usb1_mux[] = {
3610 USB1_PWEN_MARK,
3611 USB1_OVC_MARK,
3612};
3613/* - VIN0 ------------------------------------------------------------------- */
3614static const union vin_data vin0_data_pins = {
3615 .data24 = {
3616 /* B */
3617 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3618 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3619 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3620 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3621 /* G */
3622 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3623 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3624 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3625 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3626 /* R */
3627 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3628 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3629 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3630 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3631 },
3632};
3633static const union vin_data vin0_data_mux = {
3634 .data24 = {
3635 /* B */
3636 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3637 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3638 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3639 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3640 /* G */
3641 VI0_G0_MARK, VI0_G1_MARK,
3642 VI0_G2_MARK, VI0_G3_MARK,
3643 VI0_G4_MARK, VI0_G5_MARK,
3644 VI0_G6_MARK, VI0_G7_MARK,
3645 /* R */
3646 VI0_R0_MARK, VI0_R1_MARK,
3647 VI0_R2_MARK, VI0_R3_MARK,
3648 VI0_R4_MARK, VI0_R5_MARK,
3649 VI0_R6_MARK, VI0_R7_MARK,
3650 },
3651};
3652static const unsigned int vin0_data18_pins[] = {
3653 /* B */
3654 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3655 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3656 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3657 /* G */
3658 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3659 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3660 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3661 /* R */
3662 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3663 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3664 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3665};
3666static const unsigned int vin0_data18_mux[] = {
3667 /* B */
3668 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3669 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3670 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3671 /* G */
3672 VI0_G2_MARK, VI0_G3_MARK,
3673 VI0_G4_MARK, VI0_G5_MARK,
3674 VI0_G6_MARK, VI0_G7_MARK,
3675 /* R */
3676 VI0_R2_MARK, VI0_R3_MARK,
3677 VI0_R4_MARK, VI0_R5_MARK,
3678 VI0_R6_MARK, VI0_R7_MARK,
3679};
3680static const unsigned int vin0_sync_pins[] = {
3681 RCAR_GP_PIN(3, 11), /* HSYNC */
3682 RCAR_GP_PIN(3, 12), /* VSYNC */
3683};
3684static const unsigned int vin0_sync_mux[] = {
3685 VI0_HSYNC_N_MARK,
3686 VI0_VSYNC_N_MARK,
3687};
3688static const unsigned int vin0_field_pins[] = {
3689 RCAR_GP_PIN(3, 10),
3690};
3691static const unsigned int vin0_field_mux[] = {
3692 VI0_FIELD_MARK,
3693};
3694static const unsigned int vin0_clkenb_pins[] = {
3695 RCAR_GP_PIN(3, 9),
3696};
3697static const unsigned int vin0_clkenb_mux[] = {
3698 VI0_CLKENB_MARK,
3699};
3700static const unsigned int vin0_clk_pins[] = {
3701 RCAR_GP_PIN(3, 0),
3702};
3703static const unsigned int vin0_clk_mux[] = {
3704 VI0_CLK_MARK,
3705};
3706/* - VIN1 ------------------------------------------------------------------- */
3707static const union vin_data vin1_data_pins = {
3708 .data12 = {
3709 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3710 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3711 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3712 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3713 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3714 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3715 },
3716};
3717static const union vin_data vin1_data_mux = {
3718 .data12 = {
3719 VI1_DATA0_MARK, VI1_DATA1_MARK,
3720 VI1_DATA2_MARK, VI1_DATA3_MARK,
3721 VI1_DATA4_MARK, VI1_DATA5_MARK,
3722 VI1_DATA6_MARK, VI1_DATA7_MARK,
3723 VI1_DATA8_MARK, VI1_DATA9_MARK,
3724 VI1_DATA10_MARK, VI1_DATA11_MARK,
3725 },
3726};
3727static const unsigned int vin1_sync_pins[] = {
3728 RCAR_GP_PIN(5, 22), /* HSYNC */
3729 RCAR_GP_PIN(5, 23), /* VSYNC */
3730};
3731static const unsigned int vin1_sync_mux[] = {
3732 VI1_HSYNC_N_MARK,
3733 VI1_VSYNC_N_MARK,
3734};
3735static const unsigned int vin1_field_pins[] = {
3736 RCAR_GP_PIN(5, 21),
3737};
3738static const unsigned int vin1_field_mux[] = {
3739 VI1_FIELD_MARK,
3740};
3741static const unsigned int vin1_clkenb_pins[] = {
3742 RCAR_GP_PIN(5, 20),
3743};
3744static const unsigned int vin1_clkenb_mux[] = {
3745 VI1_CLKENB_MARK,
3746};
3747static const unsigned int vin1_clk_pins[] = {
3748 RCAR_GP_PIN(5, 11),
3749};
3750static const unsigned int vin1_clk_mux[] = {
3751 VI1_CLK_MARK,
3752};
3753
3754static const struct sh_pfc_pin_group pinmux_groups[] = {
3755 SH_PFC_PIN_GROUP(audio_clka),
3756 SH_PFC_PIN_GROUP(audio_clka_b),
3757 SH_PFC_PIN_GROUP(audio_clka_c),
3758 SH_PFC_PIN_GROUP(audio_clka_d),
3759 SH_PFC_PIN_GROUP(audio_clkb),
3760 SH_PFC_PIN_GROUP(audio_clkb_b),
3761 SH_PFC_PIN_GROUP(audio_clkb_c),
3762 SH_PFC_PIN_GROUP(audio_clkc),
3763 SH_PFC_PIN_GROUP(audio_clkc_b),
3764 SH_PFC_PIN_GROUP(audio_clkc_c),
3765 SH_PFC_PIN_GROUP(audio_clkout),
3766 SH_PFC_PIN_GROUP(audio_clkout_b),
3767 SH_PFC_PIN_GROUP(audio_clkout_c),
3768 SH_PFC_PIN_GROUP(avb_link),
3769 SH_PFC_PIN_GROUP(avb_magic),
3770 SH_PFC_PIN_GROUP(avb_phy_int),
3771 SH_PFC_PIN_GROUP(avb_mdio),
3772 SH_PFC_PIN_GROUP(avb_mii),
3773 SH_PFC_PIN_GROUP(avb_gmii),
3774 SH_PFC_PIN_GROUP(can0_data),
3775 SH_PFC_PIN_GROUP(can0_data_b),
3776 SH_PFC_PIN_GROUP(can0_data_c),
3777 SH_PFC_PIN_GROUP(can0_data_d),
3778 SH_PFC_PIN_GROUP(can1_data),
3779 SH_PFC_PIN_GROUP(can1_data_b),
3780 SH_PFC_PIN_GROUP(can1_data_c),
3781 SH_PFC_PIN_GROUP(can1_data_d),
3782 SH_PFC_PIN_GROUP(can_clk),
3783 SH_PFC_PIN_GROUP(can_clk_b),
3784 SH_PFC_PIN_GROUP(can_clk_c),
3785 SH_PFC_PIN_GROUP(can_clk_d),
3786 SH_PFC_PIN_GROUP(du0_rgb666),
3787 SH_PFC_PIN_GROUP(du0_rgb888),
3788 SH_PFC_PIN_GROUP(du0_clk0_out),
3789 SH_PFC_PIN_GROUP(du0_clk1_out),
3790 SH_PFC_PIN_GROUP(du0_clk_in),
3791 SH_PFC_PIN_GROUP(du0_sync),
3792 SH_PFC_PIN_GROUP(du0_oddf),
3793 SH_PFC_PIN_GROUP(du0_cde),
3794 SH_PFC_PIN_GROUP(du0_disp),
3795 SH_PFC_PIN_GROUP(du1_rgb666),
3796 SH_PFC_PIN_GROUP(du1_rgb888),
3797 SH_PFC_PIN_GROUP(du1_clk0_out),
3798 SH_PFC_PIN_GROUP(du1_clk1_out),
3799 SH_PFC_PIN_GROUP(du1_clk_in),
3800 SH_PFC_PIN_GROUP(du1_sync),
3801 SH_PFC_PIN_GROUP(du1_oddf),
3802 SH_PFC_PIN_GROUP(du1_cde),
3803 SH_PFC_PIN_GROUP(du1_disp),
3804 SH_PFC_PIN_GROUP(eth_link),
3805 SH_PFC_PIN_GROUP(eth_magic),
3806 SH_PFC_PIN_GROUP(eth_mdio),
3807 SH_PFC_PIN_GROUP(eth_rmii),
3808 SH_PFC_PIN_GROUP(eth_link_b),
3809 SH_PFC_PIN_GROUP(eth_magic_b),
3810 SH_PFC_PIN_GROUP(eth_mdio_b),
3811 SH_PFC_PIN_GROUP(eth_rmii_b),
3812 SH_PFC_PIN_GROUP(hscif0_data),
3813 SH_PFC_PIN_GROUP(hscif0_clk),
3814 SH_PFC_PIN_GROUP(hscif0_ctrl),
3815 SH_PFC_PIN_GROUP(hscif0_data_b),
3816 SH_PFC_PIN_GROUP(hscif0_clk_b),
3817 SH_PFC_PIN_GROUP(hscif1_data),
3818 SH_PFC_PIN_GROUP(hscif1_clk),
3819 SH_PFC_PIN_GROUP(hscif1_ctrl),
3820 SH_PFC_PIN_GROUP(hscif1_data_b),
3821 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3822 SH_PFC_PIN_GROUP(hscif2_data),
3823 SH_PFC_PIN_GROUP(hscif2_clk),
3824 SH_PFC_PIN_GROUP(hscif2_ctrl),
3825 SH_PFC_PIN_GROUP(i2c0),
3826 SH_PFC_PIN_GROUP(i2c0_b),
3827 SH_PFC_PIN_GROUP(i2c0_c),
3828 SH_PFC_PIN_GROUP(i2c0_d),
3829 SH_PFC_PIN_GROUP(i2c0_e),
3830 SH_PFC_PIN_GROUP(i2c1),
3831 SH_PFC_PIN_GROUP(i2c1_b),
3832 SH_PFC_PIN_GROUP(i2c1_c),
3833 SH_PFC_PIN_GROUP(i2c1_d),
3834 SH_PFC_PIN_GROUP(i2c1_e),
3835 SH_PFC_PIN_GROUP(i2c2),
3836 SH_PFC_PIN_GROUP(i2c2_b),
3837 SH_PFC_PIN_GROUP(i2c2_c),
3838 SH_PFC_PIN_GROUP(i2c2_d),
3839 SH_PFC_PIN_GROUP(i2c2_e),
3840 SH_PFC_PIN_GROUP(i2c3),
3841 SH_PFC_PIN_GROUP(i2c3_b),
3842 SH_PFC_PIN_GROUP(i2c3_c),
3843 SH_PFC_PIN_GROUP(i2c3_d),
3844 SH_PFC_PIN_GROUP(i2c3_e),
3845 SH_PFC_PIN_GROUP(i2c4),
3846 SH_PFC_PIN_GROUP(i2c4_b),
3847 SH_PFC_PIN_GROUP(i2c4_c),
3848 SH_PFC_PIN_GROUP(i2c4_d),
3849 SH_PFC_PIN_GROUP(i2c4_e),
3850 SH_PFC_PIN_GROUP(i2c5),
3851 SH_PFC_PIN_GROUP(i2c5_b),
3852 SH_PFC_PIN_GROUP(i2c5_c),
3853 SH_PFC_PIN_GROUP(i2c5_d),
3854 SH_PFC_PIN_GROUP(intc_irq0),
3855 SH_PFC_PIN_GROUP(intc_irq1),
3856 SH_PFC_PIN_GROUP(intc_irq2),
3857 SH_PFC_PIN_GROUP(intc_irq3),
3858 SH_PFC_PIN_GROUP(intc_irq4),
3859 SH_PFC_PIN_GROUP(intc_irq5),
3860 SH_PFC_PIN_GROUP(intc_irq6),
3861 SH_PFC_PIN_GROUP(intc_irq7),
3862 SH_PFC_PIN_GROUP(intc_irq8),
3863 SH_PFC_PIN_GROUP(intc_irq9),
3864 SH_PFC_PIN_GROUP(mmc_data1),
3865 SH_PFC_PIN_GROUP(mmc_data4),
3866 SH_PFC_PIN_GROUP(mmc_data8),
3867 SH_PFC_PIN_GROUP(mmc_ctrl),
3868 SH_PFC_PIN_GROUP(msiof0_clk),
3869 SH_PFC_PIN_GROUP(msiof0_sync),
3870 SH_PFC_PIN_GROUP(msiof0_ss1),
3871 SH_PFC_PIN_GROUP(msiof0_ss2),
3872 SH_PFC_PIN_GROUP(msiof0_rx),
3873 SH_PFC_PIN_GROUP(msiof0_tx),
3874 SH_PFC_PIN_GROUP(msiof1_clk),
3875 SH_PFC_PIN_GROUP(msiof1_sync),
3876 SH_PFC_PIN_GROUP(msiof1_ss1),
3877 SH_PFC_PIN_GROUP(msiof1_ss2),
3878 SH_PFC_PIN_GROUP(msiof1_rx),
3879 SH_PFC_PIN_GROUP(msiof1_tx),
3880 SH_PFC_PIN_GROUP(msiof1_clk_b),
3881 SH_PFC_PIN_GROUP(msiof1_sync_b),
3882 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3883 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3884 SH_PFC_PIN_GROUP(msiof1_rx_b),
3885 SH_PFC_PIN_GROUP(msiof1_tx_b),
3886 SH_PFC_PIN_GROUP(msiof2_clk),
3887 SH_PFC_PIN_GROUP(msiof2_sync),
3888 SH_PFC_PIN_GROUP(msiof2_ss1),
3889 SH_PFC_PIN_GROUP(msiof2_ss2),
3890 SH_PFC_PIN_GROUP(msiof2_rx),
3891 SH_PFC_PIN_GROUP(msiof2_tx),
3892 SH_PFC_PIN_GROUP(msiof2_clk_b),
3893 SH_PFC_PIN_GROUP(msiof2_sync_b),
3894 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3895 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3896 SH_PFC_PIN_GROUP(msiof2_rx_b),
3897 SH_PFC_PIN_GROUP(msiof2_tx_b),
3898 SH_PFC_PIN_GROUP(pwm0),
3899 SH_PFC_PIN_GROUP(pwm0_b),
3900 SH_PFC_PIN_GROUP(pwm1),
3901 SH_PFC_PIN_GROUP(pwm1_b),
3902 SH_PFC_PIN_GROUP(pwm1_c),
3903 SH_PFC_PIN_GROUP(pwm2),
3904 SH_PFC_PIN_GROUP(pwm2_b),
3905 SH_PFC_PIN_GROUP(pwm2_c),
3906 SH_PFC_PIN_GROUP(pwm3),
3907 SH_PFC_PIN_GROUP(pwm3_b),
3908 SH_PFC_PIN_GROUP(pwm4),
3909 SH_PFC_PIN_GROUP(pwm4_b),
3910 SH_PFC_PIN_GROUP(pwm5),
3911 SH_PFC_PIN_GROUP(pwm5_b),
3912 SH_PFC_PIN_GROUP(pwm5_c),
3913 SH_PFC_PIN_GROUP(pwm6),
3914 SH_PFC_PIN_GROUP(pwm6_b),
3915 SH_PFC_PIN_GROUP(qspi_ctrl),
3916 SH_PFC_PIN_GROUP(qspi_data2),
3917 SH_PFC_PIN_GROUP(qspi_data4),
3918 SH_PFC_PIN_GROUP(scif0_data),
3919 SH_PFC_PIN_GROUP(scif0_data_b),
3920 SH_PFC_PIN_GROUP(scif0_data_c),
3921 SH_PFC_PIN_GROUP(scif0_data_d),
3922 SH_PFC_PIN_GROUP(scif1_data),
3923 SH_PFC_PIN_GROUP(scif1_clk),
3924 SH_PFC_PIN_GROUP(scif1_data_b),
3925 SH_PFC_PIN_GROUP(scif1_clk_b),
3926 SH_PFC_PIN_GROUP(scif1_data_c),
3927 SH_PFC_PIN_GROUP(scif1_clk_c),
3928 SH_PFC_PIN_GROUP(scif2_data),
3929 SH_PFC_PIN_GROUP(scif2_clk),
3930 SH_PFC_PIN_GROUP(scif2_data_b),
3931 SH_PFC_PIN_GROUP(scif2_clk_b),
3932 SH_PFC_PIN_GROUP(scif2_data_c),
3933 SH_PFC_PIN_GROUP(scif2_clk_c),
3934 SH_PFC_PIN_GROUP(scif3_data),
3935 SH_PFC_PIN_GROUP(scif3_clk),
3936 SH_PFC_PIN_GROUP(scif3_data_b),
3937 SH_PFC_PIN_GROUP(scif3_clk_b),
3938 SH_PFC_PIN_GROUP(scif4_data),
3939 SH_PFC_PIN_GROUP(scif4_data_b),
3940 SH_PFC_PIN_GROUP(scif4_data_c),
3941 SH_PFC_PIN_GROUP(scif4_data_d),
3942 SH_PFC_PIN_GROUP(scif4_data_e),
3943 SH_PFC_PIN_GROUP(scif5_data),
3944 SH_PFC_PIN_GROUP(scif5_data_b),
3945 SH_PFC_PIN_GROUP(scif5_data_c),
3946 SH_PFC_PIN_GROUP(scif5_data_d),
3947 SH_PFC_PIN_GROUP(scifa0_data),
3948 SH_PFC_PIN_GROUP(scifa0_data_b),
3949 SH_PFC_PIN_GROUP(scifa0_data_c),
3950 SH_PFC_PIN_GROUP(scifa0_data_d),
3951 SH_PFC_PIN_GROUP(scifa1_data),
3952 SH_PFC_PIN_GROUP(scifa1_clk),
3953 SH_PFC_PIN_GROUP(scifa1_data_b),
3954 SH_PFC_PIN_GROUP(scifa1_clk_b),
3955 SH_PFC_PIN_GROUP(scifa1_data_c),
3956 SH_PFC_PIN_GROUP(scifa1_clk_c),
3957 SH_PFC_PIN_GROUP(scifa2_data),
3958 SH_PFC_PIN_GROUP(scifa2_clk),
3959 SH_PFC_PIN_GROUP(scifa2_data_b),
3960 SH_PFC_PIN_GROUP(scifa2_clk_b),
3961 SH_PFC_PIN_GROUP(scifa3_data),
3962 SH_PFC_PIN_GROUP(scifa3_clk),
3963 SH_PFC_PIN_GROUP(scifa3_data_b),
3964 SH_PFC_PIN_GROUP(scifa3_clk_b),
3965 SH_PFC_PIN_GROUP(scifa4_data),
3966 SH_PFC_PIN_GROUP(scifa4_data_b),
3967 SH_PFC_PIN_GROUP(scifa4_data_c),
3968 SH_PFC_PIN_GROUP(scifa4_data_d),
3969 SH_PFC_PIN_GROUP(scifa5_data),
3970 SH_PFC_PIN_GROUP(scifa5_data_b),
3971 SH_PFC_PIN_GROUP(scifa5_data_c),
3972 SH_PFC_PIN_GROUP(scifa5_data_d),
3973 SH_PFC_PIN_GROUP(scifb0_data),
3974 SH_PFC_PIN_GROUP(scifb0_clk),
3975 SH_PFC_PIN_GROUP(scifb0_ctrl),
3976 SH_PFC_PIN_GROUP(scifb1_data),
3977 SH_PFC_PIN_GROUP(scifb1_clk),
3978 SH_PFC_PIN_GROUP(scifb2_data),
3979 SH_PFC_PIN_GROUP(scifb2_clk),
3980 SH_PFC_PIN_GROUP(scifb2_ctrl),
3981 SH_PFC_PIN_GROUP(scif_clk),
3982 SH_PFC_PIN_GROUP(scif_clk_b),
3983 SH_PFC_PIN_GROUP(sdhi0_data1),
3984 SH_PFC_PIN_GROUP(sdhi0_data4),
3985 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3986 SH_PFC_PIN_GROUP(sdhi0_cd),
3987 SH_PFC_PIN_GROUP(sdhi0_wp),
3988 SH_PFC_PIN_GROUP(sdhi1_data1),
3989 SH_PFC_PIN_GROUP(sdhi1_data4),
3990 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3991 SH_PFC_PIN_GROUP(sdhi1_cd),
3992 SH_PFC_PIN_GROUP(sdhi1_wp),
3993 SH_PFC_PIN_GROUP(sdhi2_data1),
3994 SH_PFC_PIN_GROUP(sdhi2_data4),
3995 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3996 SH_PFC_PIN_GROUP(sdhi2_cd),
3997 SH_PFC_PIN_GROUP(sdhi2_wp),
3998 SH_PFC_PIN_GROUP(ssi0_data),
3999 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4000 SH_PFC_PIN_GROUP(ssi1_data),
4001 SH_PFC_PIN_GROUP(ssi1_ctrl),
4002 SH_PFC_PIN_GROUP(ssi1_data_b),
4003 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4004 SH_PFC_PIN_GROUP(ssi2_data),
4005 SH_PFC_PIN_GROUP(ssi2_ctrl),
4006 SH_PFC_PIN_GROUP(ssi2_data_b),
4007 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4008 SH_PFC_PIN_GROUP(ssi3_data),
4009 SH_PFC_PIN_GROUP(ssi34_ctrl),
4010 SH_PFC_PIN_GROUP(ssi4_data),
4011 SH_PFC_PIN_GROUP(ssi4_ctrl),
4012 SH_PFC_PIN_GROUP(ssi4_data_b),
4013 SH_PFC_PIN_GROUP(ssi4_ctrl_b),
4014 SH_PFC_PIN_GROUP(ssi5_data),
4015 SH_PFC_PIN_GROUP(ssi5_ctrl),
4016 SH_PFC_PIN_GROUP(ssi5_data_b),
4017 SH_PFC_PIN_GROUP(ssi5_ctrl_b),
4018 SH_PFC_PIN_GROUP(ssi6_data),
4019 SH_PFC_PIN_GROUP(ssi6_ctrl),
4020 SH_PFC_PIN_GROUP(ssi6_data_b),
4021 SH_PFC_PIN_GROUP(ssi6_ctrl_b),
4022 SH_PFC_PIN_GROUP(ssi7_data),
4023 SH_PFC_PIN_GROUP(ssi78_ctrl),
4024 SH_PFC_PIN_GROUP(ssi7_data_b),
4025 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4026 SH_PFC_PIN_GROUP(ssi8_data),
4027 SH_PFC_PIN_GROUP(ssi8_data_b),
4028 SH_PFC_PIN_GROUP(ssi9_data),
4029 SH_PFC_PIN_GROUP(ssi9_ctrl),
4030 SH_PFC_PIN_GROUP(ssi9_data_b),
4031 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4032 SH_PFC_PIN_GROUP(tpu_to0),
4033 SH_PFC_PIN_GROUP(tpu_to0_b),
4034 SH_PFC_PIN_GROUP(tpu_to0_c),
4035 SH_PFC_PIN_GROUP(tpu_to1),
4036 SH_PFC_PIN_GROUP(tpu_to1_b),
4037 SH_PFC_PIN_GROUP(tpu_to1_c),
4038 SH_PFC_PIN_GROUP(tpu_to2),
4039 SH_PFC_PIN_GROUP(tpu_to2_b),
4040 SH_PFC_PIN_GROUP(tpu_to2_c),
4041 SH_PFC_PIN_GROUP(tpu_to3),
4042 SH_PFC_PIN_GROUP(tpu_to3_b),
4043 SH_PFC_PIN_GROUP(tpu_to3_c),
4044 SH_PFC_PIN_GROUP(usb0),
4045 SH_PFC_PIN_GROUP(usb1),
4046 VIN_DATA_PIN_GROUP(vin0_data, 24),
4047 VIN_DATA_PIN_GROUP(vin0_data, 20),
4048 SH_PFC_PIN_GROUP(vin0_data18),
4049 VIN_DATA_PIN_GROUP(vin0_data, 16),
4050 VIN_DATA_PIN_GROUP(vin0_data, 12),
4051 VIN_DATA_PIN_GROUP(vin0_data, 10),
4052 VIN_DATA_PIN_GROUP(vin0_data, 8),
4053 SH_PFC_PIN_GROUP(vin0_sync),
4054 SH_PFC_PIN_GROUP(vin0_field),
4055 SH_PFC_PIN_GROUP(vin0_clkenb),
4056 SH_PFC_PIN_GROUP(vin0_clk),
4057 VIN_DATA_PIN_GROUP(vin1_data, 12),
4058 VIN_DATA_PIN_GROUP(vin1_data, 10),
4059 VIN_DATA_PIN_GROUP(vin1_data, 8),
4060 SH_PFC_PIN_GROUP(vin1_sync),
4061 SH_PFC_PIN_GROUP(vin1_field),
4062 SH_PFC_PIN_GROUP(vin1_clkenb),
4063 SH_PFC_PIN_GROUP(vin1_clk),
4064};
4065
4066static const char * const audio_clk_groups[] = {
4067 "audio_clka",
4068 "audio_clka_b",
4069 "audio_clka_c",
4070 "audio_clka_d",
4071 "audio_clkb",
4072 "audio_clkb_b",
4073 "audio_clkb_c",
4074 "audio_clkc",
4075 "audio_clkc_b",
4076 "audio_clkc_c",
4077 "audio_clkout",
4078 "audio_clkout_b",
4079 "audio_clkout_c",
4080};
4081
4082static const char * const avb_groups[] = {
4083 "avb_link",
4084 "avb_magic",
4085 "avb_phy_int",
4086 "avb_mdio",
4087 "avb_mii",
4088 "avb_gmii",
4089};
4090
4091static const char * const can0_groups[] = {
4092 "can0_data",
4093 "can0_data_b",
4094 "can0_data_c",
4095 "can0_data_d",
4096 /*
4097 * Retained for backwards compatibility, use can_clk_groups in new
4098 * designs.
4099 */
4100 "can_clk",
4101 "can_clk_b",
4102 "can_clk_c",
4103 "can_clk_d",
4104};
4105
4106static const char * const can1_groups[] = {
4107 "can1_data",
4108 "can1_data_b",
4109 "can1_data_c",
4110 "can1_data_d",
4111 /*
4112 * Retained for backwards compatibility, use can_clk_groups in new
4113 * designs.
4114 */
4115 "can_clk",
4116 "can_clk_b",
4117 "can_clk_c",
4118 "can_clk_d",
4119};
4120
4121/*
4122 * can_clk_groups allows for independent configuration, use can_clk function
4123 * in new designs.
4124 */
4125static const char * const can_clk_groups[] = {
4126 "can_clk",
4127 "can_clk_b",
4128 "can_clk_c",
4129 "can_clk_d",
4130};
4131
4132static const char * const du0_groups[] = {
4133 "du0_rgb666",
4134 "du0_rgb888",
4135 "du0_clk0_out",
4136 "du0_clk1_out",
4137 "du0_clk_in",
4138 "du0_sync",
4139 "du0_oddf",
4140 "du0_cde",
4141 "du0_disp",
4142};
4143
4144static const char * const du1_groups[] = {
4145 "du1_rgb666",
4146 "du1_rgb888",
4147 "du1_clk0_out",
4148 "du1_clk1_out",
4149 "du1_clk_in",
4150 "du1_sync",
4151 "du1_oddf",
4152 "du1_cde",
4153 "du1_disp",
4154};
4155
4156static const char * const eth_groups[] = {
4157 "eth_link",
4158 "eth_magic",
4159 "eth_mdio",
4160 "eth_rmii",
4161 "eth_link_b",
4162 "eth_magic_b",
4163 "eth_mdio_b",
4164 "eth_rmii_b",
4165};
4166
4167static const char * const hscif0_groups[] = {
4168 "hscif0_data",
4169 "hscif0_clk",
4170 "hscif0_ctrl",
4171 "hscif0_data_b",
4172 "hscif0_clk_b",
4173};
4174
4175static const char * const hscif1_groups[] = {
4176 "hscif1_data",
4177 "hscif1_clk",
4178 "hscif1_ctrl",
4179 "hscif1_data_b",
4180 "hscif1_ctrl_b",
4181};
4182
4183static const char * const hscif2_groups[] = {
4184 "hscif2_data",
4185 "hscif2_clk",
4186 "hscif2_ctrl",
4187};
4188
4189static const char * const i2c0_groups[] = {
4190 "i2c0",
4191 "i2c0_b",
4192 "i2c0_c",
4193 "i2c0_d",
4194 "i2c0_e",
4195};
4196
4197static const char * const i2c1_groups[] = {
4198 "i2c1",
4199 "i2c1_b",
4200 "i2c1_c",
4201 "i2c1_d",
4202 "i2c1_e",
4203};
4204
4205static const char * const i2c2_groups[] = {
4206 "i2c2",
4207 "i2c2_b",
4208 "i2c2_c",
4209 "i2c2_d",
4210 "i2c2_e",
4211};
4212
4213static const char * const i2c3_groups[] = {
4214 "i2c3",
4215 "i2c3_b",
4216 "i2c3_c",
4217 "i2c3_d",
4218 "i2c3_e",
4219};
4220
4221static const char * const i2c4_groups[] = {
4222 "i2c4",
4223 "i2c4_b",
4224 "i2c4_c",
4225 "i2c4_d",
4226 "i2c4_e",
4227};
4228
4229static const char * const i2c5_groups[] = {
4230 "i2c5",
4231 "i2c5_b",
4232 "i2c5_c",
4233 "i2c5_d",
4234};
4235
4236static const char * const intc_groups[] = {
4237 "intc_irq0",
4238 "intc_irq1",
4239 "intc_irq2",
4240 "intc_irq3",
4241 "intc_irq4",
4242 "intc_irq5",
4243 "intc_irq6",
4244 "intc_irq7",
4245 "intc_irq8",
4246 "intc_irq9",
4247};
4248
4249static const char * const mmc_groups[] = {
4250 "mmc_data1",
4251 "mmc_data4",
4252 "mmc_data8",
4253 "mmc_ctrl",
4254};
4255
4256static const char * const msiof0_groups[] = {
4257 "msiof0_clk",
4258 "msiof0_sync",
4259 "msiof0_ss1",
4260 "msiof0_ss2",
4261 "msiof0_rx",
4262 "msiof0_tx",
4263};
4264
4265static const char * const msiof1_groups[] = {
4266 "msiof1_clk",
4267 "msiof1_sync",
4268 "msiof1_ss1",
4269 "msiof1_ss2",
4270 "msiof1_rx",
4271 "msiof1_tx",
4272 "msiof1_clk_b",
4273 "msiof1_sync_b",
4274 "msiof1_ss1_b",
4275 "msiof1_ss2_b",
4276 "msiof1_rx_b",
4277 "msiof1_tx_b",
4278};
4279
4280static const char * const msiof2_groups[] = {
4281 "msiof2_clk",
4282 "msiof2_sync",
4283 "msiof2_ss1",
4284 "msiof2_ss2",
4285 "msiof2_rx",
4286 "msiof2_tx",
4287 "msiof2_clk_b",
4288 "msiof2_sync_b",
4289 "msiof2_ss1_b",
4290 "msiof2_ss2_b",
4291 "msiof2_rx_b",
4292 "msiof2_tx_b",
4293};
4294
4295static const char * const pwm0_groups[] = {
4296 "pwm0",
4297 "pwm0_b",
4298};
4299
4300static const char * const pwm1_groups[] = {
4301 "pwm1",
4302 "pwm1_b",
4303 "pwm1_c",
4304};
4305
4306static const char * const pwm2_groups[] = {
4307 "pwm2",
4308 "pwm2_b",
4309 "pwm2_c",
4310};
4311
4312static const char * const pwm3_groups[] = {
4313 "pwm3",
4314 "pwm3_b",
4315};
4316
4317static const char * const pwm4_groups[] = {
4318 "pwm4",
4319 "pwm4_b",
4320};
4321
4322static const char * const pwm5_groups[] = {
4323 "pwm5",
4324 "pwm5_b",
4325 "pwm5_c",
4326};
4327
4328static const char * const pwm6_groups[] = {
4329 "pwm6",
4330 "pwm6_b",
4331};
4332
4333static const char * const qspi_groups[] = {
4334 "qspi_ctrl",
4335 "qspi_data2",
4336 "qspi_data4",
4337};
4338
4339static const char * const scif0_groups[] = {
4340 "scif0_data",
4341 "scif0_data_b",
4342 "scif0_data_c",
4343 "scif0_data_d",
4344};
4345
4346static const char * const scif1_groups[] = {
4347 "scif1_data",
4348 "scif1_clk",
4349 "scif1_data_b",
4350 "scif1_clk_b",
4351 "scif1_data_c",
4352 "scif1_clk_c",
4353};
4354
4355static const char * const scif2_groups[] = {
4356 "scif2_data",
4357 "scif2_clk",
4358 "scif2_data_b",
4359 "scif2_clk_b",
4360 "scif2_data_c",
4361 "scif2_clk_c",
4362};
4363
4364static const char * const scif3_groups[] = {
4365 "scif3_data",
4366 "scif3_clk",
4367 "scif3_data_b",
4368 "scif3_clk_b",
4369};
4370
4371static const char * const scif4_groups[] = {
4372 "scif4_data",
4373 "scif4_data_b",
4374 "scif4_data_c",
4375 "scif4_data_d",
4376 "scif4_data_e",
4377};
4378
4379static const char * const scif5_groups[] = {
4380 "scif5_data",
4381 "scif5_data_b",
4382 "scif5_data_c",
4383 "scif5_data_d",
4384};
4385
4386static const char * const scifa0_groups[] = {
4387 "scifa0_data",
4388 "scifa0_data_b",
4389 "scifa0_data_c",
4390 "scifa0_data_d",
4391};
4392
4393static const char * const scifa1_groups[] = {
4394 "scifa1_data",
4395 "scifa1_clk",
4396 "scifa1_data_b",
4397 "scifa1_clk_b",
4398 "scifa1_data_c",
4399 "scifa1_clk_c",
4400};
4401
4402static const char * const scifa2_groups[] = {
4403 "scifa2_data",
4404 "scifa2_clk",
4405 "scifa2_data_b",
4406 "scifa2_clk_b",
4407};
4408
4409static const char * const scifa3_groups[] = {
4410 "scifa3_data",
4411 "scifa3_clk",
4412 "scifa3_data_b",
4413 "scifa3_clk_b",
4414};
4415
4416static const char * const scifa4_groups[] = {
4417 "scifa4_data",
4418 "scifa4_data_b",
4419 "scifa4_data_c",
4420 "scifa4_data_d",
4421};
4422
4423static const char * const scifa5_groups[] = {
4424 "scifa5_data",
4425 "scifa5_data_b",
4426 "scifa5_data_c",
4427 "scifa5_data_d",
4428};
4429
4430static const char * const scifb0_groups[] = {
4431 "scifb0_data",
4432 "scifb0_clk",
4433 "scifb0_ctrl",
4434};
4435
4436static const char * const scifb1_groups[] = {
4437 "scifb1_data",
4438 "scifb1_clk",
4439};
4440
4441static const char * const scifb2_groups[] = {
4442 "scifb2_data",
4443 "scifb2_clk",
4444 "scifb2_ctrl",
4445};
4446
4447static const char * const scif_clk_groups[] = {
4448 "scif_clk",
4449 "scif_clk_b",
4450};
4451
4452static const char * const sdhi0_groups[] = {
4453 "sdhi0_data1",
4454 "sdhi0_data4",
4455 "sdhi0_ctrl",
4456 "sdhi0_cd",
4457 "sdhi0_wp",
4458};
4459
4460static const char * const sdhi1_groups[] = {
4461 "sdhi1_data1",
4462 "sdhi1_data4",
4463 "sdhi1_ctrl",
4464 "sdhi1_cd",
4465 "sdhi1_wp",
4466};
4467
4468static const char * const sdhi2_groups[] = {
4469 "sdhi2_data1",
4470 "sdhi2_data4",
4471 "sdhi2_ctrl",
4472 "sdhi2_cd",
4473 "sdhi2_wp",
4474};
4475
4476static const char * const ssi_groups[] = {
4477 "ssi0_data",
4478 "ssi0129_ctrl",
4479 "ssi1_data",
4480 "ssi1_ctrl",
4481 "ssi1_data_b",
4482 "ssi1_ctrl_b",
4483 "ssi2_data",
4484 "ssi2_ctrl",
4485 "ssi2_data_b",
4486 "ssi2_ctrl_b",
4487 "ssi3_data",
4488 "ssi34_ctrl",
4489 "ssi4_data",
4490 "ssi4_ctrl",
4491 "ssi4_data_b",
4492 "ssi4_ctrl_b",
4493 "ssi5_data",
4494 "ssi5_ctrl",
4495 "ssi5_data_b",
4496 "ssi5_ctrl_b",
4497 "ssi6_data",
4498 "ssi6_ctrl",
4499 "ssi6_data_b",
4500 "ssi6_ctrl_b",
4501 "ssi7_data",
4502 "ssi78_ctrl",
4503 "ssi7_data_b",
4504 "ssi78_ctrl_b",
4505 "ssi8_data",
4506 "ssi8_data_b",
4507 "ssi9_data",
4508 "ssi9_ctrl",
4509 "ssi9_data_b",
4510 "ssi9_ctrl_b",
4511};
4512
4513static const char * const tpu_groups[] = {
4514 "tpu_to0",
4515 "tpu_to0_b",
4516 "tpu_to0_c",
4517 "tpu_to1",
4518 "tpu_to1_b",
4519 "tpu_to1_c",
4520 "tpu_to2",
4521 "tpu_to2_b",
4522 "tpu_to2_c",
4523 "tpu_to3",
4524 "tpu_to3_b",
4525 "tpu_to3_c",
4526};
4527
4528static const char * const usb0_groups[] = {
4529 "usb0",
4530};
4531
4532static const char * const usb1_groups[] = {
4533 "usb1",
4534};
4535
4536static const char * const vin0_groups[] = {
4537 "vin0_data24",
4538 "vin0_data20",
4539 "vin0_data18",
4540 "vin0_data16",
4541 "vin0_data12",
4542 "vin0_data10",
4543 "vin0_data8",
4544 "vin0_sync",
4545 "vin0_field",
4546 "vin0_clkenb",
4547 "vin0_clk",
4548};
4549
4550static const char * const vin1_groups[] = {
4551 "vin1_data12",
4552 "vin1_data10",
4553 "vin1_data8",
4554 "vin1_sync",
4555 "vin1_field",
4556 "vin1_clkenb",
4557 "vin1_clk",
4558};
4559
4560static const struct sh_pfc_function pinmux_functions[] = {
4561 SH_PFC_FUNCTION(audio_clk),
4562 SH_PFC_FUNCTION(avb),
4563 SH_PFC_FUNCTION(can0),
4564 SH_PFC_FUNCTION(can1),
4565 SH_PFC_FUNCTION(can_clk),
4566 SH_PFC_FUNCTION(du0),
4567 SH_PFC_FUNCTION(du1),
4568 SH_PFC_FUNCTION(eth),
4569 SH_PFC_FUNCTION(hscif0),
4570 SH_PFC_FUNCTION(hscif1),
4571 SH_PFC_FUNCTION(hscif2),
4572 SH_PFC_FUNCTION(i2c0),
4573 SH_PFC_FUNCTION(i2c1),
4574 SH_PFC_FUNCTION(i2c2),
4575 SH_PFC_FUNCTION(i2c3),
4576 SH_PFC_FUNCTION(i2c4),
4577 SH_PFC_FUNCTION(i2c5),
4578 SH_PFC_FUNCTION(intc),
4579 SH_PFC_FUNCTION(mmc),
4580 SH_PFC_FUNCTION(msiof0),
4581 SH_PFC_FUNCTION(msiof1),
4582 SH_PFC_FUNCTION(msiof2),
4583 SH_PFC_FUNCTION(pwm0),
4584 SH_PFC_FUNCTION(pwm1),
4585 SH_PFC_FUNCTION(pwm2),
4586 SH_PFC_FUNCTION(pwm3),
4587 SH_PFC_FUNCTION(pwm4),
4588 SH_PFC_FUNCTION(pwm5),
4589 SH_PFC_FUNCTION(pwm6),
4590 SH_PFC_FUNCTION(qspi),
4591 SH_PFC_FUNCTION(scif0),
4592 SH_PFC_FUNCTION(scif1),
4593 SH_PFC_FUNCTION(scif2),
4594 SH_PFC_FUNCTION(scif3),
4595 SH_PFC_FUNCTION(scif4),
4596 SH_PFC_FUNCTION(scif5),
4597 SH_PFC_FUNCTION(scifa0),
4598 SH_PFC_FUNCTION(scifa1),
4599 SH_PFC_FUNCTION(scifa2),
4600 SH_PFC_FUNCTION(scifa3),
4601 SH_PFC_FUNCTION(scifa4),
4602 SH_PFC_FUNCTION(scifa5),
4603 SH_PFC_FUNCTION(scifb0),
4604 SH_PFC_FUNCTION(scifb1),
4605 SH_PFC_FUNCTION(scifb2),
4606 SH_PFC_FUNCTION(scif_clk),
4607 SH_PFC_FUNCTION(sdhi0),
4608 SH_PFC_FUNCTION(sdhi1),
4609 SH_PFC_FUNCTION(sdhi2),
4610 SH_PFC_FUNCTION(ssi),
4611 SH_PFC_FUNCTION(tpu),
4612 SH_PFC_FUNCTION(usb0),
4613 SH_PFC_FUNCTION(usb1),
4614 SH_PFC_FUNCTION(vin0),
4615 SH_PFC_FUNCTION(vin1),
4616};
4617
4618static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4619 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4620 GP_0_31_FN, FN_IP2_17_16,
4621 GP_0_30_FN, FN_IP2_15_14,
4622 GP_0_29_FN, FN_IP2_13_12,
4623 GP_0_28_FN, FN_IP2_11_10,
4624 GP_0_27_FN, FN_IP2_9_8,
4625 GP_0_26_FN, FN_IP2_7_6,
4626 GP_0_25_FN, FN_IP2_5_4,
4627 GP_0_24_FN, FN_IP2_3_2,
4628 GP_0_23_FN, FN_IP2_1_0,
4629 GP_0_22_FN, FN_IP1_31_30,
4630 GP_0_21_FN, FN_IP1_29_28,
4631 GP_0_20_FN, FN_IP1_27,
4632 GP_0_19_FN, FN_IP1_26,
4633 GP_0_18_FN, FN_A2,
4634 GP_0_17_FN, FN_IP1_24,
4635 GP_0_16_FN, FN_IP1_23_22,
4636 GP_0_15_FN, FN_IP1_21_20,
4637 GP_0_14_FN, FN_IP1_19_18,
4638 GP_0_13_FN, FN_IP1_17_15,
4639 GP_0_12_FN, FN_IP1_14_13,
4640 GP_0_11_FN, FN_IP1_12_11,
4641 GP_0_10_FN, FN_IP1_10_8,
4642 GP_0_9_FN, FN_IP1_7_6,
4643 GP_0_8_FN, FN_IP1_5_4,
4644 GP_0_7_FN, FN_IP1_3_2,
4645 GP_0_6_FN, FN_IP1_1_0,
4646 GP_0_5_FN, FN_IP0_31_30,
4647 GP_0_4_FN, FN_IP0_29_28,
4648 GP_0_3_FN, FN_IP0_27_26,
4649 GP_0_2_FN, FN_IP0_25,
4650 GP_0_1_FN, FN_IP0_24,
4651 GP_0_0_FN, FN_IP0_23_22, }
4652 },
4653 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4654 0, 0,
4655 0, 0,
4656 0, 0,
4657 0, 0,
4658 0, 0,
4659 0, 0,
4660 GP_1_25_FN, FN_DACK0,
4661 GP_1_24_FN, FN_IP7_31,
4662 GP_1_23_FN, FN_IP4_1_0,
4663 GP_1_22_FN, FN_WE1_N,
4664 GP_1_21_FN, FN_WE0_N,
4665 GP_1_20_FN, FN_IP3_31,
4666 GP_1_19_FN, FN_IP3_30,
4667 GP_1_18_FN, FN_IP3_29_27,
4668 GP_1_17_FN, FN_IP3_26_24,
4669 GP_1_16_FN, FN_IP3_23_21,
4670 GP_1_15_FN, FN_IP3_20_18,
4671 GP_1_14_FN, FN_IP3_17_15,
4672 GP_1_13_FN, FN_IP3_14_13,
4673 GP_1_12_FN, FN_IP3_12,
4674 GP_1_11_FN, FN_IP3_11,
4675 GP_1_10_FN, FN_IP3_10,
4676 GP_1_9_FN, FN_IP3_9_8,
4677 GP_1_8_FN, FN_IP3_7_6,
4678 GP_1_7_FN, FN_IP3_5_4,
4679 GP_1_6_FN, FN_IP3_3_2,
4680 GP_1_5_FN, FN_IP3_1_0,
4681 GP_1_4_FN, FN_IP2_31_30,
4682 GP_1_3_FN, FN_IP2_29_27,
4683 GP_1_2_FN, FN_IP2_26_24,
4684 GP_1_1_FN, FN_IP2_23_21,
4685 GP_1_0_FN, FN_IP2_20_18, }
4686 },
4687 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4688 GP_2_31_FN, FN_IP6_7_6,
4689 GP_2_30_FN, FN_IP6_5_4,
4690 GP_2_29_FN, FN_IP6_3_2,
4691 GP_2_28_FN, FN_IP6_1_0,
4692 GP_2_27_FN, FN_IP5_31_30,
4693 GP_2_26_FN, FN_IP5_29_28,
4694 GP_2_25_FN, FN_IP5_27_26,
4695 GP_2_24_FN, FN_IP5_25_24,
4696 GP_2_23_FN, FN_IP5_23_22,
4697 GP_2_22_FN, FN_IP5_21_20,
4698 GP_2_21_FN, FN_IP5_19_18,
4699 GP_2_20_FN, FN_IP5_17_16,
4700 GP_2_19_FN, FN_IP5_15_14,
4701 GP_2_18_FN, FN_IP5_13_12,
4702 GP_2_17_FN, FN_IP5_11_9,
4703 GP_2_16_FN, FN_IP5_8_6,
4704 GP_2_15_FN, FN_IP5_5_4,
4705 GP_2_14_FN, FN_IP5_3_2,
4706 GP_2_13_FN, FN_IP5_1_0,
4707 GP_2_12_FN, FN_IP4_31_30,
4708 GP_2_11_FN, FN_IP4_29_28,
4709 GP_2_10_FN, FN_IP4_27_26,
4710 GP_2_9_FN, FN_IP4_25_23,
4711 GP_2_8_FN, FN_IP4_22_20,
4712 GP_2_7_FN, FN_IP4_19_18,
4713 GP_2_6_FN, FN_IP4_17_16,
4714 GP_2_5_FN, FN_IP4_15_14,
4715 GP_2_4_FN, FN_IP4_13_12,
4716 GP_2_3_FN, FN_IP4_11_10,
4717 GP_2_2_FN, FN_IP4_9_8,
4718 GP_2_1_FN, FN_IP4_7_5,
4719 GP_2_0_FN, FN_IP4_4_2 }
4720 },
4721 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4722 GP_3_31_FN, FN_IP8_22_20,
4723 GP_3_30_FN, FN_IP8_19_17,
4724 GP_3_29_FN, FN_IP8_16_15,
4725 GP_3_28_FN, FN_IP8_14_12,
4726 GP_3_27_FN, FN_IP8_11_9,
4727 GP_3_26_FN, FN_IP8_8_6,
4728 GP_3_25_FN, FN_IP8_5_3,
4729 GP_3_24_FN, FN_IP8_2_0,
4730 GP_3_23_FN, FN_IP7_29_27,
4731 GP_3_22_FN, FN_IP7_26_24,
4732 GP_3_21_FN, FN_IP7_23_21,
4733 GP_3_20_FN, FN_IP7_20_18,
4734 GP_3_19_FN, FN_IP7_17_15,
4735 GP_3_18_FN, FN_IP7_14_12,
4736 GP_3_17_FN, FN_IP7_11_9,
4737 GP_3_16_FN, FN_IP7_8_6,
4738 GP_3_15_FN, FN_IP7_5_3,
4739 GP_3_14_FN, FN_IP7_2_0,
4740 GP_3_13_FN, FN_IP6_31_29,
4741 GP_3_12_FN, FN_IP6_28_26,
4742 GP_3_11_FN, FN_IP6_25_23,
4743 GP_3_10_FN, FN_IP6_22_20,
4744 GP_3_9_FN, FN_IP6_19_17,
4745 GP_3_8_FN, FN_IP6_16,
4746 GP_3_7_FN, FN_IP6_15,
4747 GP_3_6_FN, FN_IP6_14,
4748 GP_3_5_FN, FN_IP6_13,
4749 GP_3_4_FN, FN_IP6_12,
4750 GP_3_3_FN, FN_IP6_11,
4751 GP_3_2_FN, FN_IP6_10,
4752 GP_3_1_FN, FN_IP6_9,
4753 GP_3_0_FN, FN_IP6_8 }
4754 },
4755 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4756 GP_4_31_FN, FN_IP11_17_16,
4757 GP_4_30_FN, FN_IP11_15_14,
4758 GP_4_29_FN, FN_IP11_13_11,
4759 GP_4_28_FN, FN_IP11_10_8,
4760 GP_4_27_FN, FN_IP11_7_6,
4761 GP_4_26_FN, FN_IP11_5_3,
4762 GP_4_25_FN, FN_IP11_2_0,
4763 GP_4_24_FN, FN_IP10_31_30,
4764 GP_4_23_FN, FN_IP10_29_27,
4765 GP_4_22_FN, FN_IP10_26_24,
4766 GP_4_21_FN, FN_IP10_23_21,
4767 GP_4_20_FN, FN_IP10_20_18,
4768 GP_4_19_FN, FN_IP10_17_15,
4769 GP_4_18_FN, FN_IP10_14_12,
4770 GP_4_17_FN, FN_IP10_11_9,
4771 GP_4_16_FN, FN_IP10_8_6,
4772 GP_4_15_FN, FN_IP10_5_3,
4773 GP_4_14_FN, FN_IP10_2_0,
4774 GP_4_13_FN, FN_IP9_30_28,
4775 GP_4_12_FN, FN_IP9_27_25,
4776 GP_4_11_FN, FN_IP9_24_22,
4777 GP_4_10_FN, FN_IP9_21_19,
4778 GP_4_9_FN, FN_IP9_18_17,
4779 GP_4_8_FN, FN_IP9_16_15,
4780 GP_4_7_FN, FN_IP9_14_12,
4781 GP_4_6_FN, FN_IP9_11_9,
4782 GP_4_5_FN, FN_IP9_8_6,
4783 GP_4_4_FN, FN_IP9_5_3,
4784 GP_4_3_FN, FN_IP9_2_0,
4785 GP_4_2_FN, FN_IP8_31_29,
4786 GP_4_1_FN, FN_IP8_28_26,
4787 GP_4_0_FN, FN_IP8_25_23 }
4788 },
4789 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4790 0, 0,
4791 0, 0,
4792 0, 0,
4793 0, 0,
4794 GP_5_27_FN, FN_USB1_OVC,
4795 GP_5_26_FN, FN_USB1_PWEN,
4796 GP_5_25_FN, FN_USB0_OVC,
4797 GP_5_24_FN, FN_USB0_PWEN,
4798 GP_5_23_FN, FN_IP13_26_24,
4799 GP_5_22_FN, FN_IP13_23_21,
4800 GP_5_21_FN, FN_IP13_20_18,
4801 GP_5_20_FN, FN_IP13_17_15,
4802 GP_5_19_FN, FN_IP13_14_12,
4803 GP_5_18_FN, FN_IP13_11_9,
4804 GP_5_17_FN, FN_IP13_8_6,
4805 GP_5_16_FN, FN_IP13_5_3,
4806 GP_5_15_FN, FN_IP13_2_0,
4807 GP_5_14_FN, FN_IP12_29_27,
4808 GP_5_13_FN, FN_IP12_26_24,
4809 GP_5_12_FN, FN_IP12_23_21,
4810 GP_5_11_FN, FN_IP12_20_18,
4811 GP_5_10_FN, FN_IP12_17_15,
4812 GP_5_9_FN, FN_IP12_14_13,
4813 GP_5_8_FN, FN_IP12_12_11,
4814 GP_5_7_FN, FN_IP12_10_9,
4815 GP_5_6_FN, FN_IP12_8_6,
4816 GP_5_5_FN, FN_IP12_5_3,
4817 GP_5_4_FN, FN_IP12_2_0,
4818 GP_5_3_FN, FN_IP11_29_27,
4819 GP_5_2_FN, FN_IP11_26_24,
4820 GP_5_1_FN, FN_IP11_23_21,
4821 GP_5_0_FN, FN_IP11_20_18 }
4822 },
4823 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4824 0, 0,
4825 0, 0,
4826 0, 0,
4827 0, 0,
4828 0, 0,
4829 0, 0,
4830 GP_6_25_FN, FN_IP0_21_20,
4831 GP_6_24_FN, FN_IP0_19_18,
4832 GP_6_23_FN, FN_IP0_17,
4833 GP_6_22_FN, FN_IP0_16,
4834 GP_6_21_FN, FN_IP0_15,
4835 GP_6_20_FN, FN_IP0_14,
4836 GP_6_19_FN, FN_IP0_13,
4837 GP_6_18_FN, FN_IP0_12,
4838 GP_6_17_FN, FN_IP0_11,
4839 GP_6_16_FN, FN_IP0_10,
4840 GP_6_15_FN, FN_IP0_9_8,
4841 GP_6_14_FN, FN_IP0_0,
4842 GP_6_13_FN, FN_SD1_DATA3,
4843 GP_6_12_FN, FN_SD1_DATA2,
4844 GP_6_11_FN, FN_SD1_DATA1,
4845 GP_6_10_FN, FN_SD1_DATA0,
4846 GP_6_9_FN, FN_SD1_CMD,
4847 GP_6_8_FN, FN_SD1_CLK,
4848 GP_6_7_FN, FN_SD0_WP,
4849 GP_6_6_FN, FN_SD0_CD,
4850 GP_6_5_FN, FN_SD0_DATA3,
4851 GP_6_4_FN, FN_SD0_DATA2,
4852 GP_6_3_FN, FN_SD0_DATA1,
4853 GP_6_2_FN, FN_SD0_DATA0,
4854 GP_6_1_FN, FN_SD0_CMD,
4855 GP_6_0_FN, FN_SD0_CLK }
4856 },
4857 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4858 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4859 2, 1, 1, 1, 1, 1, 1, 1, 1) {
4860 /* IP0_31_30 [2] */
4861 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4862 /* IP0_29_28 [2] */
4863 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4864 /* IP0_27_26 [2] */
4865 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4866 /* IP0_25 [1] */
4867 FN_D2, FN_SCIFA3_TXD_B,
4868 /* IP0_24 [1] */
4869 FN_D1, FN_SCIFA3_RXD_B,
4870 /* IP0_23_22 [2] */
4871 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4872 /* IP0_21_20 [2] */
4873 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4874 /* IP0_19_18 [2] */
4875 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4876 /* IP0_17 [1] */
4877 FN_MMC_D5, FN_SD2_WP,
4878 /* IP0_16 [1] */
4879 FN_MMC_D4, FN_SD2_CD,
4880 /* IP0_15 [1] */
4881 FN_MMC_D3, FN_SD2_DATA3,
4882 /* IP0_14 [1] */
4883 FN_MMC_D2, FN_SD2_DATA2,
4884 /* IP0_13 [1] */
4885 FN_MMC_D1, FN_SD2_DATA1,
4886 /* IP0_12 [1] */
4887 FN_MMC_D0, FN_SD2_DATA0,
4888 /* IP0_11 [1] */
4889 FN_MMC_CMD, FN_SD2_CMD,
4890 /* IP0_10 [1] */
4891 FN_MMC_CLK, FN_SD2_CLK,
4892 /* IP0_9_8 [2] */
4893 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4894 /* IP0_7 [1] */
4895 0, 0,
4896 /* IP0_6 [1] */
4897 0, 0,
4898 /* IP0_5 [1] */
4899 0, 0,
4900 /* IP0_4 [1] */
4901 0, 0,
4902 /* IP0_3 [1] */
4903 0, 0,
4904 /* IP0_2 [1] */
4905 0, 0,
4906 /* IP0_1 [1] */
4907 0, 0,
4908 /* IP0_0 [1] */
4909 FN_SD1_CD, FN_CAN0_RX, }
4910 },
4911 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4912 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
4913 2, 2) {
4914 /* IP1_31_30 [2] */
4915 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4916 /* IP1_29_28 [2] */
4917 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4918 /* IP1_27 [1] */
4919 FN_A4, FN_SCIFB0_TXD,
4920 /* IP1_26 [1] */
4921 FN_A3, FN_SCIFB0_SCK,
4922 /* IP1_25 [1] */
4923 0, 0,
4924 /* IP1_24 [1] */
4925 FN_A1, FN_SCIFB1_TXD,
4926 /* IP1_23_22 [2] */
4927 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4928 /* IP1_21_20 [2] */
4929 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
4930 /* IP1_19_18 [2] */
4931 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4932 /* IP1_17_15 [3] */
4933 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4934 0, 0, 0,
4935 /* IP1_14_13 [2] */
4936 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4937 /* IP1_12_11 [2] */
4938 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4939 /* IP1_10_8 [3] */
4940 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4941 0, 0, 0,
4942 /* IP1_7_6 [2] */
4943 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4944 /* IP1_5_4 [2] */
4945 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4946 /* IP1_3_2 [2] */
4947 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4948 /* IP1_1_0 [2] */
4949 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
4950 },
4951 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4952 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
4953 /* IP2_31_30 [2] */
4954 FN_A20, FN_SPCLK, 0, 0,
4955 /* IP2_29_27 [3] */
4956 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4957 0, 0, 0, 0,
4958 /* IP2_26_24 [3] */
4959 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4960 0, 0, 0, 0,
4961 /* IP2_23_21 [3] */
4962 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4963 0, 0, 0, 0,
4964 /* IP2_20_18 [3] */
4965 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4966 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4967 /* IP2_17_16 [2] */
4968 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4969 /* IP2_15_14 [2] */
4970 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4971 /* IP2_13_12 [2] */
4972 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4973 /* IP2_11_10 [2] */
4974 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4975 /* IP2_9_8 [2] */
4976 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
4977 /* IP2_7_6 [2] */
4978 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
4979 /* IP2_5_4 [2] */
4980 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4981 /* IP2_3_2 [2] */
4982 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4983 /* IP2_1_0 [2] */
4984 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
4985 },
4986 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4987 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
4988 /* IP3_31 [1] */
4989 FN_RD_WR_N, FN_ATAG1_N,
4990 /* IP3_30 [1] */
4991 FN_RD_N, FN_ATACS11_N,
4992 /* IP3_29_27 [3] */
4993 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4994 0, 0, 0,
4995 /* IP3_26_24 [3] */
4996 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4997 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
4998 /* IP3_23_21 [3] */
4999 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
5000 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
5001 /* IP3_20_18 [3] */
5002 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
5003 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
5004 /* IP3_17_15 [3] */
5005 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
5006 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
5007 /* IP3_14_13 [2] */
5008 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
5009 /* IP3_12 [1] */
5010 FN_EX_CS0_N, FN_VI1_DATA10,
5011 /* IP3_11 [1] */
5012 FN_CS1_N_A26, FN_VI1_DATA9,
5013 /* IP3_10 [1] */
5014 FN_CS0_N, FN_VI1_DATA8,
5015 /* IP3_9_8 [2] */
5016 FN_A25, FN_SSL, FN_ATARD1_N, 0,
5017 /* IP3_7_6 [2] */
5018 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
5019 /* IP3_5_4 [2] */
5020 FN_A23, FN_IO2, 0, FN_ATAWR1_N,
5021 /* IP3_3_2 [2] */
5022 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
5023 /* IP3_1_0 [2] */
5024 FN_A21, FN_MOSI_IO0, 0, 0, }
5025 },
5026 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5027 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
5028 /* IP4_31_30 [2] */
5029 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
5030 /* IP4_29_28 [2] */
5031 FN_DU0_DG3, FN_LCDOUT11, 0, 0,
5032 /* IP4_27_26 [2] */
5033 FN_DU0_DG2, FN_LCDOUT10, 0, 0,
5034 /* IP4_25_23 [3] */
5035 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
5036 0, 0, 0, 0,
5037 /* IP4_22_20 [3] */
5038 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
5039 0, 0, 0, 0,
5040 /* IP4_19_18 [2] */
5041 FN_DU0_DR7, FN_LCDOUT23, 0, 0,
5042 /* IP4_17_16 [2] */
5043 FN_DU0_DR6, FN_LCDOUT22, 0, 0,
5044 /* IP4_15_14 [2] */
5045 FN_DU0_DR5, FN_LCDOUT21, 0, 0,
5046 /* IP4_13_12 [2] */
5047 FN_DU0_DR4, FN_LCDOUT20, 0, 0,
5048 /* IP4_11_10 [2] */
5049 FN_DU0_DR3, FN_LCDOUT19, 0, 0,
5050 /* IP4_9_8 [2] */
5051 FN_DU0_DR2, FN_LCDOUT18, 0, 0,
5052 /* IP4_7_5 [3] */
5053 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
5054 0, 0, 0, 0,
5055 /* IP4_4_2 [3] */
5056 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
5057 0, 0, 0, 0,
5058 /* IP4_1_0 [2] */
5059 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
5060 },
5061 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5062 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
5063 /* IP5_31_30 [2] */
5064 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
5065 /* IP5_29_28 [2] */
5066 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
5067 /* IP5_27_26 [2] */
5068 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
5069 /* IP5_25_24 [2] */
5070 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
5071 /* IP5_23_22 [2] */
5072 FN_DU0_DB7, FN_LCDOUT7, 0, 0,
5073 /* IP5_21_20 [2] */
5074 FN_DU0_DB6, FN_LCDOUT6, 0, 0,
5075 /* IP5_19_18 [2] */
5076 FN_DU0_DB5, FN_LCDOUT5, 0, 0,
5077 /* IP5_17_16 [2] */
5078 FN_DU0_DB4, FN_LCDOUT4, 0, 0,
5079 /* IP5_15_14 [2] */
5080 FN_DU0_DB3, FN_LCDOUT3, 0, 0,
5081 /* IP5_13_12 [2] */
5082 FN_DU0_DB2, FN_LCDOUT2, 0, 0,
5083 /* IP5_11_9 [3] */
5084 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
5085 FN_CAN0_TX_C, 0, 0, 0,
5086 /* IP5_8_6 [3] */
5087 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
5088 FN_CAN0_RX_C, 0, 0, 0,
5089 /* IP5_5_4 [2] */
5090 FN_DU0_DG7, FN_LCDOUT15, 0, 0,
5091 /* IP5_3_2 [2] */
5092 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
5093 /* IP5_1_0 [2] */
5094 FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
5095 },
5096 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5097 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
5098 2, 2) {
5099 /* IP6_31_29 [3] */
5100 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
5101 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
5102 /* IP6_28_26 [3] */
5103 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
5104 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
5105 /* IP6_25_23 [3] */
5106 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
5107 FN_AVB_COL, 0, 0, 0,
5108 /* IP6_22_20 [3] */
5109 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
5110 FN_AVB_RX_ER, 0, 0, 0,
5111 /* IP6_19_17 [3] */
5112 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
5113 FN_AVB_RXD7, 0, 0, 0,
5114 /* IP6_16 [1] */
5115 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
5116 /* IP6_15 [1] */
5117 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
5118 /* IP6_14 [1] */
5119 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
5120 /* IP6_13 [1] */
5121 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
5122 /* IP6_12 [1] */
5123 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
5124 /* IP6_11 [1] */
5125 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
5126 /* IP6_10 [1] */
5127 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
5128 /* IP6_9 [1] */
5129 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
5130 /* IP6_8 [1] */
5131 FN_VI0_CLK, FN_AVB_RX_CLK,
5132 /* IP6_7_6 [2] */
5133 FN_DU0_CDE, FN_QPOLB, 0, 0,
5134 /* IP6_5_4 [2] */
5135 FN_DU0_DISP, FN_QPOLA, 0, 0,
5136 /* IP6_3_2 [2] */
5137 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
5138 0,
5139 /* IP6_1_0 [2] */
5140 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
5141 },
5142 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5143 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5144 /* IP7_31 [1] */
5145 FN_DREQ0_N, FN_SCIFB1_RXD,
5146 /* IP7_30 [1] */
5147 0, 0,
5148 /* IP7_29_27 [3] */
5149 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
5150 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
5151 /* IP7_26_24 [3] */
5152 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
5153 FN_SSI_SCK6_B, 0, 0, 0,
5154 /* IP7_23_21 [3] */
5155 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
5156 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
5157 /* IP7_20_18 [3] */
5158 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
5159 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
5160 /* IP7_17_15 [3] */
5161 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
5162 FN_SSI_SCK5_B, 0, 0, 0,
5163 /* IP7_14_12 [3] */
5164 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
5165 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
5166 /* IP7_11_9 [3] */
5167 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
5168 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
5169 /* IP7_8_6 [3] */
5170 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
5171 FN_AVB_TXD2, FN_ADICHS0, 0, 0,
5172 /* IP7_5_3 [3] */
5173 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
5174 FN_AVB_TXD1, FN_ADICLK, 0, 0,
5175 /* IP7_2_0 [3] */
5176 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
5177 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
5178 },
5179 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5180 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
5181 /* IP8_31_29 [3] */
5182 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
5183 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
5184 /* IP8_28_26 [3] */
5185 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
5186 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
5187 /* IP8_25_23 [3] */
5188 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
5189 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
5190 /* IP8_22_20 [3] */
5191 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
5192 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
5193 /* IP8_19_17 [3] */
5194 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
5195 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
5196 /* IP8_16_15 [2] */
5197 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
5198 /* IP8_14_12 [3] */
5199 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
5200 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
5201 /* IP8_11_9 [3] */
5202 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
5203 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
5204 /* IP8_8_6 [3] */
5205 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
5206 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
5207 /* IP8_5_3 [3] */
5208 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
5209 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
5210 /* IP8_2_0 [3] */
5211 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
5212 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
5213 },
5214 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5215 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
5216 /* IP9_31 [1] */
5217 0, 0,
5218 /* IP9_30_28 [3] */
5219 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
5220 FN_SSI_SDATA1_B, 0, 0, 0,
5221 /* IP9_27_25 [3] */
5222 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
5223 FN_SSI_WS1_B, 0, 0, 0,
5224 /* IP9_24_22 [3] */
5225 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
5226 FN_SSI_SCK1_B, 0, 0, 0,
5227 /* IP9_21_19 [3] */
5228 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
5229 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
5230 /* IP9_18_17 [2] */
5231 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
5232 /* IP9_16_15 [2] */
5233 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
5234 /* IP9_14_12 [3] */
5235 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
5236 0, FN_FMIN_B, 0, 0,
5237 /* IP9_11_9 [3] */
5238 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
5239 0, FN_FMCLK_B, 0, 0,
5240 /* IP9_8_6 [3] */
5241 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
5242 0, FN_BPFCLK_B, 0, 0,
5243 /* IP9_5_3 [3] */
5244 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
5245 0, FN_TPUTO1_C, 0, 0,
5246 /* IP9_2_0 [3] */
5247 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
5248 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
5249 },
5250 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5251 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5252 /* IP10_31_30 [2] */
5253 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
5254 /* IP10_29_27 [3] */
5255 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
5256 0, 0, 0, 0,
5257 /* IP10_26_24 [3] */
5258 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
5259 FN_SSI_SDATA4_B, 0, 0, 0,
5260 /* IP10_23_21 [3] */
5261 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
5262 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
5263 /* IP10_20_18 [3] */
5264 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
5265 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
5266 /* IP10_17_15 [3] */
5267 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
5268 FN_SSI_SDATA9_B, 0, 0, 0,
5269 /* IP10_14_12 [3] */
5270 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
5271 0, 0, 0, 0,
5272 /* IP10_11_9 [3] */
5273 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
5274 0, 0, 0, 0,
5275 /* IP10_8_6 [3] */
5276 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
5277 0, 0, 0, 0,
5278 /* IP10_5_3 [3] */
5279 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
5280 0, 0, 0, 0,
5281 /* IP10_2_0 [3] */
5282 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
5283 0, 0, 0, 0, }
5284 },
5285 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5286 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
5287 /* IP11_31_30 [2] */
5288 0, 0, 0, 0,
5289 /* IP11_29_27 [3] */
5290 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
5291 0, 0, 0, 0,
5292 /* IP11_26_24 [3] */
5293 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
5294 0, 0, 0, 0,
5295 /* IP11_23_21 [3] */
5296 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
5297 0, 0, 0, 0,
5298 /* IP11_20_18 [3] */
5299 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
5300 FN_CAN_CLK_D, 0, 0, 0,
5301 /* IP11_17_16 [2] */
5302 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
5303 /* IP11_15_14 [2] */
5304 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
5305 /* IP11_13_11 [3] */
5306 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
5307 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
5308 /* IP11_10_8 [3] */
5309 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
5310 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
5311 /* IP11_7_6 [2] */
5312 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
5313 /* IP11_5_3 [3] */
5314 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
5315 0, 0, 0, 0,
5316 /* IP11_2_0 [3] */
5317 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
5318 0, 0, 0, 0, }
5319 },
5320 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5321 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
5322 /* IP12_31_30 [2] */
5323 0, 0, 0, 0,
5324 /* IP12_29_27 [3] */
5325 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
5326 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
5327 /* IP12_26_24 [3] */
5328 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
5329 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
5330 /* IP12_23_21 [3] */
5331 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
5332 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
5333 /* IP12_20_18 [3] */
5334 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
5335 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
5336 /* IP12_17_15 [3] */
5337 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
5338 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
5339 /* IP12_14_13 [2] */
5340 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
5341 /* IP12_12_11 [2] */
5342 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
5343 /* IP12_10_9 [2] */
5344 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
5345 /* IP12_8_6 [3] */
5346 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
5347 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
5348 /* IP12_5_3 [3] */
5349 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
5350 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
5351 /* IP12_2_0 [3] */
5352 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
5353 0, FN_DREQ1_N_B, 0, 0, }
5354 },
5355 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5356 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5357 /* IP13_31 [1] */
5358 0, 0,
5359 /* IP13_30 [1] */
5360 0, 0,
5361 /* IP13_29 [1] */
5362 0, 0,
5363 /* IP13_28 [1] */
5364 0, 0,
5365 /* IP13_27 [1] */
5366 0, 0,
5367 /* IP13_26_24 [3] */
5368 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
5369 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
5370 /* IP13_23_21 [3] */
5371 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
5372 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
5373 /* IP13_20_18 [3] */
5374 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
5375 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
5376 /* IP13_17_15 [3] */
5377 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
5378 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
5379 /* IP13_14_12 [3] */
5380 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
5381 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
5382 /* IP13_11_9 [3] */
5383 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
5384 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
5385 /* IP13_8_6 [3] */
5386 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
5387 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
5388 /* IP13_5_3 [2] */
5389 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
5390 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5391 /* IP13_2_0 [3] */
5392 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
5393 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
5394 },
5395 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5396 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
5397 2, 1) {
5398 /* SEL_ADG [2] */
5399 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
5400 /* RESERVED [1] */
5401 0, 0,
5402 /* SEL_CAN [2] */
5403 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
5404 /* SEL_DARC [3] */
5405 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
5406 FN_SEL_DARC_4, 0, 0, 0,
5407 /* RESERVED [4] */
5408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5409 /* SEL_ETH [1] */
5410 FN_SEL_ETH_0, FN_SEL_ETH_1,
5411 /* RESERVED [1] */
5412 0, 0,
5413 /* SEL_IC200 [3] */
5414 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
5415 FN_SEL_I2C00_4, 0, 0, 0,
5416 /* SEL_I2C01 [3] */
5417 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
5418 FN_SEL_I2C01_4, 0, 0, 0,
5419 /* SEL_I2C02 [3] */
5420 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
5421 FN_SEL_I2C02_4, 0, 0, 0,
5422 /* SEL_I2C03 [3] */
5423 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
5424 FN_SEL_I2C03_4, 0, 0, 0,
5425 /* SEL_I2C04 [3] */
5426 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
5427 FN_SEL_I2C04_4, 0, 0, 0,
5428 /* SEL_I2C05 [2] */
5429 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
5430 /* RESERVED [1] */
5431 0, 0, }
5432 },
5433 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5434 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
5435 2, 2, 2, 1, 1, 2) {
5436 /* SEL_IEB [2] */
5437 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5438 /* SEL_IIC0 [2] */
5439 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
5440 /* SEL_LBS [1] */
5441 FN_SEL_LBS_0, FN_SEL_LBS_1,
5442 /* SEL_MSI1 [1] */
5443 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
5444 /* SEL_MSI2 [1] */
5445 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
5446 /* SEL_RAD [1] */
5447 FN_SEL_RAD_0, FN_SEL_RAD_1,
5448 /* SEL_RCN [1] */
5449 FN_SEL_RCN_0, FN_SEL_RCN_1,
5450 /* SEL_RSP [1] */
5451 FN_SEL_RSP_0, FN_SEL_RSP_1,
5452 /* SEL_SCIFA0 [2] */
5453 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
5454 FN_SEL_SCIFA0_3,
5455 /* SEL_SCIFA1 [2] */
5456 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5457 /* SEL_SCIFA2 [1] */
5458 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5459 /* SEL_SCIFA3 [1] */
5460 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
5461 /* SEL_SCIFA4 [2] */
5462 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
5463 FN_SEL_SCIFA4_3,
5464 /* SEL_SCIFA5 [2] */
5465 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
5466 FN_SEL_SCIFA5_3,
5467 /* RESERVED [1] */
5468 0, 0,
5469 /* SEL_TMU [1] */
5470 FN_SEL_TMU_0, FN_SEL_TMU_1,
5471 /* SEL_TSIF0 [2] */
5472 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5473 /* SEL_CAN0 [2] */
5474 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5475 /* SEL_CAN1 [2] */
5476 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5477 /* SEL_HSCIF0 [1] */
5478 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5479 /* SEL_HSCIF1 [1] */
5480 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5481 /* RESERVED [2] */
5482 0, 0, 0, 0, }
5483 },
5484 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5485 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
5486 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
5487 /* SEL_SCIF0 [2] */
5488 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5489 /* SEL_SCIF1 [2] */
5490 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5491 /* SEL_SCIF2 [2] */
5492 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5493 /* SEL_SCIF3 [1] */
5494 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
5495 /* SEL_SCIF4 [3] */
5496 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
5497 FN_SEL_SCIF4_4, 0, 0, 0,
5498 /* SEL_SCIF5 [2] */
5499 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
5500 /* SEL_SSI1 [1] */
5501 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5502 /* SEL_SSI2 [1] */
5503 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
5504 /* SEL_SSI4 [1] */
5505 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
5506 /* SEL_SSI5 [1] */
5507 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
5508 /* SEL_SSI6 [1] */
5509 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5510 /* SEL_SSI7 [1] */
5511 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5512 /* SEL_SSI8 [1] */
5513 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
5514 /* SEL_SSI9 [1] */
5515 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5516 /* RESERVED [1] */
5517 0, 0,
5518 /* RESERVED [1] */
5519 0, 0,
5520 /* RESERVED [1] */
5521 0, 0,
5522 /* RESERVED [1] */
5523 0, 0,
5524 /* RESERVED [1] */
5525 0, 0,
5526 /* RESERVED [1] */
5527 0, 0,
5528 /* RESERVED [1] */
5529 0, 0,
5530 /* RESERVED [1] */
5531 0, 0,
5532 /* RESERVED [1] */
5533 0, 0,
5534 /* RESERVED [1] */
5535 0, 0,
5536 /* RESERVED [1] */
5537 0, 0,
5538 /* RESERVED [1] */
5539 0, 0, }
5540 },
5541 { },
5542};
5543
5544static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5545{
5546 *pocctrl = 0xe606006c;
5547
5548 switch (pin & 0x1f) {
5549 case 6: return 23;
5550 case 7: return 16;
5551 case 14: return 15;
5552 case 15: return 8;
5553 case 0 ... 5:
5554 case 8 ... 13:
5555 return 22 - (pin & 0x1f);
5556 case 16 ... 23:
5557 return 47 - (pin & 0x1f);
5558 }
5559
5560 return -EINVAL;
5561}
5562
5563static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5564 .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5565};
5566
5567#ifdef CONFIG_PINCTRL_PFC_R8A7745
5568const struct sh_pfc_soc_info r8a7745_pinmux_info = {
5569 .name = "r8a77450_pfc",
5570 .ops = &r8a7794_pinmux_ops,
5571 .unlock_reg = 0xe6060000, /* PMMR */
5572
5573 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5574
5575 .pins = pinmux_pins,
5576 .nr_pins = ARRAY_SIZE(pinmux_pins),
5577 .groups = pinmux_groups,
5578 .nr_groups = ARRAY_SIZE(pinmux_groups),
5579 .functions = pinmux_functions,
5580 .nr_functions = ARRAY_SIZE(pinmux_functions),
5581
5582 .cfg_regs = pinmux_config_regs,
5583
5584 .pinmux_data = pinmux_data,
5585 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5586};
5587#endif
5588
5589#ifdef CONFIG_PINCTRL_PFC_R8A7794
5590const struct sh_pfc_soc_info r8a7794_pinmux_info = {
5591 .name = "r8a77940_pfc",
5592 .ops = &r8a7794_pinmux_ops,
5593 .unlock_reg = 0xe6060000, /* PMMR */
5594
5595 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5596
5597 .pins = pinmux_pins,
5598 .nr_pins = ARRAY_SIZE(pinmux_pins),
5599 .groups = pinmux_groups,
5600 .nr_groups = ARRAY_SIZE(pinmux_groups),
5601 .functions = pinmux_functions,
5602 .nr_functions = ARRAY_SIZE(pinmux_functions),
5603
5604 .cfg_regs = pinmux_config_regs,
5605
5606 .pinmux_data = pinmux_data,
5607 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5608};
5609#endif