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1Qualcomm QMP PHY controller
2===========================
3
4QMP phy controller supports physical layer functionality for a number of
5controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
6
7Required properties:
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
13 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
14 "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
15
16- reg:
17 - index 0: address and length of register set for PHY's common
18 serdes block.
19 - index 1: address and length of the DP_COM control block (for
20 "qcom,sdm845-qmp-usb3-phy" only).
21
22- reg-names:
23 - For "qcom,sdm845-qmp-usb3-phy":
24 - Should be: "reg-base", "dp_com"
25 - For all others:
26 - The reg-names property shouldn't be defined.
27
28 - #clock-cells: must be 1
29 - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
30 interface (for pipe based PHYs). These clock are then gate-controlled
31 by gcc.
32 - #address-cells: must be 1
33 - #size-cells: must be 1
34 - ranges: must be present
35
36 - clocks: a list of phandles and clock-specifier pairs,
37 one for each entry in clock-names.
38 - clock-names: "cfg_ahb" for phy config clock,
39 "aux" for phy aux clock,
40 "ref" for 19.2 MHz ref clk,
41 "com_aux" for phy common block aux clock,
42 "ref_aux" for phy reference aux clock,
43 For "qcom,msm8996-qmp-pcie-phy" must contain:
44 "aux", "cfg_ahb", "ref".
45 For "qcom,msm8996-qmp-usb3-phy" must contain:
46 "aux", "cfg_ahb", "ref".
47 For "qcom,qmp-v3-usb3-phy" must contain:
48 "aux", "cfg_ahb", "ref", "com_aux".
49
50 - resets: a list of phandles and reset controller specifier pairs,
51 one for each entry in reset-names.
52 - reset-names: "phy" for reset of phy block,
53 "common" for phy common block reset,
54 "cfg" for phy's ahb cfg block reset (Optional).
55 For "qcom,msm8996-qmp-pcie-phy" must contain:
56 "phy", "common", "cfg".
57 For "qcom,msm8996-qmp-usb3-phy" must contain
58 "phy", "common".
59 For "qcom,ipq8074-qmp-pcie-phy" must contain:
60 "phy", "common".
61
62 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
63 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
64
65Optional properties:
66 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
67 pll block.
68
69Required nodes:
70 - Each device node of QMP phy is required to have as many child nodes as
71 the number of lanes the PHY has.
72
73Required properties for child node:
74 - reg: list of offset and length pairs of register sets for PHY blocks -
75 - index 0: tx
76 - index 1: rx
77 - index 2: pcs
78 - index 3: pcs_misc (optional)
79
80 - #phy-cells: must be 0
81
82 - clocks: a list of phandles and clock-specifier pairs,
83 one for each entry in clock-names.
84 - clock-names: Must contain following for pcie and usb qmp phys:
85 "pipe<lane-number>" for pipe clock specific to each lane.
86 - clock-output-names: Name of the PHY clock that will be the parent for
87 the above pipe clock.
88
89 For "qcom,ipq8074-qmp-pcie-phy":
90 - "pcie20_phy0_pipe_clk" Pipe Clock parent
91 (or)
92 "pcie20_phy1_pipe_clk"
93
94 - resets: a list of phandles and reset controller specifier pairs,
95 one for each entry in reset-names.
96 - reset-names: Must contain following for pcie qmp phys:
97 "lane<lane-number>" for reset specific to each lane.
98
99Example:
100 phy@34000 {
101 compatible = "qcom,msm8996-qmp-pcie-phy";
102 reg = <0x34000 0x488>;
103 #clock-cells = <1>;
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges;
107
108 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
109 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
110 <&gcc GCC_PCIE_CLKREF_CLK>;
111 clock-names = "aux", "cfg_ahb", "ref";
112
113 vdda-phy-supply = <&pm8994_l28>;
114 vdda-pll-supply = <&pm8994_l12>;
115
116 resets = <&gcc GCC_PCIE_PHY_BCR>,
117 <&gcc GCC_PCIE_PHY_COM_BCR>,
118 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
119 reset-names = "phy", "common", "cfg";
120
121 pciephy_0: lane@35000 {
122 reg = <0x35000 0x130>,
123 <0x35200 0x200>,
124 <0x35400 0x1dc>;
125 #phy-cells = <0>;
126
127 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
128 clock-names = "pipe0";
129 clock-output-names = "pcie_0_pipe_clk_src";
130 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
131 reset-names = "lane0";
132 };
133
134 pciephy_1: lane@36000 {
135 ...
136 ...
137 };