tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
5 */
6
7#ifndef _CAAMALG_QI2_H_
8#define _CAAMALG_QI2_H_
9
10#include <soc/fsl/dpaa2-io.h>
11#include <soc/fsl/dpaa2-fd.h>
12#include <linux/threads.h>
13#include "dpseci.h"
14#include "desc_constr.h"
15
16#define DPAA2_CAAM_STORE_SIZE 16
17/* NAPI weight *must* be a multiple of the store size. */
18#define DPAA2_CAAM_NAPI_WEIGHT 64
19
20/* The congestion entrance threshold was chosen so that on LS2088
21 * we support the maximum throughput for the available memory
22 */
23#define DPAA2_SEC_CONG_ENTRY_THRESH (128 * 1024 * 1024)
24#define DPAA2_SEC_CONG_EXIT_THRESH (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
25
26/**
27 * dpaa2_caam_priv - driver private data
28 * @dpseci_id: DPSECI object unique ID
29 * @major_ver: DPSECI major version
30 * @minor_ver: DPSECI minor version
31 * @dpseci_attr: DPSECI attributes
32 * @sec_attr: SEC engine attributes
33 * @rx_queue_attr: array of Rx queue attributes
34 * @tx_queue_attr: array of Tx queue attributes
35 * @cscn_mem: pointer to memory region containing the congestion SCN
36 * it's size is larger than to accommodate alignment
37 * @cscn_mem_aligned: pointer to congestion SCN; it is computed as
38 * PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
39 * @cscn_dma: dma address used by the QMAN to write CSCN messages
40 * @dev: device associated with the DPSECI object
41 * @mc_io: pointer to MC portal's I/O object
42 * @domain: IOMMU domain
43 * @ppriv: per CPU pointers to privata data
44 */
45struct dpaa2_caam_priv {
46 int dpsec_id;
47
48 u16 major_ver;
49 u16 minor_ver;
50
51 struct dpseci_attr dpseci_attr;
52 struct dpseci_sec_attr sec_attr;
53 struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
54 struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
55 int num_pairs;
56
57 /* congestion */
58 void *cscn_mem;
59 void *cscn_mem_aligned;
60 dma_addr_t cscn_dma;
61
62 struct device *dev;
63 struct fsl_mc_io *mc_io;
64 struct iommu_domain *domain;
65
66 struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
67};
68
69/**
70 * dpaa2_caam_priv_per_cpu - per CPU private data
71 * @napi: napi structure
72 * @net_dev: netdev used by napi
73 * @req_fqid: (virtual) request (Tx / enqueue) FQID
74 * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
75 * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
76 * @nctx: notification context of response FQ
77 * @store: where dequeued frames are stored
78 * @priv: backpointer to dpaa2_caam_priv
79 */
80struct dpaa2_caam_priv_per_cpu {
81 struct napi_struct napi;
82 struct net_device net_dev;
83 int req_fqid;
84 int rsp_fqid;
85 int prio;
86 struct dpaa2_io_notification_ctx nctx;
87 struct dpaa2_io_store *store;
88 struct dpaa2_caam_priv *priv;
89};
90
91/*
92 * The CAAM QI hardware constructs a job descriptor which points
93 * to shared descriptor (as pointed by context_a of FQ to CAAM).
94 * When the job descriptor is executed by deco, the whole job
95 * descriptor together with shared descriptor gets loaded in
96 * deco buffer which is 64 words long (each 32-bit).
97 *
98 * The job descriptor constructed by QI hardware has layout:
99 *
100 * HEADER (1 word)
101 * Shdesc ptr (1 or 2 words)
102 * SEQ_OUT_PTR (1 word)
103 * Out ptr (1 or 2 words)
104 * Out length (1 word)
105 * SEQ_IN_PTR (1 word)
106 * In ptr (1 or 2 words)
107 * In length (1 word)
108 *
109 * The shdesc ptr is used to fetch shared descriptor contents
110 * into deco buffer.
111 *
112 * Apart from shdesc contents, the total number of words that
113 * get loaded in deco buffer are '8' or '11'. The remaining words
114 * in deco buffer can be used for storing shared descriptor.
115 */
116#define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
117
118/* Length of a single buffer in the QI driver memory cache */
119#define CAAM_QI_MEMCACHE_SIZE 512
120
121/*
122 * aead_edesc - s/w-extended aead descriptor
123 * @src_nents: number of segments in input scatterlist
124 * @dst_nents: number of segments in output scatterlist
125 * @iv_dma: dma address of iv for checking continuity and link table
126 * @qm_sg_bytes: length of dma mapped h/w link table
127 * @qm_sg_dma: bus physical mapped address of h/w link table
128 * @assoclen: associated data length, in CAAM endianness
129 * @assoclen_dma: bus physical mapped address of req->assoclen
130 * @sgt: the h/w link table, followed by IV
131 */
132struct aead_edesc {
133 int src_nents;
134 int dst_nents;
135 dma_addr_t iv_dma;
136 int qm_sg_bytes;
137 dma_addr_t qm_sg_dma;
138 unsigned int assoclen;
139 dma_addr_t assoclen_dma;
140 struct dpaa2_sg_entry sgt[0];
141};
142
143/*
144 * skcipher_edesc - s/w-extended skcipher descriptor
145 * @src_nents: number of segments in input scatterlist
146 * @dst_nents: number of segments in output scatterlist
147 * @iv_dma: dma address of iv for checking continuity and link table
148 * @qm_sg_bytes: length of dma mapped qm_sg space
149 * @qm_sg_dma: I/O virtual address of h/w link table
150 * @sgt: the h/w link table, followed by IV
151 */
152struct skcipher_edesc {
153 int src_nents;
154 int dst_nents;
155 dma_addr_t iv_dma;
156 int qm_sg_bytes;
157 dma_addr_t qm_sg_dma;
158 struct dpaa2_sg_entry sgt[0];
159};
160
161/*
162 * ahash_edesc - s/w-extended ahash descriptor
163 * @dst_dma: I/O virtual address of req->result
164 * @qm_sg_dma: I/O virtual address of h/w link table
165 * @src_nents: number of segments in input scatterlist
166 * @qm_sg_bytes: length of dma mapped qm_sg space
167 * @sgt: pointer to h/w link table
168 */
169struct ahash_edesc {
170 dma_addr_t dst_dma;
171 dma_addr_t qm_sg_dma;
172 int src_nents;
173 int qm_sg_bytes;
174 struct dpaa2_sg_entry sgt[0];
175};
176
177/**
178 * caam_flc - Flow Context (FLC)
179 * @flc: Flow Context options
180 * @sh_desc: Shared Descriptor
181 */
182struct caam_flc {
183 u32 flc[16];
184 u32 sh_desc[MAX_SDLEN];
185} ____cacheline_aligned;
186
187enum optype {
188 ENCRYPT = 0,
189 DECRYPT,
190 NUM_OP
191};
192
193/**
194 * caam_request - the request structure the driver application should fill while
195 * submitting a job to driver.
196 * @fd_flt: Frame list table defining input and output
197 * fd_flt[0] - FLE pointing to output buffer
198 * fd_flt[1] - FLE pointing to input buffer
199 * @fd_flt_dma: DMA address for the frame list table
200 * @flc: Flow Context
201 * @flc_dma: I/O virtual address of Flow Context
202 * @cbk: Callback function to invoke when job is completed
203 * @ctx: arbit context attached with request by the application
204 * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
205 */
206struct caam_request {
207 struct dpaa2_fl_entry fd_flt[2];
208 dma_addr_t fd_flt_dma;
209 struct caam_flc *flc;
210 dma_addr_t flc_dma;
211 void (*cbk)(void *ctx, u32 err);
212 void *ctx;
213 void *edesc;
214};
215
216/**
217 * dpaa2_caam_enqueue() - enqueue a crypto request
218 * @dev: device associated with the DPSECI object
219 * @req: pointer to caam_request
220 */
221int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
222
223#endif /* _CAAMALG_QI2_H_ */