tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Based on arch/arm/include/asm/traps.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __ASM_TRAP_H
19#define __ASM_TRAP_H
20
21#include <linux/list.h>
22#include <asm/esr.h>
23#include <asm/sections.h>
24
25struct pt_regs;
26
27struct undef_hook {
28 struct list_head node;
29 u32 instr_mask;
30 u32 instr_val;
31 u64 pstate_mask;
32 u64 pstate_val;
33 int (*fn)(struct pt_regs *regs, u32 instr);
34};
35
36void register_undef_hook(struct undef_hook *hook);
37void unregister_undef_hook(struct undef_hook *hook);
38void force_signal_inject(int signal, int code, unsigned long address);
39void arm64_notify_segfault(unsigned long addr);
40void arm64_force_sig_fault(int signo, int code, void __user *addr, const char *str);
41void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, const char *str);
42void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr, const char *str);
43
44/*
45 * Move regs->pc to next instruction and do necessary setup before it
46 * is executed.
47 */
48void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
49
50static inline int __in_irqentry_text(unsigned long ptr)
51{
52 return ptr >= (unsigned long)&__irqentry_text_start &&
53 ptr < (unsigned long)&__irqentry_text_end;
54}
55
56static inline int in_exception_text(unsigned long ptr)
57{
58 int in;
59
60 in = ptr >= (unsigned long)&__exception_text_start &&
61 ptr < (unsigned long)&__exception_text_end;
62
63 return in ? : __in_irqentry_text(ptr);
64}
65
66static inline int in_entry_text(unsigned long ptr)
67{
68 return ptr >= (unsigned long)&__entry_text_start &&
69 ptr < (unsigned long)&__entry_text_end;
70}
71
72/*
73 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
74 * to indicate whether this ESR has a RAS encoding. CPUs without this feature
75 * have a ISS-Valid bit in the same position.
76 * If this bit is set, we know its not a RAS SError.
77 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
78 * errors share the same encoding as an all-zeros encoding from a CPU that
79 * doesn't support RAS.
80 */
81static inline bool arm64_is_ras_serror(u32 esr)
82{
83 WARN_ON(preemptible());
84
85 if (esr & ESR_ELx_IDS)
86 return false;
87
88 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
89 return true;
90 else
91 return false;
92}
93
94/*
95 * Return the AET bits from a RAS SError's ESR.
96 *
97 * It is implementation defined whether Uncategorized errors are containable.
98 * We treat them as Uncontainable.
99 * Non-RAS SError's are reported as Uncontained/Uncategorized.
100 */
101static inline u32 arm64_ras_serror_get_severity(u32 esr)
102{
103 u32 aet = esr & ESR_ELx_AET;
104
105 if (!arm64_is_ras_serror(esr)) {
106 /* Not a RAS error, we can't interpret the ESR. */
107 return ESR_ELx_AET_UC;
108 }
109
110 /*
111 * AET is RES0 if 'the value returned in the DFSC field is not
112 * [ESR_ELx_FSC_SERROR]'
113 */
114 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
115 /* No severity information : Uncategorized */
116 return ESR_ELx_AET_UC;
117 }
118
119 return aet;
120}
121
122bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr);
123void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr);
124#endif