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1/* linux/include/asm-arm/arch-msm/hsusb.h
2 *
3 * Copyright (C) 2008 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __ASM_ARCH_MSM_HSUSB_H
19#define __ASM_ARCH_MSM_HSUSB_H
20
21#include <linux/extcon.h>
22#include <linux/types.h>
23#include <linux/usb/otg.h>
24#include <linux/clk.h>
25
26/**
27 * OTG control
28 *
29 * OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host
30 * only configuration.
31 * OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY.
32 * OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware.
33 * OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs.
34 *
35 */
36enum otg_control_type {
37 OTG_NO_CONTROL = 0,
38 OTG_PHY_CONTROL,
39 OTG_PMIC_CONTROL,
40 OTG_USER_CONTROL,
41};
42
43/**
44 * PHY used in
45 *
46 * INVALID_PHY Unsupported PHY
47 * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
48 * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
49 *
50 */
51enum msm_usb_phy_type {
52 INVALID_PHY = 0,
53 CI_45NM_INTEGRATED_PHY,
54 SNPS_28NM_INTEGRATED_PHY,
55};
56
57#define IDEV_CHG_MAX 1500
58#define IUNIT 100
59
60/**
61 * Different states involved in USB charger detection.
62 *
63 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
64 * process is not yet started.
65 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
66 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
67 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
68 * between SDP and DCP/CDP).
69 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
70 * between DCP and CDP).
71 * USB_CHG_STATE_DETECTED USB charger type is determined.
72 *
73 */
74enum usb_chg_state {
75 USB_CHG_STATE_UNDEFINED = 0,
76 USB_CHG_STATE_WAIT_FOR_DCD,
77 USB_CHG_STATE_DCD_DONE,
78 USB_CHG_STATE_PRIMARY_DONE,
79 USB_CHG_STATE_SECONDARY_DONE,
80 USB_CHG_STATE_DETECTED,
81};
82
83/**
84 * USB charger types
85 *
86 * USB_INVALID_CHARGER Invalid USB charger.
87 * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
88 * on USB2.0 compliant host/hub.
89 * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
90 * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
91 * IDEV_CHG_MAX can be drawn irrespective of USB state.
92 *
93 */
94enum usb_chg_type {
95 USB_INVALID_CHARGER = 0,
96 USB_SDP_CHARGER,
97 USB_DCP_CHARGER,
98 USB_CDP_CHARGER,
99};
100
101/**
102 * struct msm_otg_platform_data - platform device data
103 * for msm_otg driver.
104 * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as
105 * "do not overwrite default vaule at this address".
106 * @phy_init_sz: PHY configuration sequence size.
107 * @vbus_power: VBUS power on/off routine.
108 * @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
109 * @mode: Supported mode (OTG/peripheral/host).
110 * @otg_control: OTG switch controlled by user/Id pin
111 */
112struct msm_otg_platform_data {
113 int *phy_init_seq;
114 int phy_init_sz;
115 void (*vbus_power)(bool on);
116 unsigned power_budget;
117 enum usb_dr_mode mode;
118 enum otg_control_type otg_control;
119 enum msm_usb_phy_type phy_type;
120 void (*setup_gpio)(enum usb_otg_state state);
121};
122
123/**
124 * struct msm_usb_cable - structure for exteternal connector cable
125 * state tracking
126 * @nb: hold event notification callback
127 * @conn: used for notification registration
128 */
129struct msm_usb_cable {
130 struct notifier_block nb;
131 struct extcon_specific_cable_nb conn;
132};
133
134/**
135 * struct msm_otg: OTG driver data. Shared by HCD and DCD.
136 * @otg: USB OTG Transceiver structure.
137 * @pdata: otg device platform data.
138 * @irq: IRQ number assigned for HSUSB controller.
139 * @clk: clock struct of usb_hs_clk.
140 * @pclk: clock struct of usb_hs_pclk.
141 * @core_clk: clock struct of usb_hs_core_clk.
142 * @regs: ioremapped register base address.
143 * @inputs: OTG state machine inputs(Id, SessValid etc).
144 * @sm_work: OTG state machine work.
145 * @in_lpm: indicates low power mode (LPM) state.
146 * @async_int: Async interrupt arrived.
147 * @cur_power: The amount of mA available from downstream port.
148 * @chg_work: Charger detection work.
149 * @chg_state: The state of charger detection process.
150 * @chg_type: The type of charger attached.
151 * @dcd_retires: The retry count used to track Data contact
152 * detection process.
153 * @manual_pullup: true if VBUS is not routed to USB controller/phy
154 * and controller driver therefore enables pull-up explicitly before
155 * starting controller using usbcmd run/stop bit.
156 * @vbus: VBUS signal state trakining, using extcon framework
157 * @id: ID signal state trakining, using extcon framework
158 */
159struct msm_otg {
160 struct usb_phy phy;
161 struct msm_otg_platform_data *pdata;
162 int irq;
163 struct clk *clk;
164 struct clk *pclk;
165 struct clk *core_clk;
166 void __iomem *regs;
167#define ID 0
168#define B_SESS_VLD 1
169 unsigned long inputs;
170 struct work_struct sm_work;
171 atomic_t in_lpm;
172 int async_int;
173 unsigned cur_power;
174 int phy_number;
175 struct delayed_work chg_work;
176 enum usb_chg_state chg_state;
177 enum usb_chg_type chg_type;
178 u8 dcd_retries;
179 struct regulator *v3p3;
180 struct regulator *v1p8;
181 struct regulator *vddcx;
182
183 struct reset_control *phy_rst;
184 struct reset_control *link_rst;
185 int vdd_levels[3];
186
187 bool manual_pullup;
188
189 struct msm_usb_cable vbus;
190 struct msm_usb_cable id;
191};
192
193#endif