Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
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linux
1/*
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clocksource.h>
18#include <linux/clockchips.h>
19#include <linux/cpu.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/sched_clock.h>
28
29#include <asm/delay.h>
30
31#define TIMER_MATCH_VAL 0x0000
32#define TIMER_COUNT_VAL 0x0004
33#define TIMER_ENABLE 0x0008
34#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
35#define TIMER_ENABLE_EN BIT(0)
36#define TIMER_CLEAR 0x000C
37#define DGT_CLK_CTL 0x10
38#define DGT_CLK_CTL_DIV_4 0x3
39#define TIMER_STS_GPT0_CLR_PEND BIT(10)
40
41#define GPT_HZ 32768
42
43static void __iomem *event_base;
44static void __iomem *sts_base;
45
46static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
47{
48 struct clock_event_device *evt = dev_id;
49 /* Stop the timer tick */
50 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
51 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
52 ctrl &= ~TIMER_ENABLE_EN;
53 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
54 }
55 evt->event_handler(evt);
56 return IRQ_HANDLED;
57}
58
59static int msm_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt)
61{
62 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
63
64 ctrl &= ~TIMER_ENABLE_EN;
65 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
66
67 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
68 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
69
70 if (sts_base)
71 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
72 cpu_relax();
73
74 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
75 return 0;
76}
77
78static void msm_timer_set_mode(enum clock_event_mode mode,
79 struct clock_event_device *evt)
80{
81 u32 ctrl;
82
83 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
84 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
85
86 switch (mode) {
87 case CLOCK_EVT_MODE_RESUME:
88 case CLOCK_EVT_MODE_PERIODIC:
89 break;
90 case CLOCK_EVT_MODE_ONESHOT:
91 /* Timer is enabled in set_next_event */
92 break;
93 case CLOCK_EVT_MODE_UNUSED:
94 case CLOCK_EVT_MODE_SHUTDOWN:
95 break;
96 }
97 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
98}
99
100static struct clock_event_device __percpu *msm_evt;
101
102static void __iomem *source_base;
103
104static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
105{
106 return readl_relaxed(source_base + TIMER_COUNT_VAL);
107}
108
109static struct clocksource msm_clocksource = {
110 .name = "dg_timer",
111 .rating = 300,
112 .read = msm_read_timer_count,
113 .mask = CLOCKSOURCE_MASK(32),
114 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
115};
116
117static int msm_timer_irq;
118static int msm_timer_has_ppi;
119
120static int msm_local_timer_setup(struct clock_event_device *evt)
121{
122 int cpu = smp_processor_id();
123 int err;
124
125 evt->irq = msm_timer_irq;
126 evt->name = "msm_timer";
127 evt->features = CLOCK_EVT_FEAT_ONESHOT;
128 evt->rating = 200;
129 evt->set_mode = msm_timer_set_mode;
130 evt->set_next_event = msm_timer_set_next_event;
131 evt->cpumask = cpumask_of(cpu);
132
133 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
134
135 if (msm_timer_has_ppi) {
136 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
137 } else {
138 err = request_irq(evt->irq, msm_timer_interrupt,
139 IRQF_TIMER | IRQF_NOBALANCING |
140 IRQF_TRIGGER_RISING, "gp_timer", evt);
141 if (err)
142 pr_err("request_irq failed\n");
143 }
144
145 return 0;
146}
147
148static void msm_local_timer_stop(struct clock_event_device *evt)
149{
150 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
151 disable_percpu_irq(evt->irq);
152}
153
154static int msm_timer_cpu_notify(struct notifier_block *self,
155 unsigned long action, void *hcpu)
156{
157 /*
158 * Grab cpu pointer in each case to avoid spurious
159 * preemptible warnings
160 */
161 switch (action & ~CPU_TASKS_FROZEN) {
162 case CPU_STARTING:
163 msm_local_timer_setup(this_cpu_ptr(msm_evt));
164 break;
165 case CPU_DYING:
166 msm_local_timer_stop(this_cpu_ptr(msm_evt));
167 break;
168 }
169
170 return NOTIFY_OK;
171}
172
173static struct notifier_block msm_timer_cpu_nb = {
174 .notifier_call = msm_timer_cpu_notify,
175};
176
177static u64 notrace msm_sched_clock_read(void)
178{
179 return msm_clocksource.read(&msm_clocksource);
180}
181
182static unsigned long msm_read_current_timer(void)
183{
184 return msm_clocksource.read(&msm_clocksource);
185}
186
187static struct delay_timer msm_delay_timer = {
188 .read_current_timer = msm_read_current_timer,
189};
190
191static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
192 bool percpu)
193{
194 struct clocksource *cs = &msm_clocksource;
195 int res = 0;
196
197 msm_timer_irq = irq;
198 msm_timer_has_ppi = percpu;
199
200 msm_evt = alloc_percpu(struct clock_event_device);
201 if (!msm_evt) {
202 pr_err("memory allocation failed for clockevents\n");
203 goto err;
204 }
205
206 if (percpu)
207 res = request_percpu_irq(irq, msm_timer_interrupt,
208 "gp_timer", msm_evt);
209
210 if (res) {
211 pr_err("request_percpu_irq failed\n");
212 } else {
213 res = register_cpu_notifier(&msm_timer_cpu_nb);
214 if (res) {
215 free_percpu_irq(irq, msm_evt);
216 goto err;
217 }
218
219 /* Immediately configure the timer on the boot CPU */
220 msm_local_timer_setup(raw_cpu_ptr(msm_evt));
221 }
222
223err:
224 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
225 res = clocksource_register_hz(cs, dgt_hz);
226 if (res)
227 pr_err("clocksource_register failed\n");
228 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
229 msm_delay_timer.freq = dgt_hz;
230 register_current_timer_delay(&msm_delay_timer);
231}
232
233static void __init msm_dt_timer_init(struct device_node *np)
234{
235 u32 freq;
236 int irq;
237 struct resource res;
238 u32 percpu_offset;
239 void __iomem *base;
240 void __iomem *cpu0_base;
241
242 base = of_iomap(np, 0);
243 if (!base) {
244 pr_err("Failed to map event base\n");
245 return;
246 }
247
248 /* We use GPT0 for the clockevent */
249 irq = irq_of_parse_and_map(np, 1);
250 if (irq <= 0) {
251 pr_err("Can't get irq\n");
252 return;
253 }
254
255 /* We use CPU0's DGT for the clocksource */
256 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
257 percpu_offset = 0;
258
259 if (of_address_to_resource(np, 0, &res)) {
260 pr_err("Failed to parse DGT resource\n");
261 return;
262 }
263
264 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
265 if (!cpu0_base) {
266 pr_err("Failed to map source base\n");
267 return;
268 }
269
270 if (of_property_read_u32(np, "clock-frequency", &freq)) {
271 pr_err("Unknown frequency\n");
272 return;
273 }
274
275 event_base = base + 0x4;
276 sts_base = base + 0x88;
277 source_base = cpu0_base + 0x24;
278 freq /= 4;
279 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
280
281 msm_timer_init(freq, 32, irq, !!percpu_offset);
282}
283CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
284CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);