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1Rockchip specific extensions to the Synopsys Designware HDMI 2================================ 3 4Required properties: 5- compatible: "rockchip,rk3288-dw-hdmi"; 6- reg: Physical base address and length of the controller's registers. 7- clocks: phandle to hdmi iahb and isfr clocks. 8- clock-names: should be "iahb" "isfr" 9- rockchip,grf: this soc should set GRF regs to mux vopl/vopb. 10- interrupts: HDMI interrupt number 11- ports: contain a port node with endpoint definitions as defined in 12 Documentation/devicetree/bindings/media/video-interfaces.txt. For 13 vopb,set the reg = <0> and set the reg = <1> for vopl. 14- reg-io-width: the width of the reg:1,4, the value should be 4 on 15 rk3288 platform 16 17Optional properties 18- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 19- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec" 20 21Example: 22hdmi: hdmi@ff980000 { 23 compatible = "rockchip,rk3288-dw-hdmi"; 24 reg = <0xff980000 0x20000>; 25 reg-io-width = <4>; 26 ddc-i2c-bus = <&i2c5>; 27 rockchip,grf = <&grf>; 28 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 29 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 30 clock-names = "iahb", "isfr"; 31 status = "disabled"; 32 ports { 33 hdmi_in: port { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 hdmi_in_vopb: endpoint@0 { 37 reg = <0>; 38 remote-endpoint = <&vopb_out_hdmi>; 39 }; 40 hdmi_in_vopl: endpoint@1 { 41 reg = <1>; 42 remote-endpoint = <&vopl_out_hdmi>; 43 }; 44 }; 45 }; 46};