Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1#include <linux/bitops.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <linux/gpio.h>
5
6#define SCI_MAJOR 204
7#define SCI_MINOR_START 8
8
9
10/*
11 * SCI register subset common for all port types.
12 * Not all registers will exist on all parts.
13 */
14enum {
15 SCSMR, /* Serial Mode Register */
16 SCBRR, /* Bit Rate Register */
17 SCSCR, /* Serial Control Register */
18 SCxSR, /* Serial Status Register */
19 SCFCR, /* FIFO Control Register */
20 SCFDR, /* FIFO Data Count Register */
21 SCxTDR, /* Transmit (FIFO) Data Register */
22 SCxRDR, /* Receive (FIFO) Data Register */
23 SCLSR, /* Line Status Register */
24 SCTFDR, /* Transmit FIFO Data Count Register */
25 SCRFDR, /* Receive FIFO Data Count Register */
26 SCSPTR, /* Serial Port Register */
27 HSSRR, /* Sampling Rate Register */
28 SCPCR, /* Serial Port Control Register */
29 SCPDR, /* Serial Port Data Register */
30
31 SCIx_NR_REGS,
32};
33
34
35/* SCSMR (Serial Mode Register) */
36#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
37#define SCSMR_PE BIT(5) /* Parity Enable */
38#define SCSMR_ODD BIT(4) /* Odd Parity */
39#define SCSMR_STOP BIT(3) /* Stop Bit Length */
40#define SCSMR_CKS 0x0003 /* Clock Select */
41
42/* Serial Control Register, SCIFA/SCIFB only bits */
43#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
44#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
45
46/* SCxSR (Serial Status Register) on SCI */
47#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
48#define SCI_RDRF BIT(6) /* Receive Data Register Full */
49#define SCI_ORER BIT(5) /* Overrun Error */
50#define SCI_FER BIT(4) /* Framing Error */
51#define SCI_PER BIT(3) /* Parity Error */
52#define SCI_TEND BIT(2) /* Transmit End */
53#define SCI_RESERVED 0x03 /* All reserved bits */
54
55#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
56
57#define SCI_RDxF_CLEAR ~(SCI_RESERVED | SCI_RDRF)
58#define SCI_ERROR_CLEAR ~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)
59#define SCI_TDxE_CLEAR ~(SCI_RESERVED | SCI_TEND | SCI_TDRE)
60#define SCI_BREAK_CLEAR ~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)
61
62/* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
63#define SCIF_ER BIT(7) /* Receive Error */
64#define SCIF_TEND BIT(6) /* Transmission End */
65#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
66#define SCIF_BRK BIT(4) /* Break Detect */
67#define SCIF_FER BIT(3) /* Framing Error */
68#define SCIF_PER BIT(2) /* Parity Error */
69#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
70#define SCIF_DR BIT(0) /* Receive Data Ready */
71/* SCIF only (optional) */
72#define SCIF_PERC 0xf000 /* Number of Parity Errors */
73#define SCIF_FERC 0x0f00 /* Number of Framing Errors */
74/*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
75#define SCIFA_ORER BIT(9) /* Overrun Error */
76
77#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
78
79#define SCIF_RDxF_CLEAR ~(SCIF_DR | SCIF_RDF)
80#define SCIF_ERROR_CLEAR ~(SCIFA_ORER | SCIF_PER | SCIF_FER | SCIF_ER)
81#define SCIF_TDxE_CLEAR ~(SCIF_TDFE)
82#define SCIF_BREAK_CLEAR ~(SCIF_PER | SCIF_FER | SCIF_BRK)
83
84/* SCFCR (FIFO Control Register) */
85#define SCFCR_MCE BIT(3) /* Modem Control Enable */
86#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
87#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
88#define SCFCR_LOOP BIT(0) /* Loopback Test */
89
90/* SCLSR (Line Status Register) on (H)SCIF */
91#define SCLSR_ORER BIT(0) /* Overrun Error */
92
93/* SCSPTR (Serial Port Register), optional */
94#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */
95#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */
96#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */
97#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */
98#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
99#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
100
101/* HSSRR HSCIF */
102#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
103
104/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
105#define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */
106#define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */
107
108/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
109#define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */
110#define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */
111
112
113#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
114#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
115#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
116#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
117#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
118#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
119
120#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
121
122#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
123 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
124 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
125 defined(CONFIG_ARCH_SH73A0) || \
126 defined(CONFIG_ARCH_R8A7740)
127
128# define SCxSR_RDxF_CLEAR(port) \
129 (serial_port_in(port, SCxSR) & SCIF_RDxF_CLEAR)
130# define SCxSR_ERROR_CLEAR(port) \
131 (serial_port_in(port, SCxSR) & SCIF_ERROR_CLEAR)
132# define SCxSR_TDxE_CLEAR(port) \
133 (serial_port_in(port, SCxSR) & SCIF_TDxE_CLEAR)
134# define SCxSR_BREAK_CLEAR(port) \
135 (serial_port_in(port, SCxSR) & SCIF_BREAK_CLEAR)
136#else
137# define SCxSR_RDxF_CLEAR(port) \
138 ((((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR) & 0xff)
139# define SCxSR_ERROR_CLEAR(port) \
140 ((((port)->type == PORT_SCI) ? SCI_ERROR_CLEAR : SCIF_ERROR_CLEAR) & 0xff)
141# define SCxSR_TDxE_CLEAR(port) \
142 ((((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR) & 0xff)
143# define SCxSR_BREAK_CLEAR(port) \
144 ((((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR) & 0xff)
145#endif
146