Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef VI_H
24#define VI_H
25
26#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
27#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
28#define SDMA_MAX_INSTANCE 2
29
30/* crtc instance offsets */
31#define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
32#define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
33#define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
34#define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
35#define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
36#define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
37#define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
38
39/* dig instance offsets */
40#define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
41#define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
42#define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
43#define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
44#define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
45#define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
46#define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
47#define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
48#define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
49
50/* audio endpt instance offsets */
51#define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
52#define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
53#define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
54#define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
55#define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
56#define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
57#define AUD6_REGISTER_OFFSET (0x17c4 - 0x17a8)
58
59/* hpd instance offsets */
60#define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
61#define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
62#define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
63#define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
64#define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
65#define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
66
67#define AMDGPU_NUM_OF_VMIDS 8
68
69#define RB_BITMAP_WIDTH_PER_SH 2
70
71#define MC_SEQ_MISC0__MT__MASK 0xf0000000
72#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
73#define MC_SEQ_MISC0__MT__DDR2 0x20000000
74#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
75#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
76#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
77#define MC_SEQ_MISC0__MT__HBM 0x60000000
78#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
79
80/*
81 * PM4
82 */
83#define PACKET_TYPE0 0
84#define PACKET_TYPE1 1
85#define PACKET_TYPE2 2
86#define PACKET_TYPE3 3
87
88#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
89#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
90#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
91#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
92#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
93 ((reg) & 0xFFFF) | \
94 ((n) & 0x3FFF) << 16)
95#define CP_PACKET2 0x80000000
96#define PACKET2_PAD_SHIFT 0
97#define PACKET2_PAD_MASK (0x3fffffff << 0)
98
99#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
100
101#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
102 (((op) & 0xFF) << 8) | \
103 ((n) & 0x3FFF) << 16)
104
105#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
106
107/* Packet 3 types */
108#define PACKET3_NOP 0x10
109#define PACKET3_SET_BASE 0x11
110#define PACKET3_BASE_INDEX(x) ((x) << 0)
111#define CE_PARTITION_BASE 3
112#define PACKET3_CLEAR_STATE 0x12
113#define PACKET3_INDEX_BUFFER_SIZE 0x13
114#define PACKET3_DISPATCH_DIRECT 0x15
115#define PACKET3_DISPATCH_INDIRECT 0x16
116#define PACKET3_ATOMIC_GDS 0x1D
117#define PACKET3_ATOMIC_MEM 0x1E
118#define PACKET3_OCCLUSION_QUERY 0x1F
119#define PACKET3_SET_PREDICATION 0x20
120#define PACKET3_REG_RMW 0x21
121#define PACKET3_COND_EXEC 0x22
122#define PACKET3_PRED_EXEC 0x23
123#define PACKET3_DRAW_INDIRECT 0x24
124#define PACKET3_DRAW_INDEX_INDIRECT 0x25
125#define PACKET3_INDEX_BASE 0x26
126#define PACKET3_DRAW_INDEX_2 0x27
127#define PACKET3_CONTEXT_CONTROL 0x28
128#define PACKET3_INDEX_TYPE 0x2A
129#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
130#define PACKET3_DRAW_INDEX_AUTO 0x2D
131#define PACKET3_NUM_INSTANCES 0x2F
132#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
133#define PACKET3_INDIRECT_BUFFER_CONST 0x33
134#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
135#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
136#define PACKET3_DRAW_PREAMBLE 0x36
137#define PACKET3_WRITE_DATA 0x37
138#define WRITE_DATA_DST_SEL(x) ((x) << 8)
139 /* 0 - register
140 * 1 - memory (sync - via GRBM)
141 * 2 - gl2
142 * 3 - gds
143 * 4 - reserved
144 * 5 - memory (async - direct)
145 */
146#define WR_ONE_ADDR (1 << 16)
147#define WR_CONFIRM (1 << 20)
148#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
149 /* 0 - LRU
150 * 1 - Stream
151 */
152#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
153 /* 0 - me
154 * 1 - pfp
155 * 2 - ce
156 */
157#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
158#define PACKET3_MEM_SEMAPHORE 0x39
159# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
160# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
161# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
162# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
163# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
164#define PACKET3_WAIT_REG_MEM 0x3C
165#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
166 /* 0 - always
167 * 1 - <
168 * 2 - <=
169 * 3 - ==
170 * 4 - !=
171 * 5 - >=
172 * 6 - >
173 */
174#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
175 /* 0 - reg
176 * 1 - mem
177 */
178#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
179 /* 0 - wait_reg_mem
180 * 1 - wr_wait_wr_reg
181 */
182#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
183 /* 0 - me
184 * 1 - pfp
185 */
186#define PACKET3_INDIRECT_BUFFER 0x3F
187#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
188#define INDIRECT_BUFFER_VALID (1 << 23)
189#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
190 /* 0 - LRU
191 * 1 - Stream
192 * 2 - Bypass
193 */
194#define PACKET3_COPY_DATA 0x40
195#define PACKET3_PFP_SYNC_ME 0x42
196#define PACKET3_SURFACE_SYNC 0x43
197# define PACKET3_DEST_BASE_0_ENA (1 << 0)
198# define PACKET3_DEST_BASE_1_ENA (1 << 1)
199# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
200# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
201# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
202# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
203# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
204# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
205# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
206# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
207# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
208# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
209# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
210# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
211# define PACKET3_DEST_BASE_2_ENA (1 << 19)
212# define PACKET3_DEST_BASE_3_ENA (1 << 21)
213# define PACKET3_TCL1_ACTION_ENA (1 << 22)
214# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
215# define PACKET3_CB_ACTION_ENA (1 << 25)
216# define PACKET3_DB_ACTION_ENA (1 << 26)
217# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
218# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
219# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
220#define PACKET3_COND_WRITE 0x45
221#define PACKET3_EVENT_WRITE 0x46
222#define EVENT_TYPE(x) ((x) << 0)
223#define EVENT_INDEX(x) ((x) << 8)
224 /* 0 - any non-TS event
225 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
226 * 2 - SAMPLE_PIPELINESTAT
227 * 3 - SAMPLE_STREAMOUTSTAT*
228 * 4 - *S_PARTIAL_FLUSH
229 * 5 - EOP events
230 * 6 - EOS events
231 */
232#define PACKET3_EVENT_WRITE_EOP 0x47
233#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
234#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
235#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
236#define EOP_TCL1_ACTION_EN (1 << 16)
237#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
238#define EOP_TCL2_VOLATILE (1 << 24)
239#define EOP_CACHE_POLICY(x) ((x) << 25)
240 /* 0 - LRU
241 * 1 - Stream
242 * 2 - Bypass
243 */
244#define DATA_SEL(x) ((x) << 29)
245 /* 0 - discard
246 * 1 - send low 32bit data
247 * 2 - send 64bit data
248 * 3 - send 64bit GPU counter value
249 * 4 - send 64bit sys counter value
250 */
251#define INT_SEL(x) ((x) << 24)
252 /* 0 - none
253 * 1 - interrupt only (DATA_SEL = 0)
254 * 2 - interrupt when data write is confirmed
255 */
256#define DST_SEL(x) ((x) << 16)
257 /* 0 - MC
258 * 1 - TC/L2
259 */
260#define PACKET3_EVENT_WRITE_EOS 0x48
261#define PACKET3_RELEASE_MEM 0x49
262#define PACKET3_PREAMBLE_CNTL 0x4A
263# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
264# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
265#define PACKET3_DMA_DATA 0x50
266/* 1. header
267 * 2. CONTROL
268 * 3. SRC_ADDR_LO or DATA [31:0]
269 * 4. SRC_ADDR_HI [31:0]
270 * 5. DST_ADDR_LO [31:0]
271 * 6. DST_ADDR_HI [7:0]
272 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
273 */
274/* CONTROL */
275# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
276 /* 0 - ME
277 * 1 - PFP
278 */
279# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
280 /* 0 - LRU
281 * 1 - Stream
282 * 2 - Bypass
283 */
284# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
285# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
286 /* 0 - DST_ADDR using DAS
287 * 1 - GDS
288 * 3 - DST_ADDR using L2
289 */
290# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
291 /* 0 - LRU
292 * 1 - Stream
293 * 2 - Bypass
294 */
295# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
296# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
297 /* 0 - SRC_ADDR using SAS
298 * 1 - GDS
299 * 2 - DATA
300 * 3 - SRC_ADDR using L2
301 */
302# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
303/* COMMAND */
304# define PACKET3_DMA_DATA_DIS_WC (1 << 21)
305# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
306 /* 0 - none
307 * 1 - 8 in 16
308 * 2 - 8 in 32
309 * 3 - 8 in 64
310 */
311# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
312 /* 0 - none
313 * 1 - 8 in 16
314 * 2 - 8 in 32
315 * 3 - 8 in 64
316 */
317# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
318 /* 0 - memory
319 * 1 - register
320 */
321# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
322 /* 0 - memory
323 * 1 - register
324 */
325# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
326# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
327# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
328#define PACKET3_AQUIRE_MEM 0x58
329#define PACKET3_REWIND 0x59
330#define PACKET3_LOAD_UCONFIG_REG 0x5E
331#define PACKET3_LOAD_SH_REG 0x5F
332#define PACKET3_LOAD_CONFIG_REG 0x60
333#define PACKET3_LOAD_CONTEXT_REG 0x61
334#define PACKET3_SET_CONFIG_REG 0x68
335#define PACKET3_SET_CONFIG_REG_START 0x00002000
336#define PACKET3_SET_CONFIG_REG_END 0x00002c00
337#define PACKET3_SET_CONTEXT_REG 0x69
338#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
339#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
340#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
341#define PACKET3_SET_SH_REG 0x76
342#define PACKET3_SET_SH_REG_START 0x00002c00
343#define PACKET3_SET_SH_REG_END 0x00003000
344#define PACKET3_SET_SH_REG_OFFSET 0x77
345#define PACKET3_SET_QUEUE_REG 0x78
346#define PACKET3_SET_UCONFIG_REG 0x79
347#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
348#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
349#define PACKET3_SCRATCH_RAM_WRITE 0x7D
350#define PACKET3_SCRATCH_RAM_READ 0x7E
351#define PACKET3_LOAD_CONST_RAM 0x80
352#define PACKET3_WRITE_CONST_RAM 0x81
353#define PACKET3_DUMP_CONST_RAM 0x83
354#define PACKET3_INCREMENT_CE_COUNTER 0x84
355#define PACKET3_INCREMENT_DE_COUNTER 0x85
356#define PACKET3_WAIT_ON_CE_COUNTER 0x86
357#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
358#define PACKET3_SWITCH_BUFFER 0x8B
359
360#define VCE_CMD_NO_OP 0x00000000
361#define VCE_CMD_END 0x00000001
362#define VCE_CMD_IB 0x00000002
363#define VCE_CMD_FENCE 0x00000003
364#define VCE_CMD_TRAP 0x00000004
365#define VCE_CMD_IB_AUTO 0x00000005
366#define VCE_CMD_SEMAPHORE 0x00000006
367
368#endif