tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/slab.h>
18#include <linux/mfd/syscon.h>
19
20#include "clk-mtk.h"
21#include "clk-gate.h"
22
23#include <dt-bindings/clock/mt8173-clk.h>
24
25static DEFINE_SPINLOCK(mt8173_clk_lock);
26
27static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
28 FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1),
29 FACTOR(CLK_TOP_DPI, "dpi_ck", "clk_null", 1, 1),
30 FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1),
31 FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1),
32};
33
34static const struct mtk_fixed_factor top_divs[] __initconst = {
35 FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
36 FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
37
38 FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
39 FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
40 FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
41 FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
42
43 FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
44 FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
45
46 FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
47 FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
48 FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
49 FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
50 FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
51
52 FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
53 FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
54 FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
55
56 FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
57 FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
58
59 FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
60 FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
61
62 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
63 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
64
65 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
66 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
67 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
68 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
69 FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
70
71 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
72 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
73 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
74
75 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
76 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
77
78 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
79 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
80 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
81 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
82 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
83 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
84
85 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
86 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
87 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
88 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
89 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
90 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
91 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
92 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
93 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
94 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
95 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
96 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
97 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
98 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
99
100 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
101 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
102 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
103 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
104 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
105
106 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
107 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
108 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
109 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
110 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
111 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
112 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
113 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
114 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
115 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
116 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
117 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
118 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
119 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
120 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
121
122 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
123 FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
124
125 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
126 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
127 FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
128};
129
130static const char * const axi_parents[] __initconst = {
131 "clk26m",
132 "syspll1_d2",
133 "syspll_d5",
134 "syspll1_d4",
135 "univpll_d5",
136 "univpll2_d2",
137 "dmpll_d2",
138 "dmpll_d4"
139};
140
141static const char * const mem_parents[] __initconst = {
142 "clk26m",
143 "dmpll_ck"
144};
145
146static const char * const ddrphycfg_parents[] __initconst = {
147 "clk26m",
148 "syspll1_d8"
149};
150
151static const char * const mm_parents[] __initconst = {
152 "clk26m",
153 "vencpll_d2",
154 "main_h364m",
155 "syspll1_d2",
156 "syspll_d5",
157 "syspll1_d4",
158 "univpll1_d2",
159 "univpll2_d2",
160 "dmpll_d2"
161};
162
163static const char * const pwm_parents[] __initconst = {
164 "clk26m",
165 "univpll2_d4",
166 "univpll3_d2",
167 "univpll1_d4"
168};
169
170static const char * const vdec_parents[] __initconst = {
171 "clk26m",
172 "vcodecpll_ck",
173 "tvdpll_445p5m",
174 "univpll_d3",
175 "vencpll_d2",
176 "syspll_d3",
177 "univpll1_d2",
178 "mmpll_d2",
179 "dmpll_d2",
180 "dmpll_d4"
181};
182
183static const char * const venc_parents[] __initconst = {
184 "clk26m",
185 "vcodecpll_ck",
186 "tvdpll_445p5m",
187 "univpll_d3",
188 "vencpll_d2",
189 "syspll_d3",
190 "univpll1_d2",
191 "univpll2_d2",
192 "dmpll_d2",
193 "dmpll_d4"
194};
195
196static const char * const mfg_parents[] __initconst = {
197 "clk26m",
198 "mmpll_ck",
199 "dmpll_ck",
200 "clk26m",
201 "clk26m",
202 "clk26m",
203 "clk26m",
204 "clk26m",
205 "clk26m",
206 "syspll_d3",
207 "syspll1_d2",
208 "syspll_d5",
209 "univpll_d3",
210 "univpll1_d2",
211 "univpll_d5",
212 "univpll2_d2"
213};
214
215static const char * const camtg_parents[] __initconst = {
216 "clk26m",
217 "univpll_d26",
218 "univpll2_d2",
219 "syspll3_d2",
220 "syspll3_d4",
221 "univpll1_d4"
222};
223
224static const char * const uart_parents[] __initconst = {
225 "clk26m",
226 "univpll2_d8"
227};
228
229static const char * const spi_parents[] __initconst = {
230 "clk26m",
231 "syspll3_d2",
232 "syspll1_d4",
233 "syspll4_d2",
234 "univpll3_d2",
235 "univpll2_d4",
236 "univpll1_d8"
237};
238
239static const char * const usb20_parents[] __initconst = {
240 "clk26m",
241 "univpll1_d8",
242 "univpll3_d4"
243};
244
245static const char * const usb30_parents[] __initconst = {
246 "clk26m",
247 "univpll3_d2",
248 "usb_syspll_125m",
249 "univpll2_d4"
250};
251
252static const char * const msdc50_0_h_parents[] __initconst = {
253 "clk26m",
254 "syspll1_d2",
255 "syspll2_d2",
256 "syspll4_d2",
257 "univpll_d5",
258 "univpll1_d4"
259};
260
261static const char * const msdc50_0_parents[] __initconst = {
262 "clk26m",
263 "msdcpll_ck",
264 "msdcpll_d2",
265 "univpll1_d4",
266 "syspll2_d2",
267 "syspll_d7",
268 "msdcpll_d4",
269 "vencpll_d4",
270 "tvdpll_ck",
271 "univpll_d2",
272 "univpll1_d2",
273 "mmpll_ck",
274 "msdcpll2_ck",
275 "msdcpll2_d2",
276 "msdcpll2_d4"
277};
278
279static const char * const msdc30_1_parents[] __initconst = {
280 "clk26m",
281 "univpll2_d2",
282 "msdcpll_d4",
283 "univpll1_d4",
284 "syspll2_d2",
285 "syspll_d7",
286 "univpll_d7",
287 "vencpll_d4"
288};
289
290static const char * const msdc30_2_parents[] __initconst = {
291 "clk26m",
292 "univpll2_d2",
293 "msdcpll_d4",
294 "univpll1_d4",
295 "syspll2_d2",
296 "syspll_d7",
297 "univpll_d7",
298 "vencpll_d2"
299};
300
301static const char * const msdc30_3_parents[] __initconst = {
302 "clk26m",
303 "msdcpll2_ck",
304 "msdcpll2_d2",
305 "univpll2_d2",
306 "msdcpll2_d4",
307 "msdcpll_d4",
308 "univpll1_d4",
309 "syspll2_d2",
310 "syspll_d7",
311 "univpll_d7",
312 "vencpll_d4",
313 "msdcpll_ck",
314 "msdcpll_d2",
315 "msdcpll_d4"
316};
317
318static const char * const audio_parents[] __initconst = {
319 "clk26m",
320 "syspll3_d4",
321 "syspll4_d4",
322 "syspll1_d16"
323};
324
325static const char * const aud_intbus_parents[] __initconst = {
326 "clk26m",
327 "syspll1_d4",
328 "syspll4_d2",
329 "univpll3_d2",
330 "univpll2_d8",
331 "dmpll_d4",
332 "dmpll_d8"
333};
334
335static const char * const pmicspi_parents[] __initconst = {
336 "clk26m",
337 "syspll1_d8",
338 "syspll3_d4",
339 "syspll1_d16",
340 "univpll3_d4",
341 "univpll_d26",
342 "dmpll_d8",
343 "dmpll_d16"
344};
345
346static const char * const scp_parents[] __initconst = {
347 "clk26m",
348 "syspll1_d2",
349 "univpll_d5",
350 "syspll_d5",
351 "dmpll_d2",
352 "dmpll_d4"
353};
354
355static const char * const atb_parents[] __initconst = {
356 "clk26m",
357 "syspll1_d2",
358 "univpll_d5",
359 "dmpll_d2"
360};
361
362static const char * const venc_lt_parents[] __initconst = {
363 "clk26m",
364 "univpll_d3",
365 "vcodecpll_ck",
366 "tvdpll_445p5m",
367 "vencpll_d2",
368 "syspll_d3",
369 "univpll1_d2",
370 "univpll2_d2",
371 "syspll1_d2",
372 "univpll_d5",
373 "vcodecpll_370p5",
374 "dmpll_ck"
375};
376
377static const char * const dpi0_parents[] __initconst = {
378 "clk26m",
379 "tvdpll_d2",
380 "tvdpll_d4",
381 "clk26m",
382 "clk26m",
383 "tvdpll_d8",
384 "tvdpll_d16"
385};
386
387static const char * const irda_parents[] __initconst = {
388 "clk26m",
389 "univpll2_d4",
390 "syspll2_d4"
391};
392
393static const char * const cci400_parents[] __initconst = {
394 "clk26m",
395 "vencpll_ck",
396 "armca7pll_754m",
397 "armca7pll_502m",
398 "univpll_d2",
399 "syspll_d2",
400 "msdcpll_ck",
401 "dmpll_ck"
402};
403
404static const char * const aud_1_parents[] __initconst = {
405 "clk26m",
406 "apll1_ck",
407 "univpll2_d4",
408 "univpll2_d8"
409};
410
411static const char * const aud_2_parents[] __initconst = {
412 "clk26m",
413 "apll2_ck",
414 "univpll2_d4",
415 "univpll2_d8"
416};
417
418static const char * const mem_mfg_in_parents[] __initconst = {
419 "clk26m",
420 "mmpll_ck",
421 "dmpll_ck",
422 "clk26m"
423};
424
425static const char * const axi_mfg_in_parents[] __initconst = {
426 "clk26m",
427 "axi_sel",
428 "dmpll_d2"
429};
430
431static const char * const scam_parents[] __initconst = {
432 "clk26m",
433 "syspll3_d2",
434 "univpll2_d4",
435 "dmpll_d4"
436};
437
438static const char * const spinfi_ifr_parents[] __initconst = {
439 "clk26m",
440 "univpll2_d8",
441 "univpll3_d4",
442 "syspll4_d2",
443 "univpll2_d4",
444 "univpll3_d2",
445 "syspll1_d4",
446 "univpll1_d4"
447};
448
449static const char * const hdmi_parents[] __initconst = {
450 "clk26m",
451 "hdmitx_dig_cts",
452 "hdmitxpll_d2",
453 "hdmitxpll_d3"
454};
455
456static const char * const dpilvds_parents[] __initconst = {
457 "clk26m",
458 "lvdspll",
459 "lvdspll_d2",
460 "lvdspll_d4",
461 "lvdspll_d8",
462 "fpc_ck"
463};
464
465static const char * const msdc50_2_h_parents[] __initconst = {
466 "clk26m",
467 "syspll1_d2",
468 "syspll2_d2",
469 "syspll4_d2",
470 "univpll_d5",
471 "univpll1_d4"
472};
473
474static const char * const hdcp_parents[] __initconst = {
475 "clk26m",
476 "syspll4_d2",
477 "syspll3_d4",
478 "univpll2_d4"
479};
480
481static const char * const hdcp_24m_parents[] __initconst = {
482 "clk26m",
483 "univpll_d26",
484 "univpll_d52",
485 "univpll2_d8"
486};
487
488static const char * const rtc_parents[] __initconst = {
489 "clkrtc_int",
490 "clkrtc_ext",
491 "clk26m",
492 "univpll3_d8"
493};
494
495static const char * const i2s0_m_ck_parents[] __initconst = {
496 "apll1_div1",
497 "apll2_div1"
498};
499
500static const char * const i2s1_m_ck_parents[] __initconst = {
501 "apll1_div2",
502 "apll2_div2"
503};
504
505static const char * const i2s2_m_ck_parents[] __initconst = {
506 "apll1_div3",
507 "apll2_div3"
508};
509
510static const char * const i2s3_m_ck_parents[] __initconst = {
511 "apll1_div4",
512 "apll2_div4"
513};
514
515static const char * const i2s3_b_ck_parents[] __initconst = {
516 "apll1_div5",
517 "apll2_div5"
518};
519
520static const struct mtk_composite top_muxes[] __initconst = {
521 /* CLK_CFG_0 */
522 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
523 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
524 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
525 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
526 /* CLK_CFG_1 */
527 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
528 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
529 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
530 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
531 /* CLK_CFG_2 */
532 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
533 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
534 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
535 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
536 /* CLK_CFG_3 */
537 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
538 MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
539 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
540 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
541 /* CLK_CFG_4 */
542 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
543 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
544 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
545 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
546 /* CLK_CFG_5 */
547 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
548 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
549 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
550 MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
551 /* CLK_CFG_6 */
552 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
553 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
554 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
555 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
556 /* CLK_CFG_7 */
557 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
558 MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
559 MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
560 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
561 /* CLK_CFG_12 */
562 MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
563 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
564 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
565 /* CLK_CFG_13 */
566 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
567 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
568 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
569 MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
570
571 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
572 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
573 DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
574 DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
575 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
576 DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
577
578 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
579 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
580 DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
581 DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
582 DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
583 DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
584
585 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
586 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
587 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
588 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
589 MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
590};
591
592static const struct mtk_gate_regs infra_cg_regs = {
593 .set_ofs = 0x0040,
594 .clr_ofs = 0x0044,
595 .sta_ofs = 0x0048,
596};
597
598#define GATE_ICG(_id, _name, _parent, _shift) { \
599 .id = _id, \
600 .name = _name, \
601 .parent_name = _parent, \
602 .regs = &infra_cg_regs, \
603 .shift = _shift, \
604 .ops = &mtk_clk_gate_ops_setclr, \
605 }
606
607static const struct mtk_gate infra_clks[] __initconst = {
608 GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
609 GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
610 GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
611 GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
612 GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
613 GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
614 GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "clk_null", 15),
615 GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
616 GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
617 GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
618 GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
619};
620
621static const struct mtk_gate_regs peri0_cg_regs = {
622 .set_ofs = 0x0008,
623 .clr_ofs = 0x0010,
624 .sta_ofs = 0x0018,
625};
626
627static const struct mtk_gate_regs peri1_cg_regs = {
628 .set_ofs = 0x000c,
629 .clr_ofs = 0x0014,
630 .sta_ofs = 0x001c,
631};
632
633#define GATE_PERI0(_id, _name, _parent, _shift) { \
634 .id = _id, \
635 .name = _name, \
636 .parent_name = _parent, \
637 .regs = &peri0_cg_regs, \
638 .shift = _shift, \
639 .ops = &mtk_clk_gate_ops_setclr, \
640 }
641
642#define GATE_PERI1(_id, _name, _parent, _shift) { \
643 .id = _id, \
644 .name = _name, \
645 .parent_name = _parent, \
646 .regs = &peri1_cg_regs, \
647 .shift = _shift, \
648 .ops = &mtk_clk_gate_ops_setclr, \
649 }
650
651static const struct mtk_gate peri_gates[] __initconst = {
652 /* PERI0 */
653 GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
654 GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
655 GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
656 GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
657 GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
658 GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
659 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
660 GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
661 GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
662 GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
663 GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
664 GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
665 GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
666 GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
667 GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
668 GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
669 GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
670 GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
671 GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
672 GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
673 GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
674 GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
675 GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
676 GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
677 GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
678 GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
679 GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
680 GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
681 GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
682 GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
683 GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
684 GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
685 /* PERI1 */
686 GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
687 GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
688 GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
689};
690
691static const char * const uart_ck_sel_parents[] __initconst = {
692 "clk26m",
693 "uart_sel",
694};
695
696static const struct mtk_composite peri_clks[] __initconst = {
697 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
698 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
699 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
700 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
701};
702
703static struct clk_onecell_data *mt8173_top_clk_data __initdata;
704static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
705
706static void __init mtk_clk_enable_critical(void)
707{
708 if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
709 return;
710
711 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
712 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
713 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
714 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
715 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
716 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
717}
718
719static void __init mtk_topckgen_init(struct device_node *node)
720{
721 struct clk_onecell_data *clk_data;
722 void __iomem *base;
723 int r;
724
725 base = of_iomap(node, 0);
726 if (!base) {
727 pr_err("%s(): ioremap failed\n", __func__);
728 return;
729 }
730
731 mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
732
733 mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
734 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
735 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
736 &mt8173_clk_lock, clk_data);
737
738 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
739 if (r)
740 pr_err("%s(): could not register clock provider: %d\n",
741 __func__, r);
742
743 mtk_clk_enable_critical();
744}
745CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
746
747static void __init mtk_infrasys_init(struct device_node *node)
748{
749 struct clk_onecell_data *clk_data;
750 int r;
751
752 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
753
754 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
755 clk_data);
756
757 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
758 if (r)
759 pr_err("%s(): could not register clock provider: %d\n",
760 __func__, r);
761
762 mtk_register_reset_controller(node, 2, 0x30);
763}
764CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
765
766static void __init mtk_pericfg_init(struct device_node *node)
767{
768 struct clk_onecell_data *clk_data;
769 int r;
770 void __iomem *base;
771
772 base = of_iomap(node, 0);
773 if (!base) {
774 pr_err("%s(): ioremap failed\n", __func__);
775 return;
776 }
777
778 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
779
780 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
781 clk_data);
782 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
783 &mt8173_clk_lock, clk_data);
784
785 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
786 if (r)
787 pr_err("%s(): could not register clock provider: %d\n",
788 __func__, r);
789
790 mtk_register_reset_controller(node, 2, 0);
791}
792CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
793
794#define MT8173_PLL_FMAX (3000UL * MHZ)
795
796#define CON0_MT8173_RST_BAR BIT(24)
797
798#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, \
799 _tuner_reg, _pcw_reg, _pcw_shift) { \
800 .id = _id, \
801 .name = _name, \
802 .reg = _reg, \
803 .pwr_reg = _pwr_reg, \
804 .en_mask = _en_mask, \
805 .flags = _flags, \
806 .rst_bar_mask = CON0_MT8173_RST_BAR, \
807 .fmax = MT8173_PLL_FMAX, \
808 .pcwbits = _pcwbits, \
809 .pd_reg = _pd_reg, \
810 .pd_shift = _pd_shift, \
811 .tuner_reg = _tuner_reg, \
812 .pcw_reg = _pcw_reg, \
813 .pcw_shift = _pcw_shift, \
814 }
815
816static const struct mtk_pll_data plls[] = {
817 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
818 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
819 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
820 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
821 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0),
822 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
823 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
824 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
825 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
826 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
827 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
828 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
829 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
830 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
831};
832
833static void __init mtk_apmixedsys_init(struct device_node *node)
834{
835 struct clk_onecell_data *clk_data;
836
837 mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
838 if (!clk_data)
839 return;
840
841 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
842
843 mtk_clk_enable_critical();
844}
845CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
846 mtk_apmixedsys_init);