tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * bits.h - register bits of the ChipIdea USB IP core
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
14#define __DRIVERS_USB_CHIPIDEA_BITS_H
15
16#include <linux/usb/ehci_def.h>
17
18/*
19 * ID
20 * For 1.x revision, bit24 - bit31 are reserved
21 * For 2.x revision, bit25 - bit28 are 0x2
22 */
23#define TAG (0x1F << 16)
24#define REVISION (0xF << 21)
25#define VERSION (0xF << 25)
26#define CIVERSION (0x7 << 29)
27
28/* HCCPARAMS */
29#define HCCPARAMS_LEN BIT(17)
30
31/* DCCPARAMS */
32#define DCCPARAMS_DEN (0x1F << 0)
33#define DCCPARAMS_DC BIT(7)
34#define DCCPARAMS_HC BIT(8)
35
36/* TESTMODE */
37#define TESTMODE_FORCE BIT(0)
38
39/* USBCMD */
40#define USBCMD_RS BIT(0)
41#define USBCMD_RST BIT(1)
42#define USBCMD_SUTW BIT(13)
43#define USBCMD_ATDTW BIT(14)
44
45/* USBSTS & USBINTR */
46#define USBi_UI BIT(0)
47#define USBi_UEI BIT(1)
48#define USBi_PCI BIT(2)
49#define USBi_URI BIT(6)
50#define USBi_SLI BIT(8)
51
52/* DEVICEADDR */
53#define DEVICEADDR_USBADRA BIT(24)
54#define DEVICEADDR_USBADR (0x7FUL << 25)
55
56/* PORTSC */
57#define PORTSC_CCS BIT(0)
58#define PORTSC_CSC BIT(1)
59#define PORTSC_PEC BIT(3)
60#define PORTSC_OCC BIT(5)
61#define PORTSC_FPR BIT(6)
62#define PORTSC_SUSP BIT(7)
63#define PORTSC_HSP BIT(9)
64#define PORTSC_PP BIT(12)
65#define PORTSC_PTC (0x0FUL << 16)
66#define PORTSC_WKCN BIT(20)
67#define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23))
68/* PTS and PTW for non lpm version only */
69#define PORTSC_PFSC BIT(24)
70#define PORTSC_PTS(d) \
71 (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
72#define PORTSC_PTW BIT(28)
73#define PORTSC_STS BIT(29)
74
75#define PORTSC_W1C_BITS \
76 (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
77
78/* DEVLC */
79#define DEVLC_PFSC BIT(23)
80#define DEVLC_PSPD (0x03UL << 25)
81#define DEVLC_PSPD_HS (0x02UL << 25)
82#define DEVLC_PTW BIT(27)
83#define DEVLC_STS BIT(28)
84#define DEVLC_PTS(d) (u32)(((d) & 0x7) << 29)
85
86/* Encoding for DEVLC_PTS and PORTSC_PTS */
87#define PTS_UTMI 0
88#define PTS_ULPI 2
89#define PTS_SERIAL 3
90#define PTS_HSIC 4
91
92/* OTGSC */
93#define OTGSC_IDPU BIT(5)
94#define OTGSC_HADP BIT(6)
95#define OTGSC_HABA BIT(7)
96#define OTGSC_ID BIT(8)
97#define OTGSC_AVV BIT(9)
98#define OTGSC_ASV BIT(10)
99#define OTGSC_BSV BIT(11)
100#define OTGSC_BSE BIT(12)
101#define OTGSC_IDIS BIT(16)
102#define OTGSC_AVVIS BIT(17)
103#define OTGSC_ASVIS BIT(18)
104#define OTGSC_BSVIS BIT(19)
105#define OTGSC_BSEIS BIT(20)
106#define OTGSC_1MSIS BIT(21)
107#define OTGSC_DPIS BIT(22)
108#define OTGSC_IDIE BIT(24)
109#define OTGSC_AVVIE BIT(25)
110#define OTGSC_ASVIE BIT(26)
111#define OTGSC_BSVIE BIT(27)
112#define OTGSC_BSEIE BIT(28)
113#define OTGSC_1MSIE BIT(29)
114#define OTGSC_DPIE BIT(30)
115#define OTGSC_INT_EN_BITS (OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \
116 | OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \
117 | OTGSC_DPIE)
118#define OTGSC_INT_STATUS_BITS (OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS \
119 | OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \
120 | OTGSC_DPIS)
121
122/* USBMODE */
123#define USBMODE_CM (0x03UL << 0)
124#define USBMODE_CM_DC (0x02UL << 0)
125#define USBMODE_SLOM BIT(3)
126#define USBMODE_CI_SDIS BIT(4)
127
128/* ENDPTCTRL */
129#define ENDPTCTRL_RXS BIT(0)
130#define ENDPTCTRL_RXT (0x03UL << 2)
131#define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
132#define ENDPTCTRL_RXE BIT(7)
133#define ENDPTCTRL_TXS BIT(16)
134#define ENDPTCTRL_TXT (0x03UL << 18)
135#define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
136#define ENDPTCTRL_TXE BIT(23)
137
138#endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */