tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/random.h>
17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
21#include "farch_regs.h"
22#include "io.h"
23#include "phy.h"
24#include "workarounds.h"
25#include "mcdi.h"
26#include "mcdi_pcol.h"
27#include "selftest.h"
28#include "siena_sriov.h"
29
30/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32static void siena_init_wol(struct efx_nic *efx);
33
34
35static void siena_push_irq_moderation(struct efx_channel *channel)
36{
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52}
53
54void siena_prepare_flush(struct efx_nic *efx)
55{
56 if (efx->fc_disable++ == 0)
57 efx_mcdi_set_mac(efx);
58}
59
60void siena_finish_flush(struct efx_nic *efx)
61{
62 if (--efx->fc_disable == 0)
63 efx_mcdi_set_mac(efx);
64}
65
66static const struct efx_farch_register_test siena_register_tests[] = {
67 { FR_AZ_ADR_REGION,
68 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
69 { FR_CZ_USR_EV_CFG,
70 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
71 { FR_AZ_RX_CFG,
72 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
73 { FR_AZ_TX_CFG,
74 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
75 { FR_AZ_TX_RESERVED,
76 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
77 { FR_AZ_SRM_TX_DC_CFG,
78 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
79 { FR_AZ_RX_DC_CFG,
80 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
81 { FR_AZ_RX_DC_PF_WM,
82 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
83 { FR_BZ_DP_CTRL,
84 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
85 { FR_BZ_RX_RSS_TKEY,
86 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
87 { FR_CZ_RX_RSS_IPV6_REG1,
88 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
89 { FR_CZ_RX_RSS_IPV6_REG2,
90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
91 { FR_CZ_RX_RSS_IPV6_REG3,
92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
93};
94
95static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
96{
97 enum reset_type reset_method = RESET_TYPE_ALL;
98 int rc, rc2;
99
100 efx_reset_down(efx, reset_method);
101
102 /* Reset the chip immediately so that it is completely
103 * quiescent regardless of what any VF driver does.
104 */
105 rc = efx_mcdi_reset(efx, reset_method);
106 if (rc)
107 goto out;
108
109 tests->registers =
110 efx_farch_test_registers(efx, siena_register_tests,
111 ARRAY_SIZE(siena_register_tests))
112 ? -1 : 1;
113
114 rc = efx_mcdi_reset(efx, reset_method);
115out:
116 rc2 = efx_reset_up(efx, reset_method, rc == 0);
117 return rc ? rc : rc2;
118}
119
120/**************************************************************************
121 *
122 * PTP
123 *
124 **************************************************************************
125 */
126
127static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
128{
129 _efx_writed(efx, cpu_to_le32(host_time),
130 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
131}
132
133static int siena_ptp_set_ts_config(struct efx_nic *efx,
134 struct hwtstamp_config *init)
135{
136 int rc;
137
138 switch (init->rx_filter) {
139 case HWTSTAMP_FILTER_NONE:
140 /* if TX timestamping is still requested then leave PTP on */
141 return efx_ptp_change_mode(efx,
142 init->tx_type != HWTSTAMP_TX_OFF,
143 efx_ptp_get_mode(efx));
144 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
145 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
146 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
147 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
148 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
149 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
150 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
151 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
152 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
153 rc = efx_ptp_change_mode(efx, true,
154 MC_CMD_PTP_MODE_V2_ENHANCED);
155 /* bug 33070 - old versions of the firmware do not support the
156 * improved UUID filtering option. Similarly old versions of the
157 * application do not expect it to be enabled. If the firmware
158 * does not accept the enhanced mode, fall back to the standard
159 * PTP v2 UUID filtering. */
160 if (rc != 0)
161 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
162 return rc;
163 default:
164 return -ERANGE;
165 }
166}
167
168/**************************************************************************
169 *
170 * Device reset
171 *
172 **************************************************************************
173 */
174
175static int siena_map_reset_flags(u32 *flags)
176{
177 enum {
178 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
179 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
180 ETH_RESET_PHY),
181 SIENA_RESET_MC = (SIENA_RESET_PORT |
182 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
183 };
184
185 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
186 *flags &= ~SIENA_RESET_MC;
187 return RESET_TYPE_WORLD;
188 }
189
190 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
191 *flags &= ~SIENA_RESET_PORT;
192 return RESET_TYPE_ALL;
193 }
194
195 /* no invisible reset implemented */
196
197 return -EINVAL;
198}
199
200#ifdef CONFIG_EEH
201/* When a PCI device is isolated from the bus, a subsequent MMIO read is
202 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
203 * was written to minimise MMIO read (for latency) then a periodic call to check
204 * the EEH status of the device is required so that device recovery can happen
205 * in a timely fashion.
206 */
207static void siena_monitor(struct efx_nic *efx)
208{
209 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
210
211 eeh_dev_check_failure(eehdev);
212}
213#endif
214
215static int siena_probe_nvconfig(struct efx_nic *efx)
216{
217 u32 caps = 0;
218 int rc;
219
220 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
221
222 efx->timer_quantum_ns =
223 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
224 3072 : 6144; /* 768 cycles */
225 return rc;
226}
227
228static int siena_dimension_resources(struct efx_nic *efx)
229{
230 /* Each port has a small block of internal SRAM dedicated to
231 * the buffer table and descriptor caches. In theory we can
232 * map both blocks to one port, but we don't.
233 */
234 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
235 return 0;
236}
237
238static unsigned int siena_mem_map_size(struct efx_nic *efx)
239{
240 return FR_CZ_MC_TREG_SMEM +
241 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
242}
243
244static int siena_probe_nic(struct efx_nic *efx)
245{
246 struct siena_nic_data *nic_data;
247 efx_oword_t reg;
248 int rc;
249
250 /* Allocate storage for hardware specific data */
251 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
252 if (!nic_data)
253 return -ENOMEM;
254 nic_data->efx = efx;
255 efx->nic_data = nic_data;
256
257 if (efx_farch_fpga_ver(efx) != 0) {
258 netif_err(efx, probe, efx->net_dev,
259 "Siena FPGA not supported\n");
260 rc = -ENODEV;
261 goto fail1;
262 }
263
264 efx->max_channels = EFX_MAX_CHANNELS;
265
266 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
267 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
268
269 rc = efx_mcdi_init(efx);
270 if (rc)
271 goto fail1;
272
273 /* Now we can reset the NIC */
274 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
275 if (rc) {
276 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
277 goto fail3;
278 }
279
280 siena_init_wol(efx);
281
282 /* Allocate memory for INT_KER */
283 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
284 GFP_KERNEL);
285 if (rc)
286 goto fail4;
287 BUG_ON(efx->irq_status.dma_addr & 0x0f);
288
289 netif_dbg(efx, probe, efx->net_dev,
290 "INT_KER at %llx (virt %p phys %llx)\n",
291 (unsigned long long)efx->irq_status.dma_addr,
292 efx->irq_status.addr,
293 (unsigned long long)virt_to_phys(efx->irq_status.addr));
294
295 /* Read in the non-volatile configuration */
296 rc = siena_probe_nvconfig(efx);
297 if (rc == -EINVAL) {
298 netif_err(efx, probe, efx->net_dev,
299 "NVRAM is invalid therefore using defaults\n");
300 efx->phy_type = PHY_TYPE_NONE;
301 efx->mdio.prtad = MDIO_PRTAD_NONE;
302 } else if (rc) {
303 goto fail5;
304 }
305
306 rc = efx_mcdi_mon_probe(efx);
307 if (rc)
308 goto fail5;
309
310#ifdef CONFIG_SFC_SRIOV
311 efx_siena_sriov_probe(efx);
312#endif
313 efx_ptp_defer_probe_with_channel(efx);
314
315 return 0;
316
317fail5:
318 efx_nic_free_buffer(efx, &efx->irq_status);
319fail4:
320fail3:
321 efx_mcdi_fini(efx);
322fail1:
323 kfree(efx->nic_data);
324 return rc;
325}
326
327static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
328 const u32 *rx_indir_table)
329{
330 efx_oword_t temp;
331
332 /* Set hash key for IPv4 */
333 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
334 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
335
336 /* Enable IPv6 RSS */
337 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
338 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
339 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
340 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
341 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
342 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
343 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
344 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
345 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
346 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
347 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
348 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
349
350 memcpy(efx->rx_indir_table, rx_indir_table,
351 sizeof(efx->rx_indir_table));
352 efx_farch_rx_push_indir_table(efx);
353
354 return 0;
355}
356
357/* This call performs hardware-specific global initialisation, such as
358 * defining the descriptor cache sizes and number of RSS channels.
359 * It does not set up any buffers, descriptor rings or event queues.
360 */
361static int siena_init_nic(struct efx_nic *efx)
362{
363 efx_oword_t temp;
364 int rc;
365
366 /* Recover from a failed assertion post-reset */
367 rc = efx_mcdi_handle_assertion(efx);
368 if (rc)
369 return rc;
370
371 /* Squash TX of packets of 16 bytes or less */
372 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
373 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
374 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
375
376 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
377 * descriptors (which is bad).
378 */
379 efx_reado(efx, &temp, FR_AZ_TX_CFG);
380 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
381 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
382 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
383
384 efx_reado(efx, &temp, FR_AZ_RX_CFG);
385 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
386 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
387 /* Enable hash insertion. This is broken for the 'Falcon' hash
388 * if IPv6 hashing is also enabled, so also select Toeplitz
389 * TCP/IPv4 and IPv4 hashes. */
390 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
391 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
392 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
393 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
394 EFX_RX_USR_BUF_SIZE >> 5);
395 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
396
397 siena_rx_push_rss_config(efx, false, efx->rx_indir_table);
398
399 /* Enable event logging */
400 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
401 if (rc)
402 return rc;
403
404 /* Set destination of both TX and RX Flush events */
405 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
406 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
407
408 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
409 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
410
411 efx_farch_init_common(efx);
412 return 0;
413}
414
415static void siena_remove_nic(struct efx_nic *efx)
416{
417 efx_mcdi_mon_remove(efx);
418
419 efx_nic_free_buffer(efx, &efx->irq_status);
420
421 efx_mcdi_reset(efx, RESET_TYPE_ALL);
422
423 efx_mcdi_fini(efx);
424
425 /* Tear down the private nic state */
426 kfree(efx->nic_data);
427 efx->nic_data = NULL;
428}
429
430#define SIENA_DMA_STAT(ext_name, mcdi_name) \
431 [SIENA_STAT_ ## ext_name] = \
432 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
433#define SIENA_OTHER_STAT(ext_name) \
434 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
435#define GENERIC_SW_STAT(ext_name) \
436 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
437
438static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
439 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
440 SIENA_OTHER_STAT(tx_good_bytes),
441 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
442 SIENA_DMA_STAT(tx_packets, TX_PKTS),
443 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
444 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
445 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
446 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
447 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
448 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
449 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
450 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
451 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
452 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
453 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
454 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
455 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
456 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
457 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
458 SIENA_OTHER_STAT(tx_collision),
459 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
460 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
461 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
462 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
463 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
464 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
465 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
466 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
467 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
468 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
469 SIENA_OTHER_STAT(rx_good_bytes),
470 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
471 SIENA_DMA_STAT(rx_packets, RX_PKTS),
472 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
473 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
474 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
475 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
476 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
477 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
478 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
479 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
480 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
481 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
482 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
483 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
484 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
485 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
486 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
487 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
488 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
489 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
490 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
491 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
492 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
493 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
494 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
495 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
496 GENERIC_SW_STAT(rx_nodesc_trunc),
497 GENERIC_SW_STAT(rx_noskb_drops),
498};
499static const unsigned long siena_stat_mask[] = {
500 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
501};
502
503static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
504{
505 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
506 siena_stat_mask, names);
507}
508
509static int siena_try_update_nic_stats(struct efx_nic *efx)
510{
511 struct siena_nic_data *nic_data = efx->nic_data;
512 u64 *stats = nic_data->stats;
513 __le64 *dma_stats;
514 __le64 generation_start, generation_end;
515
516 dma_stats = efx->stats_buffer.addr;
517
518 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
519 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
520 return 0;
521 rmb();
522 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
523 stats, efx->stats_buffer.addr, false);
524 rmb();
525 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
526 if (generation_end != generation_start)
527 return -EAGAIN;
528
529 /* Update derived statistics */
530 efx_nic_fix_nodesc_drop_stat(efx,
531 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
532 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
533 stats[SIENA_STAT_tx_bytes] -
534 stats[SIENA_STAT_tx_bad_bytes]);
535 stats[SIENA_STAT_tx_collision] =
536 stats[SIENA_STAT_tx_single_collision] +
537 stats[SIENA_STAT_tx_multiple_collision] +
538 stats[SIENA_STAT_tx_excessive_collision] +
539 stats[SIENA_STAT_tx_late_collision];
540 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
541 stats[SIENA_STAT_rx_bytes] -
542 stats[SIENA_STAT_rx_bad_bytes]);
543 efx_update_sw_stats(efx, stats);
544 return 0;
545}
546
547static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
548 struct rtnl_link_stats64 *core_stats)
549{
550 struct siena_nic_data *nic_data = efx->nic_data;
551 u64 *stats = nic_data->stats;
552 int retry;
553
554 /* If we're unlucky enough to read statistics wduring the DMA, wait
555 * up to 10ms for it to finish (typically takes <500us) */
556 for (retry = 0; retry < 100; ++retry) {
557 if (siena_try_update_nic_stats(efx) == 0)
558 break;
559 udelay(100);
560 }
561
562 if (full_stats)
563 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
564
565 if (core_stats) {
566 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
567 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
568 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
569 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
570 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
571 stats[GENERIC_STAT_rx_nodesc_trunc] +
572 stats[GENERIC_STAT_rx_noskb_drops];
573 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
574 core_stats->collisions = stats[SIENA_STAT_tx_collision];
575 core_stats->rx_length_errors =
576 stats[SIENA_STAT_rx_gtjumbo] +
577 stats[SIENA_STAT_rx_length_error];
578 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
579 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
580 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
581 core_stats->tx_window_errors =
582 stats[SIENA_STAT_tx_late_collision];
583
584 core_stats->rx_errors = (core_stats->rx_length_errors +
585 core_stats->rx_crc_errors +
586 core_stats->rx_frame_errors +
587 stats[SIENA_STAT_rx_symbol_error]);
588 core_stats->tx_errors = (core_stats->tx_window_errors +
589 stats[SIENA_STAT_tx_bad]);
590 }
591
592 return SIENA_STAT_COUNT;
593}
594
595static int siena_mac_reconfigure(struct efx_nic *efx)
596{
597 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
598 int rc;
599
600 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
601 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
602 sizeof(efx->multicast_hash));
603
604 efx_farch_filter_sync_rx_mode(efx);
605
606 WARN_ON(!mutex_is_locked(&efx->mac_lock));
607
608 rc = efx_mcdi_set_mac(efx);
609 if (rc != 0)
610 return rc;
611
612 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
613 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
614 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
615 inbuf, sizeof(inbuf), NULL, 0, NULL);
616}
617
618/**************************************************************************
619 *
620 * Wake on LAN
621 *
622 **************************************************************************
623 */
624
625static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
626{
627 struct siena_nic_data *nic_data = efx->nic_data;
628
629 wol->supported = WAKE_MAGIC;
630 if (nic_data->wol_filter_id != -1)
631 wol->wolopts = WAKE_MAGIC;
632 else
633 wol->wolopts = 0;
634 memset(&wol->sopass, 0, sizeof(wol->sopass));
635}
636
637
638static int siena_set_wol(struct efx_nic *efx, u32 type)
639{
640 struct siena_nic_data *nic_data = efx->nic_data;
641 int rc;
642
643 if (type & ~WAKE_MAGIC)
644 return -EINVAL;
645
646 if (type & WAKE_MAGIC) {
647 if (nic_data->wol_filter_id != -1)
648 efx_mcdi_wol_filter_remove(efx,
649 nic_data->wol_filter_id);
650 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
651 &nic_data->wol_filter_id);
652 if (rc)
653 goto fail;
654
655 pci_wake_from_d3(efx->pci_dev, true);
656 } else {
657 rc = efx_mcdi_wol_filter_reset(efx);
658 nic_data->wol_filter_id = -1;
659 pci_wake_from_d3(efx->pci_dev, false);
660 if (rc)
661 goto fail;
662 }
663
664 return 0;
665 fail:
666 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
667 __func__, type, rc);
668 return rc;
669}
670
671
672static void siena_init_wol(struct efx_nic *efx)
673{
674 struct siena_nic_data *nic_data = efx->nic_data;
675 int rc;
676
677 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
678
679 if (rc != 0) {
680 /* If it failed, attempt to get into a synchronised
681 * state with MC by resetting any set WoL filters */
682 efx_mcdi_wol_filter_reset(efx);
683 nic_data->wol_filter_id = -1;
684 } else if (nic_data->wol_filter_id != -1) {
685 pci_wake_from_d3(efx->pci_dev, true);
686 }
687}
688
689/**************************************************************************
690 *
691 * MCDI
692 *
693 **************************************************************************
694 */
695
696#define MCDI_PDU(efx) \
697 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
698#define MCDI_DOORBELL(efx) \
699 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
700#define MCDI_STATUS(efx) \
701 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
702
703static void siena_mcdi_request(struct efx_nic *efx,
704 const efx_dword_t *hdr, size_t hdr_len,
705 const efx_dword_t *sdu, size_t sdu_len)
706{
707 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
708 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
709 unsigned int i;
710 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
711
712 EFX_BUG_ON_PARANOID(hdr_len != 4);
713
714 efx_writed(efx, hdr, pdu);
715
716 for (i = 0; i < inlen_dw; i++)
717 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
718
719 /* Ensure the request is written out before the doorbell */
720 wmb();
721
722 /* ring the doorbell with a distinctive value */
723 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
724}
725
726static bool siena_mcdi_poll_response(struct efx_nic *efx)
727{
728 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
729 efx_dword_t hdr;
730
731 efx_readd(efx, &hdr, pdu);
732
733 /* All 1's indicates that shared memory is in reset (and is
734 * not a valid hdr). Wait for it to come out reset before
735 * completing the command
736 */
737 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
738 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
739}
740
741static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
742 size_t offset, size_t outlen)
743{
744 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
745 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
746 int i;
747
748 for (i = 0; i < outlen_dw; i++)
749 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
750}
751
752static int siena_mcdi_poll_reboot(struct efx_nic *efx)
753{
754 struct siena_nic_data *nic_data = efx->nic_data;
755 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
756 efx_dword_t reg;
757 u32 value;
758
759 efx_readd(efx, ®, addr);
760 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
761
762 if (value == 0)
763 return 0;
764
765 EFX_ZERO_DWORD(reg);
766 efx_writed(efx, ®, addr);
767
768 /* MAC statistics have been cleared on the NIC; clear the local
769 * copies that we update with efx_update_diff_stat().
770 */
771 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
772 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
773
774 if (value == MC_STATUS_DWORD_ASSERT)
775 return -EINTR;
776 else
777 return -EIO;
778}
779
780/**************************************************************************
781 *
782 * MTD
783 *
784 **************************************************************************
785 */
786
787#ifdef CONFIG_SFC_MTD
788
789struct siena_nvram_type_info {
790 int port;
791 const char *name;
792};
793
794static const struct siena_nvram_type_info siena_nvram_types[] = {
795 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
796 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
797 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
798 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
799 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
800 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
801 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
802 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
803 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
804 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
805 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
806 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
807 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
808};
809
810static int siena_mtd_probe_partition(struct efx_nic *efx,
811 struct efx_mcdi_mtd_partition *part,
812 unsigned int type)
813{
814 const struct siena_nvram_type_info *info;
815 size_t size, erase_size;
816 bool protected;
817 int rc;
818
819 if (type >= ARRAY_SIZE(siena_nvram_types) ||
820 siena_nvram_types[type].name == NULL)
821 return -ENODEV;
822
823 info = &siena_nvram_types[type];
824
825 if (info->port != efx_port_num(efx))
826 return -ENODEV;
827
828 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
829 if (rc)
830 return rc;
831 if (protected)
832 return -ENODEV; /* hide it */
833
834 part->nvram_type = type;
835 part->common.dev_type_name = "Siena NVRAM manager";
836 part->common.type_name = info->name;
837
838 part->common.mtd.type = MTD_NORFLASH;
839 part->common.mtd.flags = MTD_CAP_NORFLASH;
840 part->common.mtd.size = size;
841 part->common.mtd.erasesize = erase_size;
842
843 return 0;
844}
845
846static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
847 struct efx_mcdi_mtd_partition *parts,
848 size_t n_parts)
849{
850 uint16_t fw_subtype_list[
851 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
852 size_t i;
853 int rc;
854
855 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
856 if (rc)
857 return rc;
858
859 for (i = 0; i < n_parts; i++)
860 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
861
862 return 0;
863}
864
865static int siena_mtd_probe(struct efx_nic *efx)
866{
867 struct efx_mcdi_mtd_partition *parts;
868 u32 nvram_types;
869 unsigned int type;
870 size_t n_parts;
871 int rc;
872
873 ASSERT_RTNL();
874
875 rc = efx_mcdi_nvram_types(efx, &nvram_types);
876 if (rc)
877 return rc;
878
879 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
880 if (!parts)
881 return -ENOMEM;
882
883 type = 0;
884 n_parts = 0;
885
886 while (nvram_types != 0) {
887 if (nvram_types & 1) {
888 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
889 type);
890 if (rc == 0)
891 n_parts++;
892 else if (rc != -ENODEV)
893 goto fail;
894 }
895 type++;
896 nvram_types >>= 1;
897 }
898
899 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
900 if (rc)
901 goto fail;
902
903 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
904fail:
905 if (rc)
906 kfree(parts);
907 return rc;
908}
909
910#endif /* CONFIG_SFC_MTD */
911
912/**************************************************************************
913 *
914 * Revision-dependent attributes used by efx.c and nic.c
915 *
916 **************************************************************************
917 */
918
919const struct efx_nic_type siena_a0_nic_type = {
920 .is_vf = false,
921 .mem_bar = EFX_MEM_BAR,
922 .mem_map_size = siena_mem_map_size,
923 .probe = siena_probe_nic,
924 .remove = siena_remove_nic,
925 .init = siena_init_nic,
926 .dimension_resources = siena_dimension_resources,
927 .fini = efx_port_dummy_op_void,
928#ifdef CONFIG_EEH
929 .monitor = siena_monitor,
930#else
931 .monitor = NULL,
932#endif
933 .map_reset_reason = efx_mcdi_map_reset_reason,
934 .map_reset_flags = siena_map_reset_flags,
935 .reset = efx_mcdi_reset,
936 .probe_port = efx_mcdi_port_probe,
937 .remove_port = efx_mcdi_port_remove,
938 .fini_dmaq = efx_farch_fini_dmaq,
939 .prepare_flush = siena_prepare_flush,
940 .finish_flush = siena_finish_flush,
941 .prepare_flr = efx_port_dummy_op_void,
942 .finish_flr = efx_farch_finish_flr,
943 .describe_stats = siena_describe_nic_stats,
944 .update_stats = siena_update_nic_stats,
945 .start_stats = efx_mcdi_mac_start_stats,
946 .pull_stats = efx_mcdi_mac_pull_stats,
947 .stop_stats = efx_mcdi_mac_stop_stats,
948 .set_id_led = efx_mcdi_set_id_led,
949 .push_irq_moderation = siena_push_irq_moderation,
950 .reconfigure_mac = siena_mac_reconfigure,
951 .check_mac_fault = efx_mcdi_mac_check_fault,
952 .reconfigure_port = efx_mcdi_port_reconfigure,
953 .get_wol = siena_get_wol,
954 .set_wol = siena_set_wol,
955 .resume_wol = siena_init_wol,
956 .test_chip = siena_test_chip,
957 .test_nvram = efx_mcdi_nvram_test_all,
958 .mcdi_request = siena_mcdi_request,
959 .mcdi_poll_response = siena_mcdi_poll_response,
960 .mcdi_read_response = siena_mcdi_read_response,
961 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
962 .irq_enable_master = efx_farch_irq_enable_master,
963 .irq_test_generate = efx_farch_irq_test_generate,
964 .irq_disable_non_ev = efx_farch_irq_disable_master,
965 .irq_handle_msi = efx_farch_msi_interrupt,
966 .irq_handle_legacy = efx_farch_legacy_interrupt,
967 .tx_probe = efx_farch_tx_probe,
968 .tx_init = efx_farch_tx_init,
969 .tx_remove = efx_farch_tx_remove,
970 .tx_write = efx_farch_tx_write,
971 .rx_push_rss_config = siena_rx_push_rss_config,
972 .rx_probe = efx_farch_rx_probe,
973 .rx_init = efx_farch_rx_init,
974 .rx_remove = efx_farch_rx_remove,
975 .rx_write = efx_farch_rx_write,
976 .rx_defer_refill = efx_farch_rx_defer_refill,
977 .ev_probe = efx_farch_ev_probe,
978 .ev_init = efx_farch_ev_init,
979 .ev_fini = efx_farch_ev_fini,
980 .ev_remove = efx_farch_ev_remove,
981 .ev_process = efx_farch_ev_process,
982 .ev_read_ack = efx_farch_ev_read_ack,
983 .ev_test_generate = efx_farch_ev_test_generate,
984 .filter_table_probe = efx_farch_filter_table_probe,
985 .filter_table_restore = efx_farch_filter_table_restore,
986 .filter_table_remove = efx_farch_filter_table_remove,
987 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
988 .filter_insert = efx_farch_filter_insert,
989 .filter_remove_safe = efx_farch_filter_remove_safe,
990 .filter_get_safe = efx_farch_filter_get_safe,
991 .filter_clear_rx = efx_farch_filter_clear_rx,
992 .filter_count_rx_used = efx_farch_filter_count_rx_used,
993 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
994 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
995#ifdef CONFIG_RFS_ACCEL
996 .filter_rfs_insert = efx_farch_filter_rfs_insert,
997 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
998#endif
999#ifdef CONFIG_SFC_MTD
1000 .mtd_probe = siena_mtd_probe,
1001 .mtd_rename = efx_mcdi_mtd_rename,
1002 .mtd_read = efx_mcdi_mtd_read,
1003 .mtd_erase = efx_mcdi_mtd_erase,
1004 .mtd_write = efx_mcdi_mtd_write,
1005 .mtd_sync = efx_mcdi_mtd_sync,
1006#endif
1007 .ptp_write_host_time = siena_ptp_write_host_time,
1008 .ptp_set_ts_config = siena_ptp_set_ts_config,
1009#ifdef CONFIG_SFC_SRIOV
1010 .sriov_configure = efx_siena_sriov_configure,
1011 .sriov_init = efx_siena_sriov_init,
1012 .sriov_fini = efx_siena_sriov_fini,
1013 .sriov_wanted = efx_siena_sriov_wanted,
1014 .sriov_reset = efx_siena_sriov_reset,
1015 .sriov_flr = efx_siena_sriov_flr,
1016 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1017 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1018 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1019 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1020 .vswitching_probe = efx_port_dummy_op_int,
1021 .vswitching_restore = efx_port_dummy_op_int,
1022 .vswitching_remove = efx_port_dummy_op_void,
1023 .set_mac_address = efx_siena_sriov_mac_address_changed,
1024#endif
1025
1026 .revision = EFX_REV_SIENA_A0,
1027 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1028 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1029 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1030 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1031 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1032 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1033 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1034 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1035 .rx_buffer_padding = 0,
1036 .can_rx_scatter = true,
1037 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1038 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1039 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1040 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1041 .mcdi_max_ver = 1,
1042 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1043 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1044 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1045 1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC |
1046 1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ |
1047 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT |
1048 1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC |
1049 1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ),
1050};