Linux kernel mirror (for testing)
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16/*
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
19 */
20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif
23#ifndef cpu_has_tlbinv
24#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
25#endif
26#ifndef cpu_has_segments
27#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
28#endif
29#ifndef cpu_has_eva
30#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
31#endif
32#ifndef cpu_has_htw
33#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
34#endif
35#ifndef cpu_has_rixiex
36#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
37#endif
38#ifndef cpu_has_maar
39#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
40#endif
41#ifndef cpu_has_rw_llb
42#define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
43#endif
44
45/*
46 * For the moment we don't consider R6000 and R8000 so we can assume that
47 * anything that doesn't support R4000-style exceptions and interrupts is
48 * R3000-like. Users should still treat these two macro definitions as
49 * opaque.
50 */
51#ifndef cpu_has_3kex
52#define cpu_has_3kex (!cpu_has_4kex)
53#endif
54#ifndef cpu_has_4kex
55#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
56#endif
57#ifndef cpu_has_3k_cache
58#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
59#endif
60#define cpu_has_6k_cache 0
61#define cpu_has_8k_cache 0
62#ifndef cpu_has_4k_cache
63#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
64#endif
65#ifndef cpu_has_tx39_cache
66#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
67#endif
68#ifndef cpu_has_octeon_cache
69#define cpu_has_octeon_cache 0
70#endif
71/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
72#ifndef cpu_has_fpu
73#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
74#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
75#else
76#define raw_cpu_has_fpu cpu_has_fpu
77#endif
78#ifndef cpu_has_32fpr
79#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
80#endif
81#ifndef cpu_has_counter
82#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
83#endif
84#ifndef cpu_has_watch
85#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
86#endif
87#ifndef cpu_has_divec
88#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
89#endif
90#ifndef cpu_has_vce
91#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
92#endif
93#ifndef cpu_has_cache_cdex_p
94#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
95#endif
96#ifndef cpu_has_cache_cdex_s
97#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
98#endif
99#ifndef cpu_has_prefetch
100#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
101#endif
102#ifndef cpu_has_mcheck
103#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
104#endif
105#ifndef cpu_has_ejtag
106#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
107#endif
108#ifndef cpu_has_llsc
109#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
110#endif
111#ifndef cpu_has_bp_ghist
112#define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST)
113#endif
114#ifndef kernel_uses_llsc
115#define kernel_uses_llsc cpu_has_llsc
116#endif
117#ifndef cpu_has_mips16
118#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
119#endif
120#ifndef cpu_has_mdmx
121#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
122#endif
123#ifndef cpu_has_mips3d
124#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
125#endif
126#ifndef cpu_has_smartmips
127#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
128#endif
129
130#ifndef cpu_has_rixi
131# ifdef CONFIG_64BIT
132# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
133# else /* CONFIG_32BIT */
134# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
135# endif
136#endif
137
138#ifndef cpu_has_mmips
139# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
140# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
141# else
142# define cpu_has_mmips 0
143# endif
144#endif
145
146#ifndef cpu_has_xpa
147#define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA)
148#endif
149#ifndef cpu_has_vtag_icache
150#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
151#endif
152#ifndef cpu_has_dc_aliases
153#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
154#endif
155#ifndef cpu_has_ic_fills_f_dc
156#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
157#endif
158#ifndef cpu_has_pindexed_dcache
159#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
160#endif
161#ifndef cpu_has_local_ebase
162#define cpu_has_local_ebase 1
163#endif
164
165/*
166 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
167 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
168 * don't. For maintaining I-cache coherency this means we need to flush the
169 * D-cache all the way back to whever the I-cache does refills from, so the
170 * I-cache has a chance to see the new data at all. Then we have to flush the
171 * I-cache also.
172 * Note we may have been rescheduled and may no longer be running on the CPU
173 * that did the store so we can't optimize this into only doing the flush on
174 * the local CPU.
175 */
176#ifndef cpu_icache_snoops_remote_store
177#ifdef CONFIG_SMP
178#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
179#else
180#define cpu_icache_snoops_remote_store 1
181#endif
182#endif
183
184#ifndef cpu_has_mips_1
185# define cpu_has_mips_1 (!cpu_has_mips_r6)
186#endif
187#ifndef cpu_has_mips_2
188# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
189#endif
190#ifndef cpu_has_mips_3
191# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
192#endif
193#ifndef cpu_has_mips_4
194# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
195#endif
196#ifndef cpu_has_mips_5
197# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
198#endif
199#ifndef cpu_has_mips32r1
200# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
201#endif
202#ifndef cpu_has_mips32r2
203# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
204#endif
205#ifndef cpu_has_mips32r6
206# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
207#endif
208#ifndef cpu_has_mips64r1
209# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
210#endif
211#ifndef cpu_has_mips64r2
212# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
213#endif
214#ifndef cpu_has_mips64r6
215# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
216#endif
217
218/*
219 * Shortcuts ...
220 */
221#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
222#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
223#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
224
225#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
226#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
227#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
228#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
229
230#define cpu_has_mips_3_4_5_64_r2_r6 \
231 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
232#define cpu_has_mips_4_5_64_r2_r6 \
233 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
234 cpu_has_mips_r2 | cpu_has_mips_r6)
235
236#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
237#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
238#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
239#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
240#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
241#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
242 cpu_has_mips32r6 | cpu_has_mips64r1 | \
243 cpu_has_mips64r2 | cpu_has_mips64r6)
244
245/* MIPSR2 and MIPSR6 have a lot of similarities */
246#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
247
248/*
249 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
250 *
251 * Returns non-zero value if the current processor implementation requires
252 * an IHB instruction to deal with an instruction hazard as per MIPS R2
253 * architecture specification, zero otherwise.
254 */
255#ifndef cpu_has_mips_r2_exec_hazard
256#define cpu_has_mips_r2_exec_hazard \
257({ \
258 int __res; \
259 \
260 switch (current_cpu_type()) { \
261 case CPU_M14KC: \
262 case CPU_74K: \
263 case CPU_1074K: \
264 case CPU_PROAPTIV: \
265 case CPU_P5600: \
266 case CPU_M5150: \
267 case CPU_QEMU_GENERIC: \
268 case CPU_CAVIUM_OCTEON: \
269 case CPU_CAVIUM_OCTEON_PLUS: \
270 case CPU_CAVIUM_OCTEON2: \
271 case CPU_CAVIUM_OCTEON3: \
272 __res = 0; \
273 break; \
274 \
275 default: \
276 __res = 1; \
277 } \
278 \
279 __res; \
280})
281#endif
282
283/*
284 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
285 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
286 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
287 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
288 */
289#ifndef cpu_has_clo_clz
290#define cpu_has_clo_clz cpu_has_mips_r
291#endif
292
293/*
294 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
295 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
296 * This indicates the availability of WSBH and in case of 64 bit CPUs also
297 * DSBH and DSHD.
298 */
299#ifndef cpu_has_wsbh
300#define cpu_has_wsbh cpu_has_mips_r2
301#endif
302
303#ifndef cpu_has_dsp
304#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
305#endif
306
307#ifndef cpu_has_dsp2
308#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
309#endif
310
311#ifndef cpu_has_mipsmt
312#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
313#endif
314
315#ifndef cpu_has_userlocal
316#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
317#endif
318
319#ifdef CONFIG_32BIT
320# ifndef cpu_has_nofpuex
321# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
322# endif
323# ifndef cpu_has_64bits
324# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
325# endif
326# ifndef cpu_has_64bit_zero_reg
327# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
328# endif
329# ifndef cpu_has_64bit_gp_regs
330# define cpu_has_64bit_gp_regs 0
331# endif
332# ifndef cpu_has_64bit_addresses
333# define cpu_has_64bit_addresses 0
334# endif
335# ifndef cpu_vmbits
336# define cpu_vmbits 31
337# endif
338#endif
339
340#ifdef CONFIG_64BIT
341# ifndef cpu_has_nofpuex
342# define cpu_has_nofpuex 0
343# endif
344# ifndef cpu_has_64bits
345# define cpu_has_64bits 1
346# endif
347# ifndef cpu_has_64bit_zero_reg
348# define cpu_has_64bit_zero_reg 1
349# endif
350# ifndef cpu_has_64bit_gp_regs
351# define cpu_has_64bit_gp_regs 1
352# endif
353# ifndef cpu_has_64bit_addresses
354# define cpu_has_64bit_addresses 1
355# endif
356# ifndef cpu_vmbits
357# define cpu_vmbits cpu_data[0].vmbits
358# define __NEED_VMBITS_PROBE
359# endif
360#endif
361
362#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
363# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
364#elif !defined(cpu_has_vint)
365# define cpu_has_vint 0
366#endif
367
368#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
369# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
370#elif !defined(cpu_has_veic)
371# define cpu_has_veic 0
372#endif
373
374#ifndef cpu_has_inclusive_pcaches
375#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
376#endif
377
378#ifndef cpu_dcache_line_size
379#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
380#endif
381#ifndef cpu_icache_line_size
382#define cpu_icache_line_size() cpu_data[0].icache.linesz
383#endif
384#ifndef cpu_scache_line_size
385#define cpu_scache_line_size() cpu_data[0].scache.linesz
386#endif
387
388#ifndef cpu_hwrena_impl_bits
389#define cpu_hwrena_impl_bits 0
390#endif
391
392#ifndef cpu_has_perf_cntr_intr_bit
393#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
394#endif
395
396#ifndef cpu_has_vz
397#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
398#endif
399
400#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
401# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
402#elif !defined(cpu_has_msa)
403# define cpu_has_msa 0
404#endif
405
406#ifndef cpu_has_fre
407# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
408#endif
409
410#ifndef cpu_has_cdmm
411# define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
412#endif
413
414#endif /* __ASM_CPU_FEATURES_H */