tjh.dev
Linux kernel mirror (for testing)
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linux
1/*
2 * Intel Core SoC Power Management Controller Header File
3 *
4 * Copyright (c) 2016, Intel Corporation.
5 * All Rights Reserved.
6 *
7 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
8 * Vishwanath Somayaji <vishwanath.somayaji@intel.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 */
20
21#ifndef PMC_CORE_H
22#define PMC_CORE_H
23
24#define PMC_BASE_ADDR_DEFAULT 0xFE000000
25
26/* Sunrise Point Power Management Controller PCI Device ID */
27#define SPT_PMC_PCI_DEVICE_ID 0x9d21
28#define SPT_PMC_BASE_ADDR_OFFSET 0x48
29#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
30#define SPT_PMC_PM_CFG_OFFSET 0x18
31#define SPT_PMC_PM_STS_OFFSET 0x1c
32#define SPT_PMC_MTPMC_OFFSET 0x20
33#define SPT_PMC_MFPMC_OFFSET 0x38
34#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
35#define SPT_PMC_MPHY_CORE_STS_0 0x1143
36#define SPT_PMC_MPHY_CORE_STS_1 0x1142
37#define SPT_PMC_MPHY_COM_STS_0 0x1155
38#define SPT_PMC_MMIO_REG_LEN 0x1000
39#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64
40#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
41#define MTPMC_MASK 0xffff0000
42#define PPFEAR_MAX_NUM_ENTRIES 5
43#define SPT_PPFEAR_NUM_ENTRIES 5
44#define SPT_PMC_READ_DISABLE_BIT 0x16
45#define SPT_PMC_MSG_FULL_STS_BIT 0x18
46#define NUM_RETRIES 100
47#define NUM_IP_IGN_ALLOWED 17
48
49/* Sunrise Point: PGD PFET Enable Ack Status Registers */
50enum ppfear_regs {
51 SPT_PMC_XRAM_PPFEAR0A = 0x590,
52 SPT_PMC_XRAM_PPFEAR0B,
53 SPT_PMC_XRAM_PPFEAR0C,
54 SPT_PMC_XRAM_PPFEAR0D,
55 SPT_PMC_XRAM_PPFEAR1A,
56};
57
58#define SPT_PMC_BIT_PMC BIT(0)
59#define SPT_PMC_BIT_OPI BIT(1)
60#define SPT_PMC_BIT_SPI BIT(2)
61#define SPT_PMC_BIT_XHCI BIT(3)
62#define SPT_PMC_BIT_SPA BIT(4)
63#define SPT_PMC_BIT_SPB BIT(5)
64#define SPT_PMC_BIT_SPC BIT(6)
65#define SPT_PMC_BIT_GBE BIT(7)
66
67#define SPT_PMC_BIT_SATA BIT(0)
68#define SPT_PMC_BIT_HDA_PGD0 BIT(1)
69#define SPT_PMC_BIT_HDA_PGD1 BIT(2)
70#define SPT_PMC_BIT_HDA_PGD2 BIT(3)
71#define SPT_PMC_BIT_HDA_PGD3 BIT(4)
72#define SPT_PMC_BIT_RSVD_0B BIT(5)
73#define SPT_PMC_BIT_LPSS BIT(6)
74#define SPT_PMC_BIT_LPC BIT(7)
75
76#define SPT_PMC_BIT_SMB BIT(0)
77#define SPT_PMC_BIT_ISH BIT(1)
78#define SPT_PMC_BIT_P2SB BIT(2)
79#define SPT_PMC_BIT_DFX BIT(3)
80#define SPT_PMC_BIT_SCC BIT(4)
81#define SPT_PMC_BIT_RSVD_0C BIT(5)
82#define SPT_PMC_BIT_FUSE BIT(6)
83#define SPT_PMC_BIT_CAMREA BIT(7)
84
85#define SPT_PMC_BIT_RSVD_0D BIT(0)
86#define SPT_PMC_BIT_USB3_OTG BIT(1)
87#define SPT_PMC_BIT_EXI BIT(2)
88#define SPT_PMC_BIT_CSE BIT(3)
89#define SPT_PMC_BIT_CSME_KVM BIT(4)
90#define SPT_PMC_BIT_CSME_PMT BIT(5)
91#define SPT_PMC_BIT_CSME_CLINK BIT(6)
92#define SPT_PMC_BIT_CSME_PTIO BIT(7)
93
94#define SPT_PMC_BIT_CSME_USBR BIT(0)
95#define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
96#define SPT_PMC_BIT_CSME_SMT BIT(2)
97#define SPT_PMC_BIT_RSVD_1A BIT(3)
98#define SPT_PMC_BIT_CSME_SMS2 BIT(4)
99#define SPT_PMC_BIT_CSME_SMS1 BIT(5)
100#define SPT_PMC_BIT_CSME_RTC BIT(6)
101#define SPT_PMC_BIT_CSME_PSF BIT(7)
102
103#define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
104#define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
105#define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
106#define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
107#define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
108#define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
109#define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
110#define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
111
112#define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
113#define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
114#define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
115#define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
116#define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
117#define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
118#define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
119#define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
120
121#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
122#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
123#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
124#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
125
126/* Cannonlake Power Management Controller register offsets */
127#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
128#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
129#define CNP_PMC_PM_CFG_OFFSET 0x1818
130#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
131/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
132#define CNP_PMC_HOST_PPFEAR0A 0x1D90
133
134#define CNP_PMC_MMIO_REG_LEN 0x2000
135#define CNP_PPFEAR_NUM_ENTRIES 8
136#define CNP_PMC_READ_DISABLE_BIT 22
137#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
138
139struct pmc_bit_map {
140 const char *name;
141 u32 bit_mask;
142};
143
144/**
145 * struct pmc_reg_map - Structure used to define parameter unique to a
146 PCH family
147 * @pfear_sts: Maps name of IP block to PPFEAR* bit
148 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
149 * @pll_sts: Maps name of PLL to corresponding bit status
150 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
151 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
152 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
153 * @regmap_length: Length of memory to map from PWRMBASE address to access
154 * @ppfear0_offset: PWRMBASE offset to to read PPFEAR*
155 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
156 * PPFEAR
157 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register
158 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
159 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
160 *
161 * Each PCH has unique set of register offsets and bit indexes. This structure
162 * captures them to have a common implementation.
163 */
164struct pmc_reg_map {
165 const struct pmc_bit_map *pfear_sts;
166 const struct pmc_bit_map *mphy_sts;
167 const struct pmc_bit_map *pll_sts;
168 const struct pmc_bit_map **slps0_dbg_maps;
169 const u32 slp_s0_offset;
170 const u32 ltr_ignore_offset;
171 const int regmap_length;
172 const u32 ppfear0_offset;
173 const int ppfear_buckets;
174 const u32 pm_cfg_offset;
175 const int pm_read_disable_bit;
176 const u32 slps0_dbg_offset;
177};
178
179/**
180 * struct pmc_dev - pmc device structure
181 * @base_addr: contains pmc base address
182 * @regbase: pointer to io-remapped memory location
183 * @map: pointer to pmc_reg_map struct that contains platform
184 * specific attributes
185 * @dbgfs_dir: path to debugfs interface
186 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
187 * used to read MPHY PG and PLL status are available
188 * @mutex_lock: mutex to complete one transcation
189 *
190 * pmc_dev contains info about power management controller device.
191 */
192struct pmc_dev {
193 u32 base_addr;
194 void __iomem *regbase;
195 const struct pmc_reg_map *map;
196#if IS_ENABLED(CONFIG_DEBUG_FS)
197 struct dentry *dbgfs_dir;
198#endif /* CONFIG_DEBUG_FS */
199 int pmc_xram_read_bit;
200 struct mutex lock; /* generic mutex lock for PMC Core */
201};
202
203#endif /* PMC_CORE_H */