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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * CS4271 ASoC codec driver
3 *
4 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * This driver support CS4271 codec being master or slave, working
17 * in control port mode, connected either via SPI or I2C.
18 * The data format accepted is I2S or left-justified.
19 * DAPM support not implemented.
20 */
21
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/delay.h>
25#include <linux/gpio.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <linux/regulator/consumer.h>
30#include <sound/pcm.h>
31#include <sound/soc.h>
32#include <sound/tlv.h>
33#include <sound/cs4271.h>
34#include "cs4271.h"
35
36#define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
37 SNDRV_PCM_FMTBIT_S24_LE | \
38 SNDRV_PCM_FMTBIT_S32_LE)
39#define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
40
41/*
42 * CS4271 registers
43 */
44#define CS4271_MODE1 0x01 /* Mode Control 1 */
45#define CS4271_DACCTL 0x02 /* DAC Control */
46#define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */
47#define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */
48#define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */
49#define CS4271_ADCCTL 0x06 /* ADC Control */
50#define CS4271_MODE2 0x07 /* Mode Control 2 */
51#define CS4271_CHIPID 0x08 /* Chip ID */
52
53#define CS4271_FIRSTREG CS4271_MODE1
54#define CS4271_LASTREG CS4271_MODE2
55#define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
56
57/* Bit masks for the CS4271 registers */
58#define CS4271_MODE1_MODE_MASK 0xC0
59#define CS4271_MODE1_MODE_1X 0x00
60#define CS4271_MODE1_MODE_2X 0x80
61#define CS4271_MODE1_MODE_4X 0xC0
62
63#define CS4271_MODE1_DIV_MASK 0x30
64#define CS4271_MODE1_DIV_1 0x00
65#define CS4271_MODE1_DIV_15 0x10
66#define CS4271_MODE1_DIV_2 0x20
67#define CS4271_MODE1_DIV_3 0x30
68
69#define CS4271_MODE1_MASTER 0x08
70
71#define CS4271_MODE1_DAC_DIF_MASK 0x07
72#define CS4271_MODE1_DAC_DIF_LJ 0x00
73#define CS4271_MODE1_DAC_DIF_I2S 0x01
74#define CS4271_MODE1_DAC_DIF_RJ16 0x02
75#define CS4271_MODE1_DAC_DIF_RJ24 0x03
76#define CS4271_MODE1_DAC_DIF_RJ20 0x04
77#define CS4271_MODE1_DAC_DIF_RJ18 0x05
78
79#define CS4271_DACCTL_AMUTE 0x80
80#define CS4271_DACCTL_IF_SLOW 0x40
81
82#define CS4271_DACCTL_DEM_MASK 0x30
83#define CS4271_DACCTL_DEM_DIS 0x00
84#define CS4271_DACCTL_DEM_441 0x10
85#define CS4271_DACCTL_DEM_48 0x20
86#define CS4271_DACCTL_DEM_32 0x30
87
88#define CS4271_DACCTL_SVRU 0x08
89#define CS4271_DACCTL_SRD 0x04
90#define CS4271_DACCTL_INVA 0x02
91#define CS4271_DACCTL_INVB 0x01
92
93#define CS4271_DACVOL_BEQUA 0x40
94#define CS4271_DACVOL_SOFT 0x20
95#define CS4271_DACVOL_ZEROC 0x10
96
97#define CS4271_DACVOL_ATAPI_MASK 0x0F
98#define CS4271_DACVOL_ATAPI_M_M 0x00
99#define CS4271_DACVOL_ATAPI_M_BR 0x01
100#define CS4271_DACVOL_ATAPI_M_BL 0x02
101#define CS4271_DACVOL_ATAPI_M_BLR2 0x03
102#define CS4271_DACVOL_ATAPI_AR_M 0x04
103#define CS4271_DACVOL_ATAPI_AR_BR 0x05
104#define CS4271_DACVOL_ATAPI_AR_BL 0x06
105#define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
106#define CS4271_DACVOL_ATAPI_AL_M 0x08
107#define CS4271_DACVOL_ATAPI_AL_BR 0x09
108#define CS4271_DACVOL_ATAPI_AL_BL 0x0A
109#define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
110#define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
111#define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
112#define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
113#define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
114
115#define CS4271_VOLA_MUTE 0x80
116#define CS4271_VOLA_VOL_MASK 0x7F
117#define CS4271_VOLB_MUTE 0x80
118#define CS4271_VOLB_VOL_MASK 0x7F
119
120#define CS4271_ADCCTL_DITHER16 0x20
121
122#define CS4271_ADCCTL_ADC_DIF_MASK 0x10
123#define CS4271_ADCCTL_ADC_DIF_LJ 0x00
124#define CS4271_ADCCTL_ADC_DIF_I2S 0x10
125
126#define CS4271_ADCCTL_MUTEA 0x08
127#define CS4271_ADCCTL_MUTEB 0x04
128#define CS4271_ADCCTL_HPFDA 0x02
129#define CS4271_ADCCTL_HPFDB 0x01
130
131#define CS4271_MODE2_LOOP 0x10
132#define CS4271_MODE2_MUTECAEQUB 0x08
133#define CS4271_MODE2_FREEZE 0x04
134#define CS4271_MODE2_CPEN 0x02
135#define CS4271_MODE2_PDN 0x01
136
137#define CS4271_CHIPID_PART_MASK 0xF0
138#define CS4271_CHIPID_REV_MASK 0x0F
139
140/*
141 * Default CS4271 power-up configuration
142 * Array contains non-existing in hw register at address 0
143 * Array do not include Chip ID, as codec driver does not use
144 * registers read operations at all
145 */
146static const struct reg_default cs4271_reg_defaults[] = {
147 { CS4271_MODE1, 0, },
148 { CS4271_DACCTL, CS4271_DACCTL_AMUTE, },
149 { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
150 { CS4271_VOLA, 0, },
151 { CS4271_VOLB, 0, },
152 { CS4271_ADCCTL, 0, },
153 { CS4271_MODE2, 0, },
154};
155
156static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
157{
158 return reg == CS4271_CHIPID;
159}
160
161static const char * const supply_names[] = {
162 "vd", "vl", "va"
163};
164
165struct cs4271_private {
166 unsigned int mclk;
167 bool master;
168 bool deemph;
169 struct regmap *regmap;
170 /* Current sample rate for de-emphasis control */
171 int rate;
172 /* GPIO driving Reset pin, if any */
173 int gpio_nreset;
174 /* GPIO that disable serial bus, if any */
175 int gpio_disable;
176 /* enable soft reset workaround */
177 bool enable_soft_reset;
178 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
179};
180
181static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
182SND_SOC_DAPM_INPUT("AINA"),
183SND_SOC_DAPM_INPUT("AINB"),
184
185SND_SOC_DAPM_OUTPUT("AOUTA+"),
186SND_SOC_DAPM_OUTPUT("AOUTA-"),
187SND_SOC_DAPM_OUTPUT("AOUTB+"),
188SND_SOC_DAPM_OUTPUT("AOUTB-"),
189};
190
191static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
192 { "Capture", NULL, "AINA" },
193 { "Capture", NULL, "AINB" },
194
195 { "AOUTA+", NULL, "Playback" },
196 { "AOUTA-", NULL, "Playback" },
197 { "AOUTB+", NULL, "Playback" },
198 { "AOUTB-", NULL, "Playback" },
199};
200
201/*
202 * @freq is the desired MCLK rate
203 * MCLK rate should (c) be the sample rate, multiplied by one of the
204 * ratios listed in cs4271_mclk_fs_ratios table
205 */
206static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
207 int clk_id, unsigned int freq, int dir)
208{
209 struct snd_soc_component *component = codec_dai->component;
210 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
211
212 cs4271->mclk = freq;
213 return 0;
214}
215
216static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
217 unsigned int format)
218{
219 struct snd_soc_component *component = codec_dai->component;
220 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
221 unsigned int val = 0;
222 int ret;
223
224 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
225 case SND_SOC_DAIFMT_CBS_CFS:
226 cs4271->master = 0;
227 break;
228 case SND_SOC_DAIFMT_CBM_CFM:
229 cs4271->master = 1;
230 val |= CS4271_MODE1_MASTER;
231 break;
232 default:
233 dev_err(component->dev, "Invalid DAI format\n");
234 return -EINVAL;
235 }
236
237 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
238 case SND_SOC_DAIFMT_LEFT_J:
239 val |= CS4271_MODE1_DAC_DIF_LJ;
240 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
241 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
242 if (ret < 0)
243 return ret;
244 break;
245 case SND_SOC_DAIFMT_I2S:
246 val |= CS4271_MODE1_DAC_DIF_I2S;
247 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
248 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
249 if (ret < 0)
250 return ret;
251 break;
252 default:
253 dev_err(component->dev, "Invalid DAI format\n");
254 return -EINVAL;
255 }
256
257 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
258 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
259 if (ret < 0)
260 return ret;
261 return 0;
262}
263
264static int cs4271_deemph[] = {0, 44100, 48000, 32000};
265
266static int cs4271_set_deemph(struct snd_soc_component *component)
267{
268 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
269 int i, ret;
270 int val = CS4271_DACCTL_DEM_DIS;
271
272 if (cs4271->deemph) {
273 /* Find closest de-emphasis freq */
274 val = 1;
275 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
276 if (abs(cs4271_deemph[i] - cs4271->rate) <
277 abs(cs4271_deemph[val] - cs4271->rate))
278 val = i;
279 val <<= 4;
280 }
281
282 ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL,
283 CS4271_DACCTL_DEM_MASK, val);
284 if (ret < 0)
285 return ret;
286 return 0;
287}
288
289static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_value *ucontrol)
291{
292 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
293 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
294
295 ucontrol->value.integer.value[0] = cs4271->deemph;
296 return 0;
297}
298
299static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
300 struct snd_ctl_elem_value *ucontrol)
301{
302 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
303 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
304
305 cs4271->deemph = ucontrol->value.integer.value[0];
306 return cs4271_set_deemph(component);
307}
308
309struct cs4271_clk_cfg {
310 bool master; /* codec mode */
311 u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */
312 unsigned short ratio; /* MCLK / sample rate */
313 u8 ratio_mask; /* ratio bit mask for Master mode */
314};
315
316static struct cs4271_clk_cfg cs4271_clk_tab[] = {
317 {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
318 {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15},
319 {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2},
320 {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3},
321 {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
322 {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15},
323 {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2},
324 {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3},
325 {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
326 {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15},
327 {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2},
328 {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3},
329 {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
330 {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1},
331 {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1},
332 {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2},
333 {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
334 {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
335 {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1},
336 {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1},
337 {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2},
338 {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2},
339 {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
340 {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1},
341 {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1},
342 {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2},
343 {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2},
344};
345
346#define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
347
348static int cs4271_hw_params(struct snd_pcm_substream *substream,
349 struct snd_pcm_hw_params *params,
350 struct snd_soc_dai *dai)
351{
352 struct snd_soc_component *component = dai->component;
353 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
354 int i, ret;
355 unsigned int ratio, val;
356
357 if (cs4271->enable_soft_reset) {
358 /*
359 * Put the codec in soft reset and back again in case it's not
360 * currently streaming data. This way of bringing the codec in
361 * sync to the current clocks is not explicitly documented in
362 * the data sheet, but it seems to work fine, and in contrast
363 * to a read hardware reset, we don't have to sync back all
364 * registers every time.
365 */
366
367 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
368 !dai->capture_active) ||
369 (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
370 !dai->playback_active)) {
371 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
372 CS4271_MODE2_PDN,
373 CS4271_MODE2_PDN);
374 if (ret < 0)
375 return ret;
376
377 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
378 CS4271_MODE2_PDN, 0);
379 if (ret < 0)
380 return ret;
381 }
382 }
383
384 cs4271->rate = params_rate(params);
385
386 /* Configure DAC */
387 if (cs4271->rate < 50000)
388 val = CS4271_MODE1_MODE_1X;
389 else if (cs4271->rate < 100000)
390 val = CS4271_MODE1_MODE_2X;
391 else
392 val = CS4271_MODE1_MODE_4X;
393
394 ratio = cs4271->mclk / cs4271->rate;
395 for (i = 0; i < CS4171_NR_RATIOS; i++)
396 if ((cs4271_clk_tab[i].master == cs4271->master) &&
397 (cs4271_clk_tab[i].speed_mode == val) &&
398 (cs4271_clk_tab[i].ratio == ratio))
399 break;
400
401 if (i == CS4171_NR_RATIOS) {
402 dev_err(component->dev, "Invalid sample rate\n");
403 return -EINVAL;
404 }
405
406 val |= cs4271_clk_tab[i].ratio_mask;
407
408 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
409 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
410 if (ret < 0)
411 return ret;
412
413 return cs4271_set_deemph(component);
414}
415
416static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
417{
418 struct snd_soc_component *component = dai->component;
419 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
420 int ret;
421 int val_a = 0;
422 int val_b = 0;
423
424 if (stream != SNDRV_PCM_STREAM_PLAYBACK)
425 return 0;
426
427 if (mute) {
428 val_a = CS4271_VOLA_MUTE;
429 val_b = CS4271_VOLB_MUTE;
430 }
431
432 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA,
433 CS4271_VOLA_MUTE, val_a);
434 if (ret < 0)
435 return ret;
436
437 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB,
438 CS4271_VOLB_MUTE, val_b);
439 if (ret < 0)
440 return ret;
441
442 return 0;
443}
444
445/* CS4271 controls */
446static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
447
448static const struct snd_kcontrol_new cs4271_snd_controls[] = {
449 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
450 0, 0x7F, 1, cs4271_dac_tlv),
451 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
452 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
453 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
454 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
455 cs4271_get_deemph, cs4271_put_deemph),
456 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
457 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
458 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
459 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
460 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
461 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
462 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
463 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
464 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
465 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
466 7, 1, 1),
467};
468
469static const struct snd_soc_dai_ops cs4271_dai_ops = {
470 .hw_params = cs4271_hw_params,
471 .set_sysclk = cs4271_set_dai_sysclk,
472 .set_fmt = cs4271_set_dai_fmt,
473 .mute_stream = cs4271_mute_stream,
474};
475
476static struct snd_soc_dai_driver cs4271_dai = {
477 .name = "cs4271-hifi",
478 .playback = {
479 .stream_name = "Playback",
480 .channels_min = 2,
481 .channels_max = 2,
482 .rates = CS4271_PCM_RATES,
483 .formats = CS4271_PCM_FORMATS,
484 },
485 .capture = {
486 .stream_name = "Capture",
487 .channels_min = 2,
488 .channels_max = 2,
489 .rates = CS4271_PCM_RATES,
490 .formats = CS4271_PCM_FORMATS,
491 },
492 .ops = &cs4271_dai_ops,
493 .symmetric_rates = 1,
494};
495
496static int cs4271_reset(struct snd_soc_component *component)
497{
498 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
499
500 if (gpio_is_valid(cs4271->gpio_nreset)) {
501 gpio_direction_output(cs4271->gpio_nreset, 0);
502 mdelay(1);
503 gpio_set_value(cs4271->gpio_nreset, 1);
504 mdelay(1);
505 }
506
507 return 0;
508}
509
510#ifdef CONFIG_PM
511static int cs4271_soc_suspend(struct snd_soc_component *component)
512{
513 int ret;
514 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
515
516 /* Set power-down bit */
517 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
518 CS4271_MODE2_PDN, CS4271_MODE2_PDN);
519 if (ret < 0)
520 return ret;
521
522 regcache_mark_dirty(cs4271->regmap);
523 regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
524
525 return 0;
526}
527
528static int cs4271_soc_resume(struct snd_soc_component *component)
529{
530 int ret;
531 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
532
533 ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
534 cs4271->supplies);
535 if (ret < 0) {
536 dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
537 return ret;
538 }
539
540 /* Do a proper reset after power up */
541 cs4271_reset(component);
542
543 /* Restore codec state */
544 ret = regcache_sync(cs4271->regmap);
545 if (ret < 0)
546 return ret;
547
548 /* then disable the power-down bit */
549 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
550 CS4271_MODE2_PDN, 0);
551 if (ret < 0)
552 return ret;
553
554 return 0;
555}
556#else
557#define cs4271_soc_suspend NULL
558#define cs4271_soc_resume NULL
559#endif /* CONFIG_PM */
560
561#ifdef CONFIG_OF
562const struct of_device_id cs4271_dt_ids[] = {
563 { .compatible = "cirrus,cs4271", },
564 { }
565};
566MODULE_DEVICE_TABLE(of, cs4271_dt_ids);
567EXPORT_SYMBOL_GPL(cs4271_dt_ids);
568#endif
569
570static int cs4271_component_probe(struct snd_soc_component *component)
571{
572 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
573 struct cs4271_platform_data *cs4271plat = component->dev->platform_data;
574 int ret;
575 bool amutec_eq_bmutec = false;
576
577#ifdef CONFIG_OF
578 if (of_match_device(cs4271_dt_ids, component->dev)) {
579 if (of_get_property(component->dev->of_node,
580 "cirrus,amutec-eq-bmutec", NULL))
581 amutec_eq_bmutec = true;
582
583 if (of_get_property(component->dev->of_node,
584 "cirrus,enable-soft-reset", NULL))
585 cs4271->enable_soft_reset = true;
586 }
587#endif
588
589 ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
590 cs4271->supplies);
591 if (ret < 0) {
592 dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
593 return ret;
594 }
595
596 if (cs4271plat) {
597 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
598 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
599 }
600
601 /* Reset codec */
602 cs4271_reset(component);
603
604 ret = regcache_sync(cs4271->regmap);
605 if (ret < 0)
606 return ret;
607
608 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
609 CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
610 CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
611 if (ret < 0)
612 return ret;
613 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
614 CS4271_MODE2_PDN, 0);
615 if (ret < 0)
616 return ret;
617 /* Power-up sequence requires 85 uS */
618 udelay(85);
619
620 if (amutec_eq_bmutec)
621 regmap_update_bits(cs4271->regmap, CS4271_MODE2,
622 CS4271_MODE2_MUTECAEQUB,
623 CS4271_MODE2_MUTECAEQUB);
624
625 return 0;
626}
627
628static void cs4271_component_remove(struct snd_soc_component *component)
629{
630 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
631
632 if (gpio_is_valid(cs4271->gpio_nreset))
633 /* Set codec to the reset state */
634 gpio_set_value(cs4271->gpio_nreset, 0);
635
636 regcache_mark_dirty(cs4271->regmap);
637 regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
638};
639
640static const struct snd_soc_component_driver soc_component_dev_cs4271 = {
641 .probe = cs4271_component_probe,
642 .remove = cs4271_component_remove,
643 .suspend = cs4271_soc_suspend,
644 .resume = cs4271_soc_resume,
645 .controls = cs4271_snd_controls,
646 .num_controls = ARRAY_SIZE(cs4271_snd_controls),
647 .dapm_widgets = cs4271_dapm_widgets,
648 .num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets),
649 .dapm_routes = cs4271_dapm_routes,
650 .num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes),
651 .idle_bias_on = 1,
652 .use_pmdown_time = 1,
653 .endianness = 1,
654 .non_legacy_dai_naming = 1,
655};
656
657static int cs4271_common_probe(struct device *dev,
658 struct cs4271_private **c)
659{
660 struct cs4271_platform_data *cs4271plat = dev->platform_data;
661 struct cs4271_private *cs4271;
662 int i, ret;
663
664 cs4271 = devm_kzalloc(dev, sizeof(*cs4271), GFP_KERNEL);
665 if (!cs4271)
666 return -ENOMEM;
667
668 if (of_match_device(cs4271_dt_ids, dev))
669 cs4271->gpio_nreset =
670 of_get_named_gpio(dev->of_node, "reset-gpio", 0);
671
672 if (cs4271plat)
673 cs4271->gpio_nreset = cs4271plat->gpio_nreset;
674
675 if (gpio_is_valid(cs4271->gpio_nreset)) {
676 ret = devm_gpio_request(dev, cs4271->gpio_nreset,
677 "CS4271 Reset");
678 if (ret < 0)
679 return ret;
680 }
681
682 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
683 cs4271->supplies[i].supply = supply_names[i];
684
685 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs4271->supplies),
686 cs4271->supplies);
687
688 if (ret < 0) {
689 dev_err(dev, "Failed to get regulators: %d\n", ret);
690 return ret;
691 }
692
693 *c = cs4271;
694 return 0;
695}
696
697const struct regmap_config cs4271_regmap_config = {
698 .max_register = CS4271_LASTREG,
699
700 .reg_defaults = cs4271_reg_defaults,
701 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
702 .cache_type = REGCACHE_RBTREE,
703
704 .volatile_reg = cs4271_volatile_reg,
705};
706EXPORT_SYMBOL_GPL(cs4271_regmap_config);
707
708int cs4271_probe(struct device *dev, struct regmap *regmap)
709{
710 struct cs4271_private *cs4271;
711 int ret;
712
713 if (IS_ERR(regmap))
714 return PTR_ERR(regmap);
715
716 ret = cs4271_common_probe(dev, &cs4271);
717 if (ret < 0)
718 return ret;
719
720 dev_set_drvdata(dev, cs4271);
721 cs4271->regmap = regmap;
722
723 return devm_snd_soc_register_component(dev, &soc_component_dev_cs4271,
724 &cs4271_dai, 1);
725}
726EXPORT_SYMBOL_GPL(cs4271_probe);
727
728MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
729MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
730MODULE_LICENSE("GPL");