Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 MLX5_SET(typ, p, fld[idx], v); \
85} while (0)
86
87#define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 << __mlx5_dw_bit_off(typ, fld))); \
93} while (0)
94
95#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97__mlx5_mask(typ, fld))
98
99#define MLX5_GET_PR(typ, p, fld) ({ \
100 u32 ___t = MLX5_GET(typ, p, fld); \
101 pr_debug(#fld " = 0x%x\n", ___t); \
102 ___t; \
103})
104
105#define __MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108} while (0)
109
110#define MLX5_SET64(typ, p, fld, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld, v); \
113} while (0)
114
115#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 __MLX5_SET64(typ, p, fld[idx], v); \
118} while (0)
119
120#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET64_PR(typ, p, fld) ({ \
123 u64 ___t = MLX5_GET64(typ, p, fld); \
124 pr_debug(#fld " = 0x%llx\n", ___t); \
125 ___t; \
126})
127
128#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130__mlx5_mask16(typ, fld))
131
132#define MLX5_SET16(typ, p, fld, v) do { \
133 u16 _v = v; \
134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 << __mlx5_16_bit_off(typ, fld))); \
139} while (0)
140
141/* Big endian getters */
142#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 __mlx5_64_off(typ, fld)))
144
145#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
146 type_t tmp; \
147 switch (sizeof(tmp)) { \
148 case sizeof(u8): \
149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
150 break; \
151 case sizeof(u16): \
152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 break; \
154 case sizeof(u32): \
155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 break; \
157 case sizeof(u64): \
158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 break; \
160 } \
161 tmp; \
162 })
163
164enum mlx5_inline_modes {
165 MLX5_INLINE_MODE_NONE,
166 MLX5_INLINE_MODE_L2,
167 MLX5_INLINE_MODE_IP,
168 MLX5_INLINE_MODE_TCP_UDP,
169};
170
171enum {
172 MLX5_MAX_COMMANDS = 32,
173 MLX5_CMD_DATA_BLOCK_SIZE = 512,
174 MLX5_PCI_CMD_XPORT = 7,
175 MLX5_MKEY_BSF_OCTO_SIZE = 4,
176 MLX5_MAX_PSVS = 4,
177};
178
179enum {
180 MLX5_EXTENDED_UD_AV = 0x80000000,
181};
182
183enum {
184 MLX5_CQ_STATE_ARMED = 9,
185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
186 MLX5_CQ_STATE_FIRED = 0xa,
187};
188
189enum {
190 MLX5_STAT_RATE_OFFSET = 5,
191};
192
193enum {
194 MLX5_INLINE_SEG = 0x80000000,
195};
196
197enum {
198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199};
200
201enum {
202 MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 MLX5_MAX_LOG_PKEY_TABLE = 5,
204};
205
206enum {
207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208};
209
210enum {
211 MLX5_PFAULT_SUBTYPE_WQE = 0,
212 MLX5_PFAULT_SUBTYPE_RDMA = 1,
213};
214
215enum {
216 MLX5_PERM_LOCAL_READ = 1 << 2,
217 MLX5_PERM_LOCAL_WRITE = 1 << 3,
218 MLX5_PERM_REMOTE_READ = 1 << 4,
219 MLX5_PERM_REMOTE_WRITE = 1 << 5,
220 MLX5_PERM_ATOMIC = 1 << 6,
221 MLX5_PERM_UMR_EN = 1 << 7,
222};
223
224enum {
225 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
226 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
227 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
228 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
229 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
230};
231
232enum {
233 MLX5_EN_RD = (u64)1,
234 MLX5_EN_WR = (u64)2
235};
236
237enum {
238 MLX5_ADAPTER_PAGE_SHIFT = 12,
239 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
240};
241
242enum {
243 MLX5_BFREGS_PER_UAR = 4,
244 MLX5_MAX_UARS = 1 << 8,
245 MLX5_NON_FP_BFREGS_PER_UAR = 2,
246 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
247 MLX5_NON_FP_BFREGS_PER_UAR,
248 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
249 MLX5_NON_FP_BFREGS_PER_UAR,
250 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
251 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
252 MLX5_MIN_DYN_BFREGS = 512,
253 MLX5_MAX_DYN_BFREGS = 1024,
254};
255
256enum {
257 MLX5_MKEY_MASK_LEN = 1ull << 0,
258 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
259 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
260 MLX5_MKEY_MASK_PD = 1ull << 7,
261 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
262 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
263 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
264 MLX5_MKEY_MASK_KEY = 1ull << 13,
265 MLX5_MKEY_MASK_QPN = 1ull << 14,
266 MLX5_MKEY_MASK_LR = 1ull << 17,
267 MLX5_MKEY_MASK_LW = 1ull << 18,
268 MLX5_MKEY_MASK_RR = 1ull << 19,
269 MLX5_MKEY_MASK_RW = 1ull << 20,
270 MLX5_MKEY_MASK_A = 1ull << 21,
271 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
272 MLX5_MKEY_MASK_FREE = 1ull << 29,
273};
274
275enum {
276 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
277
278 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
279 MLX5_UMR_CHECK_FREE = (2 << 5),
280
281 MLX5_UMR_INLINE = (1 << 7),
282};
283
284#define MLX5_UMR_MTT_ALIGNMENT 0x40
285#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
286#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
287
288#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
289
290enum {
291 MLX5_EVENT_QUEUE_TYPE_QP = 0,
292 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
293 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
294 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
295};
296
297enum mlx5_event {
298 MLX5_EVENT_TYPE_COMP = 0x0,
299
300 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
301 MLX5_EVENT_TYPE_COMM_EST = 0x02,
302 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
303 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
304 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
305
306 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
307 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
308 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
309 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
310 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
311 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
312
313 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
314 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
315 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
316 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
317 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
318 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
319 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
320 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
321
322 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
323 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
324
325 MLX5_EVENT_TYPE_CMD = 0x0a,
326 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
327
328 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
329 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
330
331 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
332
333 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
334 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
335};
336
337enum {
338 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
339};
340
341enum {
342 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
343 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
344 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
345 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
346 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
347 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
348 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
349};
350
351enum {
352 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
353 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
354 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
355 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
356 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
357 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
358 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
359 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
360 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
361 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
362 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
363 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
364};
365
366enum {
367 MLX5_ROCE_VERSION_1 = 0,
368 MLX5_ROCE_VERSION_2 = 2,
369};
370
371enum {
372 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
373 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
374};
375
376enum {
377 MLX5_ROCE_L3_TYPE_IPV4 = 0,
378 MLX5_ROCE_L3_TYPE_IPV6 = 1,
379};
380
381enum {
382 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
383 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
384};
385
386enum {
387 MLX5_OPCODE_NOP = 0x00,
388 MLX5_OPCODE_SEND_INVAL = 0x01,
389 MLX5_OPCODE_RDMA_WRITE = 0x08,
390 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
391 MLX5_OPCODE_SEND = 0x0a,
392 MLX5_OPCODE_SEND_IMM = 0x0b,
393 MLX5_OPCODE_LSO = 0x0e,
394 MLX5_OPCODE_RDMA_READ = 0x10,
395 MLX5_OPCODE_ATOMIC_CS = 0x11,
396 MLX5_OPCODE_ATOMIC_FA = 0x12,
397 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
398 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
399 MLX5_OPCODE_BIND_MW = 0x18,
400 MLX5_OPCODE_CONFIG_CMD = 0x1f,
401
402 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
403 MLX5_RECV_OPCODE_SEND = 0x01,
404 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
405 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
406
407 MLX5_CQE_OPCODE_ERROR = 0x1e,
408 MLX5_CQE_OPCODE_RESIZE = 0x16,
409
410 MLX5_OPCODE_SET_PSV = 0x20,
411 MLX5_OPCODE_GET_PSV = 0x21,
412 MLX5_OPCODE_CHECK_PSV = 0x22,
413 MLX5_OPCODE_RGET_PSV = 0x26,
414 MLX5_OPCODE_RCHECK_PSV = 0x27,
415
416 MLX5_OPCODE_UMR = 0x25,
417
418};
419
420enum {
421 MLX5_SET_PORT_RESET_QKEY = 0,
422 MLX5_SET_PORT_GUID0 = 16,
423 MLX5_SET_PORT_NODE_GUID = 17,
424 MLX5_SET_PORT_SYS_GUID = 18,
425 MLX5_SET_PORT_GID_TABLE = 19,
426 MLX5_SET_PORT_PKEY_TABLE = 20,
427};
428
429enum {
430 MLX5_BW_NO_LIMIT = 0,
431 MLX5_100_MBPS_UNIT = 3,
432 MLX5_GBPS_UNIT = 4,
433};
434
435enum {
436 MLX5_MAX_PAGE_SHIFT = 31
437};
438
439enum {
440 MLX5_CAP_OFF_CMDIF_CSUM = 46,
441};
442
443enum {
444 /*
445 * Max wqe size for rdma read is 512 bytes, so this
446 * limits our max_sge_rd as the wqe needs to fit:
447 * - ctrl segment (16 bytes)
448 * - rdma segment (16 bytes)
449 * - scatter elements (16 bytes each)
450 */
451 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
452};
453
454enum mlx5_odp_transport_cap_bits {
455 MLX5_ODP_SUPPORT_SEND = 1 << 31,
456 MLX5_ODP_SUPPORT_RECV = 1 << 30,
457 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
458 MLX5_ODP_SUPPORT_READ = 1 << 28,
459};
460
461struct mlx5_odp_caps {
462 char reserved[0x10];
463 struct {
464 __be32 rc_odp_caps;
465 __be32 uc_odp_caps;
466 __be32 ud_odp_caps;
467 } per_transport_caps;
468 char reserved2[0xe4];
469};
470
471struct mlx5_cmd_layout {
472 u8 type;
473 u8 rsvd0[3];
474 __be32 inlen;
475 __be64 in_ptr;
476 __be32 in[4];
477 __be32 out[4];
478 __be64 out_ptr;
479 __be32 outlen;
480 u8 token;
481 u8 sig;
482 u8 rsvd1;
483 u8 status_own;
484};
485
486struct health_buffer {
487 __be32 assert_var[5];
488 __be32 rsvd0[3];
489 __be32 assert_exit_ptr;
490 __be32 assert_callra;
491 __be32 rsvd1[2];
492 __be32 fw_ver;
493 __be32 hw_id;
494 __be32 rsvd2;
495 u8 irisc_index;
496 u8 synd;
497 __be16 ext_synd;
498};
499
500struct mlx5_init_seg {
501 __be32 fw_rev;
502 __be32 cmdif_rev_fw_sub;
503 __be32 rsvd0[2];
504 __be32 cmdq_addr_h;
505 __be32 cmdq_addr_l_sz;
506 __be32 cmd_dbell;
507 __be32 rsvd1[120];
508 __be32 initializing;
509 struct health_buffer health;
510 __be32 rsvd2[880];
511 __be32 internal_timer_h;
512 __be32 internal_timer_l;
513 __be32 rsvd3[2];
514 __be32 health_counter;
515 __be32 rsvd4[1019];
516 __be64 ieee1588_clk;
517 __be32 ieee1588_clk_type;
518 __be32 clr_intx;
519};
520
521struct mlx5_eqe_comp {
522 __be32 reserved[6];
523 __be32 cqn;
524};
525
526struct mlx5_eqe_qp_srq {
527 __be32 reserved1[5];
528 u8 type;
529 u8 reserved2[3];
530 __be32 qp_srq_n;
531};
532
533struct mlx5_eqe_cq_err {
534 __be32 cqn;
535 u8 reserved1[7];
536 u8 syndrome;
537};
538
539struct mlx5_eqe_port_state {
540 u8 reserved0[8];
541 u8 port;
542};
543
544struct mlx5_eqe_gpio {
545 __be32 reserved0[2];
546 __be64 gpio_event;
547};
548
549struct mlx5_eqe_congestion {
550 u8 type;
551 u8 rsvd0;
552 u8 congestion_level;
553};
554
555struct mlx5_eqe_stall_vl {
556 u8 rsvd0[3];
557 u8 port_vl;
558};
559
560struct mlx5_eqe_cmd {
561 __be32 vector;
562 __be32 rsvd[6];
563};
564
565struct mlx5_eqe_page_req {
566 u8 rsvd0[2];
567 __be16 func_id;
568 __be32 num_pages;
569 __be32 rsvd1[5];
570};
571
572struct mlx5_eqe_page_fault {
573 __be32 bytes_committed;
574 union {
575 struct {
576 u16 reserved1;
577 __be16 wqe_index;
578 u16 reserved2;
579 __be16 packet_length;
580 __be32 token;
581 u8 reserved4[8];
582 __be32 pftype_wq;
583 } __packed wqe;
584 struct {
585 __be32 r_key;
586 u16 reserved1;
587 __be16 packet_length;
588 __be32 rdma_op_len;
589 __be64 rdma_va;
590 __be32 pftype_token;
591 } __packed rdma;
592 } __packed;
593} __packed;
594
595struct mlx5_eqe_vport_change {
596 u8 rsvd0[2];
597 __be16 vport_num;
598 __be32 rsvd1[6];
599} __packed;
600
601struct mlx5_eqe_port_module {
602 u8 reserved_at_0[1];
603 u8 module;
604 u8 reserved_at_2[1];
605 u8 module_status;
606 u8 reserved_at_4[2];
607 u8 error_type;
608} __packed;
609
610struct mlx5_eqe_pps {
611 u8 rsvd0[3];
612 u8 pin;
613 u8 rsvd1[4];
614 union {
615 struct {
616 __be32 time_sec;
617 __be32 time_nsec;
618 };
619 struct {
620 __be64 time_stamp;
621 };
622 };
623 u8 rsvd2[12];
624} __packed;
625
626struct mlx5_eqe_dct {
627 __be32 reserved[6];
628 __be32 dctn;
629};
630
631struct mlx5_eqe_temp_warning {
632 __be64 sensor_warning_msb;
633 __be64 sensor_warning_lsb;
634} __packed;
635
636union ev_data {
637 __be32 raw[7];
638 struct mlx5_eqe_cmd cmd;
639 struct mlx5_eqe_comp comp;
640 struct mlx5_eqe_qp_srq qp_srq;
641 struct mlx5_eqe_cq_err cq_err;
642 struct mlx5_eqe_port_state port;
643 struct mlx5_eqe_gpio gpio;
644 struct mlx5_eqe_congestion cong;
645 struct mlx5_eqe_stall_vl stall_vl;
646 struct mlx5_eqe_page_req req_pages;
647 struct mlx5_eqe_page_fault page_fault;
648 struct mlx5_eqe_vport_change vport_change;
649 struct mlx5_eqe_port_module port_module;
650 struct mlx5_eqe_pps pps;
651 struct mlx5_eqe_dct dct;
652 struct mlx5_eqe_temp_warning temp_warning;
653} __packed;
654
655struct mlx5_eqe {
656 u8 rsvd0;
657 u8 type;
658 u8 rsvd1;
659 u8 sub_type;
660 __be32 rsvd2[7];
661 union ev_data data;
662 __be16 rsvd3;
663 u8 signature;
664 u8 owner;
665} __packed;
666
667struct mlx5_cmd_prot_block {
668 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
669 u8 rsvd0[48];
670 __be64 next;
671 __be32 block_num;
672 u8 rsvd1;
673 u8 token;
674 u8 ctrl_sig;
675 u8 sig;
676};
677
678enum {
679 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
680};
681
682struct mlx5_err_cqe {
683 u8 rsvd0[32];
684 __be32 srqn;
685 u8 rsvd1[18];
686 u8 vendor_err_synd;
687 u8 syndrome;
688 __be32 s_wqe_opcode_qpn;
689 __be16 wqe_counter;
690 u8 signature;
691 u8 op_own;
692};
693
694struct mlx5_cqe64 {
695 u8 outer_l3_tunneled;
696 u8 rsvd0;
697 __be16 wqe_id;
698 u8 lro_tcppsh_abort_dupack;
699 u8 lro_min_ttl;
700 __be16 lro_tcp_win;
701 __be32 lro_ack_seq_num;
702 __be32 rss_hash_result;
703 u8 rss_hash_type;
704 u8 ml_path;
705 u8 rsvd20[2];
706 __be16 check_sum;
707 __be16 slid;
708 __be32 flags_rqpn;
709 u8 hds_ip_ext;
710 u8 l4_l3_hdr_type;
711 __be16 vlan_info;
712 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
713 __be32 imm_inval_pkey;
714 u8 rsvd40[4];
715 __be32 byte_cnt;
716 __be32 timestamp_h;
717 __be32 timestamp_l;
718 __be32 sop_drop_qpn;
719 __be16 wqe_counter;
720 u8 signature;
721 u8 op_own;
722};
723
724struct mlx5_mini_cqe8 {
725 union {
726 __be32 rx_hash_result;
727 struct {
728 __be16 checksum;
729 __be16 rsvd;
730 };
731 struct {
732 __be16 wqe_counter;
733 u8 s_wqe_opcode;
734 u8 reserved;
735 } s_wqe_info;
736 };
737 __be32 byte_cnt;
738};
739
740enum {
741 MLX5_NO_INLINE_DATA,
742 MLX5_INLINE_DATA32_SEG,
743 MLX5_INLINE_DATA64_SEG,
744 MLX5_COMPRESSED,
745};
746
747enum {
748 MLX5_CQE_FORMAT_CSUM = 0x1,
749};
750
751#define MLX5_MINI_CQE_ARRAY_SIZE 8
752
753static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
754{
755 return (cqe->op_own >> 2) & 0x3;
756}
757
758static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
759{
760 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
761}
762
763static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
764{
765 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
766}
767
768static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
769{
770 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
771}
772
773static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
774{
775 return cqe->outer_l3_tunneled & 0x1;
776}
777
778static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
779{
780 return !!(cqe->l4_l3_hdr_type & 0x1);
781}
782
783static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
784{
785 u32 hi, lo;
786
787 hi = be32_to_cpu(cqe->timestamp_h);
788 lo = be32_to_cpu(cqe->timestamp_l);
789
790 return (u64)lo | ((u64)hi << 32);
791}
792
793#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
794#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
795
796struct mpwrq_cqe_bc {
797 __be16 filler_consumed_strides;
798 __be16 byte_cnt;
799};
800
801static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
802{
803 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
804
805 return be16_to_cpu(bc->byte_cnt);
806}
807
808static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
809{
810 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
811}
812
813static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
814{
815 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
816
817 return mpwrq_get_cqe_bc_consumed_strides(bc);
818}
819
820static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
821{
822 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
823
824 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
825}
826
827static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
828{
829 return be16_to_cpu(cqe->wqe_counter);
830}
831
832enum {
833 CQE_L4_HDR_TYPE_NONE = 0x0,
834 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
835 CQE_L4_HDR_TYPE_UDP = 0x2,
836 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
837 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
838};
839
840enum {
841 CQE_RSS_HTYPE_IP = 0x3 << 2,
842 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
843 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
844 */
845 CQE_RSS_HTYPE_L4 = 0x3 << 6,
846 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
847 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
848 */
849};
850
851enum {
852 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
853 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
854 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
855};
856
857enum {
858 CQE_L2_OK = 1 << 0,
859 CQE_L3_OK = 1 << 1,
860 CQE_L4_OK = 1 << 2,
861};
862
863struct mlx5_sig_err_cqe {
864 u8 rsvd0[16];
865 __be32 expected_trans_sig;
866 __be32 actual_trans_sig;
867 __be32 expected_reftag;
868 __be32 actual_reftag;
869 __be16 syndrome;
870 u8 rsvd22[2];
871 __be32 mkey;
872 __be64 err_offset;
873 u8 rsvd30[8];
874 __be32 qpn;
875 u8 rsvd38[2];
876 u8 signature;
877 u8 op_own;
878};
879
880struct mlx5_wqe_srq_next_seg {
881 u8 rsvd0[2];
882 __be16 next_wqe_index;
883 u8 signature;
884 u8 rsvd1[11];
885};
886
887union mlx5_ext_cqe {
888 struct ib_grh grh;
889 u8 inl[64];
890};
891
892struct mlx5_cqe128 {
893 union mlx5_ext_cqe inl_grh;
894 struct mlx5_cqe64 cqe64;
895};
896
897enum {
898 MLX5_MKEY_STATUS_FREE = 1 << 6,
899};
900
901enum {
902 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
903 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
904 MLX5_MKEY_BSF_EN = 1 << 30,
905 MLX5_MKEY_LEN64 = 1 << 31,
906};
907
908struct mlx5_mkey_seg {
909 /* This is a two bit field occupying bits 31-30.
910 * bit 31 is always 0,
911 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
912 */
913 u8 status;
914 u8 pcie_control;
915 u8 flags;
916 u8 version;
917 __be32 qpn_mkey7_0;
918 u8 rsvd1[4];
919 __be32 flags_pd;
920 __be64 start_addr;
921 __be64 len;
922 __be32 bsfs_octo_size;
923 u8 rsvd2[16];
924 __be32 xlt_oct_size;
925 u8 rsvd3[3];
926 u8 log2_page_size;
927 u8 rsvd4[4];
928};
929
930#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
931
932enum {
933 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
934};
935
936enum {
937 VPORT_STATE_DOWN = 0x0,
938 VPORT_STATE_UP = 0x1,
939};
940
941enum {
942 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
943 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
944 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
945};
946
947enum {
948 MLX5_L3_PROT_TYPE_IPV4 = 0,
949 MLX5_L3_PROT_TYPE_IPV6 = 1,
950};
951
952enum {
953 MLX5_L4_PROT_TYPE_TCP = 0,
954 MLX5_L4_PROT_TYPE_UDP = 1,
955};
956
957enum {
958 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
959 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
960 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
961 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
962 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
963};
964
965enum {
966 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
967 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
968 MLX5_MATCH_INNER_HEADERS = 1 << 2,
969
970};
971
972enum {
973 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
974 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
975};
976
977enum {
978 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
979 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
980 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
981};
982
983enum mlx5_list_type {
984 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
985 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
986 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
987};
988
989enum {
990 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
991 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
992};
993
994enum mlx5_wol_mode {
995 MLX5_WOL_DISABLE = 0,
996 MLX5_WOL_SECURED_MAGIC = 1 << 1,
997 MLX5_WOL_MAGIC = 1 << 2,
998 MLX5_WOL_ARP = 1 << 3,
999 MLX5_WOL_BROADCAST = 1 << 4,
1000 MLX5_WOL_MULTICAST = 1 << 5,
1001 MLX5_WOL_UNICAST = 1 << 6,
1002 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1003};
1004
1005enum mlx5_mpls_supported_fields {
1006 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1007 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1008 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1009 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1010};
1011
1012enum mlx5_flex_parser_protos {
1013 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1014 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1015};
1016
1017/* MLX5 DEV CAPs */
1018
1019/* TODO: EAT.ME */
1020enum mlx5_cap_mode {
1021 HCA_CAP_OPMOD_GET_MAX = 0,
1022 HCA_CAP_OPMOD_GET_CUR = 1,
1023};
1024
1025enum mlx5_cap_type {
1026 MLX5_CAP_GENERAL = 0,
1027 MLX5_CAP_ETHERNET_OFFLOADS,
1028 MLX5_CAP_ODP,
1029 MLX5_CAP_ATOMIC,
1030 MLX5_CAP_ROCE,
1031 MLX5_CAP_IPOIB_OFFLOADS,
1032 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1033 MLX5_CAP_FLOW_TABLE,
1034 MLX5_CAP_ESWITCH_FLOW_TABLE,
1035 MLX5_CAP_ESWITCH,
1036 MLX5_CAP_RESERVED,
1037 MLX5_CAP_VECTOR_CALC,
1038 MLX5_CAP_QOS,
1039 MLX5_CAP_DEBUG,
1040 MLX5_CAP_RESERVED_14,
1041 MLX5_CAP_DEV_MEM,
1042 /* NUM OF CAP Types */
1043 MLX5_CAP_NUM
1044};
1045
1046enum mlx5_pcam_reg_groups {
1047 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1048};
1049
1050enum mlx5_pcam_feature_groups {
1051 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1052};
1053
1054enum mlx5_mcam_reg_groups {
1055 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1056};
1057
1058enum mlx5_mcam_feature_groups {
1059 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1060};
1061
1062enum mlx5_qcam_reg_groups {
1063 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1064};
1065
1066enum mlx5_qcam_feature_groups {
1067 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1068};
1069
1070/* GET Dev Caps macros */
1071#define MLX5_CAP_GEN(mdev, cap) \
1072 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1073
1074#define MLX5_CAP_GEN_MAX(mdev, cap) \
1075 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1076
1077#define MLX5_CAP_ETH(mdev, cap) \
1078 MLX5_GET(per_protocol_networking_offload_caps,\
1079 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1080
1081#define MLX5_CAP_ETH_MAX(mdev, cap) \
1082 MLX5_GET(per_protocol_networking_offload_caps,\
1083 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1084
1085#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1086 MLX5_GET(per_protocol_networking_offload_caps,\
1087 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1088
1089#define MLX5_CAP_ROCE(mdev, cap) \
1090 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1091
1092#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1093 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1094
1095#define MLX5_CAP_ATOMIC(mdev, cap) \
1096 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1097
1098#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1099 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1100
1101#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1102 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1103
1104#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1105 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1106
1107#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1108 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1109
1110#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1111 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1112
1113#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1114 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1115
1116#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1117 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1118
1119#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1120 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1121
1122#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1123 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1124
1125#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1126 MLX5_GET(flow_table_eswitch_cap, \
1127 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1128
1129#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1130 MLX5_GET(flow_table_eswitch_cap, \
1131 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1132
1133#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1134 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1135
1136#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1137 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1138
1139#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1140 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1141
1142#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1143 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1144
1145#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1146 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1147
1148#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1149 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1150
1151#define MLX5_CAP_ESW(mdev, cap) \
1152 MLX5_GET(e_switch_cap, \
1153 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1154
1155#define MLX5_CAP_ESW_MAX(mdev, cap) \
1156 MLX5_GET(e_switch_cap, \
1157 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1158
1159#define MLX5_CAP_ODP(mdev, cap)\
1160 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1161
1162#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1163 MLX5_GET(vector_calc_cap, \
1164 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1165
1166#define MLX5_CAP_QOS(mdev, cap)\
1167 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1168
1169#define MLX5_CAP_DEBUG(mdev, cap)\
1170 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1171
1172#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1173 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1174
1175#define MLX5_CAP_PCAM_REG(mdev, reg) \
1176 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1177
1178#define MLX5_CAP_MCAM_REG(mdev, reg) \
1179 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1180
1181#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1182 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1183
1184#define MLX5_CAP_QCAM_REG(mdev, fld) \
1185 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1186
1187#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1188 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1189
1190#define MLX5_CAP_FPGA(mdev, cap) \
1191 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1192
1193#define MLX5_CAP64_FPGA(mdev, cap) \
1194 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1195
1196#define MLX5_CAP_DEV_MEM(mdev, cap)\
1197 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1198
1199#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1200 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1201
1202enum {
1203 MLX5_CMD_STAT_OK = 0x0,
1204 MLX5_CMD_STAT_INT_ERR = 0x1,
1205 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1206 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1207 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1208 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1209 MLX5_CMD_STAT_RES_BUSY = 0x6,
1210 MLX5_CMD_STAT_LIM_ERR = 0x8,
1211 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1212 MLX5_CMD_STAT_IX_ERR = 0xa,
1213 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1214 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1215 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1216 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1217 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1218 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1219};
1220
1221enum {
1222 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1223 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1224 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1225 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1226 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1227 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1228 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1229 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1230 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1231 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1232};
1233
1234enum {
1235 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1236};
1237
1238static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1239{
1240 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1241 return 0;
1242 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1243}
1244
1245#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1246#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1247#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1248#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1249 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1250 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1251
1252#endif /* MLX5_DEVICE_H */