Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/bitops.h>
17#include <linux/phy.h>
18#include <linux/module.h>
19
20#define RTL821x_PHYSR 0x11
21#define RTL821x_PHYSR_DUPLEX BIT(13)
22#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
23
24#define RTL821x_INER 0x12
25#define RTL8211B_INER_INIT 0x6400
26#define RTL8211E_INER_LINK_STATUS BIT(10)
27#define RTL8211F_INER_LINK_STATUS BIT(4)
28
29#define RTL821x_INSR 0x13
30
31#define RTL821x_PAGE_SELECT 0x1f
32
33#define RTL8211F_INSR 0x1d
34
35#define RTL8211F_TX_DELAY BIT(8)
36
37#define RTL8201F_ISR 0x1e
38#define RTL8201F_IER 0x13
39
40MODULE_DESCRIPTION("Realtek PHY driver");
41MODULE_AUTHOR("Johnson Leung");
42MODULE_LICENSE("GPL");
43
44static int rtl821x_read_page(struct phy_device *phydev)
45{
46 return __phy_read(phydev, RTL821x_PAGE_SELECT);
47}
48
49static int rtl821x_write_page(struct phy_device *phydev, int page)
50{
51 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
52}
53
54static int rtl8201_ack_interrupt(struct phy_device *phydev)
55{
56 int err;
57
58 err = phy_read(phydev, RTL8201F_ISR);
59
60 return (err < 0) ? err : 0;
61}
62
63static int rtl821x_ack_interrupt(struct phy_device *phydev)
64{
65 int err;
66
67 err = phy_read(phydev, RTL821x_INSR);
68
69 return (err < 0) ? err : 0;
70}
71
72static int rtl8211f_ack_interrupt(struct phy_device *phydev)
73{
74 int err;
75
76 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
77
78 return (err < 0) ? err : 0;
79}
80
81static int rtl8201_config_intr(struct phy_device *phydev)
82{
83 u16 val;
84
85 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
86 val = BIT(13) | BIT(12) | BIT(11);
87 else
88 val = 0;
89
90 return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
91}
92
93static int rtl8211b_config_intr(struct phy_device *phydev)
94{
95 int err;
96
97 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
98 err = phy_write(phydev, RTL821x_INER,
99 RTL8211B_INER_INIT);
100 else
101 err = phy_write(phydev, RTL821x_INER, 0);
102
103 return err;
104}
105
106static int rtl8211e_config_intr(struct phy_device *phydev)
107{
108 int err;
109
110 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
111 err = phy_write(phydev, RTL821x_INER,
112 RTL8211E_INER_LINK_STATUS);
113 else
114 err = phy_write(phydev, RTL821x_INER, 0);
115
116 return err;
117}
118
119static int rtl8211f_config_intr(struct phy_device *phydev)
120{
121 u16 val;
122
123 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
124 val = RTL8211F_INER_LINK_STATUS;
125 else
126 val = 0;
127
128 return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
129}
130
131static int rtl8211f_config_init(struct phy_device *phydev)
132{
133 int ret;
134 u16 val = 0;
135
136 ret = genphy_config_init(phydev);
137 if (ret < 0)
138 return ret;
139
140 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
141 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
142 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
143 val = RTL8211F_TX_DELAY;
144
145 return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val);
146}
147
148static int rtl8211b_suspend(struct phy_device *phydev)
149{
150 phy_write(phydev, MII_MMD_DATA, BIT(9));
151
152 return genphy_suspend(phydev);
153}
154
155static int rtl8211b_resume(struct phy_device *phydev)
156{
157 phy_write(phydev, MII_MMD_DATA, 0);
158
159 return genphy_resume(phydev);
160}
161
162static struct phy_driver realtek_drvs[] = {
163 {
164 .phy_id = 0x00008201,
165 .name = "RTL8201CP Ethernet",
166 .phy_id_mask = 0x0000ffff,
167 .features = PHY_BASIC_FEATURES,
168 .flags = PHY_HAS_INTERRUPT,
169 }, {
170 .phy_id = 0x001cc816,
171 .name = "RTL8201F 10/100Mbps Ethernet",
172 .phy_id_mask = 0x001fffff,
173 .features = PHY_BASIC_FEATURES,
174 .flags = PHY_HAS_INTERRUPT,
175 .ack_interrupt = &rtl8201_ack_interrupt,
176 .config_intr = &rtl8201_config_intr,
177 .suspend = genphy_suspend,
178 .resume = genphy_resume,
179 .read_page = rtl821x_read_page,
180 .write_page = rtl821x_write_page,
181 }, {
182 .phy_id = 0x001cc912,
183 .name = "RTL8211B Gigabit Ethernet",
184 .phy_id_mask = 0x001fffff,
185 .features = PHY_GBIT_FEATURES,
186 .flags = PHY_HAS_INTERRUPT,
187 .ack_interrupt = &rtl821x_ack_interrupt,
188 .config_intr = &rtl8211b_config_intr,
189 .read_mmd = &genphy_read_mmd_unsupported,
190 .write_mmd = &genphy_write_mmd_unsupported,
191 .suspend = rtl8211b_suspend,
192 .resume = rtl8211b_resume,
193 }, {
194 .phy_id = 0x001cc914,
195 .name = "RTL8211DN Gigabit Ethernet",
196 .phy_id_mask = 0x001fffff,
197 .features = PHY_GBIT_FEATURES,
198 .flags = PHY_HAS_INTERRUPT,
199 .ack_interrupt = rtl821x_ack_interrupt,
200 .config_intr = rtl8211e_config_intr,
201 .suspend = genphy_suspend,
202 .resume = genphy_resume,
203 }, {
204 .phy_id = 0x001cc915,
205 .name = "RTL8211E Gigabit Ethernet",
206 .phy_id_mask = 0x001fffff,
207 .features = PHY_GBIT_FEATURES,
208 .flags = PHY_HAS_INTERRUPT,
209 .ack_interrupt = &rtl821x_ack_interrupt,
210 .config_intr = &rtl8211e_config_intr,
211 .suspend = genphy_suspend,
212 .resume = genphy_resume,
213 }, {
214 .phy_id = 0x001cc916,
215 .name = "RTL8211F Gigabit Ethernet",
216 .phy_id_mask = 0x001fffff,
217 .features = PHY_GBIT_FEATURES,
218 .flags = PHY_HAS_INTERRUPT,
219 .config_init = &rtl8211f_config_init,
220 .ack_interrupt = &rtl8211f_ack_interrupt,
221 .config_intr = &rtl8211f_config_intr,
222 .suspend = genphy_suspend,
223 .resume = genphy_resume,
224 .read_page = rtl821x_read_page,
225 .write_page = rtl821x_write_page,
226 },
227};
228
229module_phy_driver(realtek_drvs);
230
231static struct mdio_device_id __maybe_unused realtek_tbl[] = {
232 { 0x001cc816, 0x001fffff },
233 { 0x001cc912, 0x001fffff },
234 { 0x001cc914, 0x001fffff },
235 { 0x001cc915, 0x001fffff },
236 { 0x001cc916, 0x001fffff },
237 { }
238};
239
240MODULE_DEVICE_TABLE(mdio, realtek_tbl);