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1/* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18#ifndef __MSM_DRV_H__ 19#define __MSM_DRV_H__ 20 21#include <linux/kernel.h> 22#include <linux/clk.h> 23#include <linux/cpufreq.h> 24#include <linux/module.h> 25#include <linux/component.h> 26#include <linux/platform_device.h> 27#include <linux/pm.h> 28#include <linux/pm_runtime.h> 29#include <linux/slab.h> 30#include <linux/list.h> 31#include <linux/iommu.h> 32#include <linux/types.h> 33#include <linux/of_graph.h> 34#include <linux/of_device.h> 35#include <asm/sizes.h> 36 37#include <drm/drmP.h> 38#include <drm/drm_atomic.h> 39#include <drm/drm_atomic_helper.h> 40#include <drm/drm_crtc_helper.h> 41#include <drm/drm_plane_helper.h> 42#include <drm/drm_fb_helper.h> 43#include <drm/msm_drm.h> 44#include <drm/drm_gem.h> 45 46struct msm_kms; 47struct msm_gpu; 48struct msm_mmu; 49struct msm_mdss; 50struct msm_rd_state; 51struct msm_perf_state; 52struct msm_gem_submit; 53struct msm_fence_context; 54struct msm_gem_address_space; 55struct msm_gem_vma; 56 57struct msm_file_private { 58 rwlock_t queuelock; 59 struct list_head submitqueues; 60 int queueid; 61}; 62 63enum msm_mdp_plane_property { 64 PLANE_PROP_ZPOS, 65 PLANE_PROP_ALPHA, 66 PLANE_PROP_PREMULTIPLIED, 67 PLANE_PROP_MAX_NUM 68}; 69 70struct msm_vblank_ctrl { 71 struct work_struct work; 72 struct list_head event_list; 73 spinlock_t lock; 74}; 75 76#define MSM_GPU_MAX_RINGS 4 77 78struct msm_drm_private { 79 80 struct drm_device *dev; 81 82 struct msm_kms *kms; 83 84 /* subordinate devices, if present: */ 85 struct platform_device *gpu_pdev; 86 87 /* top level MDSS wrapper device (for MDP5 only) */ 88 struct msm_mdss *mdss; 89 90 /* possibly this should be in the kms component, but it is 91 * shared by both mdp4 and mdp5.. 92 */ 93 struct hdmi *hdmi; 94 95 /* eDP is for mdp5 only, but kms has not been created 96 * when edp_bind() and edp_init() are called. Here is the only 97 * place to keep the edp instance. 98 */ 99 struct msm_edp *edp; 100 101 /* DSI is shared by mdp4 and mdp5 */ 102 struct msm_dsi *dsi[2]; 103 104 /* when we have more than one 'msm_gpu' these need to be an array: */ 105 struct msm_gpu *gpu; 106 struct msm_file_private *lastctx; 107 108 struct drm_fb_helper *fbdev; 109 110 struct msm_rd_state *rd; /* debugfs to dump all submits */ 111 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 112 struct msm_perf_state *perf; 113 114 /* list of GEM objects: */ 115 struct list_head inactive_list; 116 117 struct workqueue_struct *wq; 118 struct workqueue_struct *atomic_wq; 119 120 unsigned int num_planes; 121 struct drm_plane *planes[16]; 122 123 unsigned int num_crtcs; 124 struct drm_crtc *crtcs[8]; 125 126 unsigned int num_encoders; 127 struct drm_encoder *encoders[8]; 128 129 unsigned int num_bridges; 130 struct drm_bridge *bridges[8]; 131 132 unsigned int num_connectors; 133 struct drm_connector *connectors[8]; 134 135 /* Properties */ 136 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 137 138 /* VRAM carveout, used when no IOMMU: */ 139 struct { 140 unsigned long size; 141 dma_addr_t paddr; 142 /* NOTE: mm managed at the page level, size is in # of pages 143 * and position mm_node->start is in # of pages: 144 */ 145 struct drm_mm mm; 146 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 147 } vram; 148 149 struct notifier_block vmap_notifier; 150 struct shrinker shrinker; 151 152 struct msm_vblank_ctrl vblank_ctrl; 153}; 154 155struct msm_format { 156 uint32_t pixel_format; 157}; 158 159int msm_atomic_prepare_fb(struct drm_plane *plane, 160 struct drm_plane_state *new_state); 161void msm_atomic_commit_tail(struct drm_atomic_state *state); 162struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 163void msm_atomic_state_clear(struct drm_atomic_state *state); 164void msm_atomic_state_free(struct drm_atomic_state *state); 165 166void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 167 struct msm_gem_vma *vma, struct sg_table *sgt); 168int msm_gem_map_vma(struct msm_gem_address_space *aspace, 169 struct msm_gem_vma *vma, struct sg_table *sgt, int npages); 170 171void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 172 173struct msm_gem_address_space * 174msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, 175 const char *name); 176 177void msm_gem_submit_free(struct msm_gem_submit *submit); 178int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 179 struct drm_file *file); 180 181void msm_gem_shrinker_init(struct drm_device *dev); 182void msm_gem_shrinker_cleanup(struct drm_device *dev); 183 184int msm_gem_mmap_obj(struct drm_gem_object *obj, 185 struct vm_area_struct *vma); 186int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 187int msm_gem_fault(struct vm_fault *vmf); 188uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 189int msm_gem_get_iova(struct drm_gem_object *obj, 190 struct msm_gem_address_space *aspace, uint64_t *iova); 191uint64_t msm_gem_iova(struct drm_gem_object *obj, 192 struct msm_gem_address_space *aspace); 193struct page **msm_gem_get_pages(struct drm_gem_object *obj); 194void msm_gem_put_pages(struct drm_gem_object *obj); 195void msm_gem_put_iova(struct drm_gem_object *obj, 196 struct msm_gem_address_space *aspace); 197int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 198 struct drm_mode_create_dumb *args); 199int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 200 uint32_t handle, uint64_t *offset); 201struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 202void *msm_gem_prime_vmap(struct drm_gem_object *obj); 203void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 204int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 205struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj); 206struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 207 struct dma_buf_attachment *attach, struct sg_table *sg); 208int msm_gem_prime_pin(struct drm_gem_object *obj); 209void msm_gem_prime_unpin(struct drm_gem_object *obj); 210void *msm_gem_get_vaddr(struct drm_gem_object *obj); 211void *msm_gem_get_vaddr_active(struct drm_gem_object *obj); 212void msm_gem_put_vaddr(struct drm_gem_object *obj); 213int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); 214int msm_gem_sync_object(struct drm_gem_object *obj, 215 struct msm_fence_context *fctx, bool exclusive); 216void msm_gem_move_to_active(struct drm_gem_object *obj, 217 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence); 218void msm_gem_move_to_inactive(struct drm_gem_object *obj); 219int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 220int msm_gem_cpu_fini(struct drm_gem_object *obj); 221void msm_gem_free_object(struct drm_gem_object *obj); 222int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 223 uint32_t size, uint32_t flags, uint32_t *handle); 224struct drm_gem_object *msm_gem_new(struct drm_device *dev, 225 uint32_t size, uint32_t flags); 226struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, 227 uint32_t size, uint32_t flags); 228void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, 229 uint32_t flags, struct msm_gem_address_space *aspace, 230 struct drm_gem_object **bo, uint64_t *iova); 231void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, 232 uint32_t flags, struct msm_gem_address_space *aspace, 233 struct drm_gem_object **bo, uint64_t *iova); 234struct drm_gem_object *msm_gem_import(struct drm_device *dev, 235 struct dma_buf *dmabuf, struct sg_table *sgt); 236 237int msm_framebuffer_prepare(struct drm_framebuffer *fb, 238 struct msm_gem_address_space *aspace); 239void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 240 struct msm_gem_address_space *aspace); 241uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 242 struct msm_gem_address_space *aspace, int plane); 243struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 244const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 245struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 246 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 247struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 248 int w, int h, int p, uint32_t format); 249 250struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 251void msm_fbdev_free(struct drm_device *dev); 252 253struct hdmi; 254int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 255 struct drm_encoder *encoder); 256void __init msm_hdmi_register(void); 257void __exit msm_hdmi_unregister(void); 258 259struct msm_edp; 260void __init msm_edp_register(void); 261void __exit msm_edp_unregister(void); 262int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 263 struct drm_encoder *encoder); 264 265struct msm_dsi; 266#ifdef CONFIG_DRM_MSM_DSI 267void __init msm_dsi_register(void); 268void __exit msm_dsi_unregister(void); 269int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 270 struct drm_encoder *encoder); 271#else 272static inline void __init msm_dsi_register(void) 273{ 274} 275static inline void __exit msm_dsi_unregister(void) 276{ 277} 278static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 279 struct drm_device *dev, 280 struct drm_encoder *encoder) 281{ 282 return -EINVAL; 283} 284#endif 285 286void __init msm_mdp_register(void); 287void __exit msm_mdp_unregister(void); 288 289#ifdef CONFIG_DEBUG_FS 290void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 291void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 292void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 293int msm_debugfs_late_init(struct drm_device *dev); 294int msm_rd_debugfs_init(struct drm_minor *minor); 295void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 296void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 297 const char *fmt, ...); 298int msm_perf_debugfs_init(struct drm_minor *minor); 299void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 300#else 301static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 302static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 303 const char *fmt, ...) {} 304static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 305static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 306#endif 307 308struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 309void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 310 const char *dbgname); 311void msm_writel(u32 data, void __iomem *addr); 312u32 msm_readl(const void __iomem *addr); 313 314struct msm_gpu_submitqueue; 315int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); 316struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, 317 u32 id); 318int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 319 u32 prio, u32 flags, u32 *id); 320int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); 321void msm_submitqueue_close(struct msm_file_private *ctx); 322 323void msm_submitqueue_destroy(struct kref *kref); 324 325 326#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 327#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 328 329static inline int align_pitch(int width, int bpp) 330{ 331 int bytespp = (bpp + 7) / 8; 332 /* adreno needs pitch aligned to 32 pixels: */ 333 return bytespp * ALIGN(width, 32); 334} 335 336/* for the generated headers: */ 337#define INVALID_IDX(idx) ({BUG(); 0;}) 338#define fui(x) ({BUG(); 0;}) 339#define util_float_to_half(x) ({BUG(); 0;}) 340 341 342#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 343 344/* for conditionally setting boolean flag(s): */ 345#define COND(bool, val) ((bool) ? (val) : 0) 346 347static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 348{ 349 ktime_t now = ktime_get(); 350 unsigned long remaining_jiffies; 351 352 if (ktime_compare(*timeout, now) < 0) { 353 remaining_jiffies = 0; 354 } else { 355 ktime_t rem = ktime_sub(*timeout, now); 356 struct timespec ts = ktime_to_timespec(rem); 357 remaining_jiffies = timespec_to_jiffies(&ts); 358 } 359 360 return remaining_jiffies; 361} 362 363#endif /* __MSM_DRV_H__ */