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Linux kernel mirror (for testing)
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1/*
2 * Copyright © 2012-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DPLL_MGR_H_
26#define _INTEL_DPLL_MGR_H_
27
28/*FIXME: Move this to a more appropriate place. */
29#define abs_diff(a, b) ({ \
30 typeof(a) __a = (a); \
31 typeof(b) __b = (b); \
32 (void) (&__a == &__b); \
33 __a > __b ? (__a - __b) : (__b - __a); })
34
35struct drm_i915_private;
36struct intel_crtc;
37struct intel_crtc_state;
38struct intel_encoder;
39
40struct intel_shared_dpll;
41struct intel_dpll_mgr;
42
43/**
44 * enum intel_dpll_id - possible DPLL ids
45 *
46 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
47 */
48enum intel_dpll_id {
49 /**
50 * @DPLL_ID_PRIVATE: non-shared dpll in use
51 */
52 DPLL_ID_PRIVATE = -1,
53
54 /**
55 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
56 */
57 DPLL_ID_PCH_PLL_A = 0,
58 /**
59 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
60 */
61 DPLL_ID_PCH_PLL_B = 1,
62
63
64 /**
65 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
66 */
67 DPLL_ID_WRPLL1 = 0,
68 /**
69 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
70 */
71 DPLL_ID_WRPLL2 = 1,
72 /**
73 * @DPLL_ID_SPLL: HSW and BDW SPLL
74 */
75 DPLL_ID_SPLL = 2,
76 /**
77 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
78 */
79 DPLL_ID_LCPLL_810 = 3,
80 /**
81 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
82 */
83 DPLL_ID_LCPLL_1350 = 4,
84 /**
85 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
86 */
87 DPLL_ID_LCPLL_2700 = 5,
88
89
90 /**
91 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
92 */
93 DPLL_ID_SKL_DPLL0 = 0,
94 /**
95 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
96 */
97 DPLL_ID_SKL_DPLL1 = 1,
98 /**
99 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
100 */
101 DPLL_ID_SKL_DPLL2 = 2,
102 /**
103 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
104 */
105 DPLL_ID_SKL_DPLL3 = 3,
106
107
108 /**
109 * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
110 */
111 DPLL_ID_ICL_DPLL0 = 0,
112 /**
113 * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
114 */
115 DPLL_ID_ICL_DPLL1 = 1,
116 /**
117 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
118 */
119 DPLL_ID_ICL_MGPLL1 = 2,
120 /**
121 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
122 */
123 DPLL_ID_ICL_MGPLL2 = 3,
124 /**
125 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
126 */
127 DPLL_ID_ICL_MGPLL3 = 4,
128 /**
129 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
130 */
131 DPLL_ID_ICL_MGPLL4 = 5,
132};
133#define I915_NUM_PLLS 6
134
135struct intel_dpll_hw_state {
136 /* i9xx, pch plls */
137 uint32_t dpll;
138 uint32_t dpll_md;
139 uint32_t fp0;
140 uint32_t fp1;
141
142 /* hsw, bdw */
143 uint32_t wrpll;
144 uint32_t spll;
145
146 /* skl */
147 /*
148 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
149 * lower part of ctrl1 and they get shifted into position when writing
150 * the register. This allows us to easily compare the state to share
151 * the DPLL.
152 */
153 uint32_t ctrl1;
154 /* HDMI only, 0 when used for DP */
155 uint32_t cfgcr1, cfgcr2;
156
157 /* cnl */
158 uint32_t cfgcr0;
159 /* CNL also uses cfgcr1 */
160
161 /* bxt */
162 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
163 pcsdw12;
164
165 /*
166 * ICL uses the following, already defined:
167 * uint32_t cfgcr0, cfgcr1;
168 */
169 uint32_t mg_refclkin_ctl;
170 uint32_t mg_clktop2_coreclkctl1;
171 uint32_t mg_clktop2_hsclkctl;
172 uint32_t mg_pll_div0;
173 uint32_t mg_pll_div1;
174 uint32_t mg_pll_lf;
175 uint32_t mg_pll_frac_lock;
176 uint32_t mg_pll_ssc;
177 uint32_t mg_pll_bias;
178 uint32_t mg_pll_tdc_coldst_bias;
179};
180
181/**
182 * struct intel_shared_dpll_state - hold the DPLL atomic state
183 *
184 * This structure holds an atomic state for the DPLL, that can represent
185 * either its current state (in struct &intel_shared_dpll) or a desired
186 * future state which would be applied by an atomic mode set (stored in
187 * a struct &intel_atomic_state).
188 *
189 * See also intel_get_shared_dpll() and intel_release_shared_dpll().
190 */
191struct intel_shared_dpll_state {
192 /**
193 * @crtc_mask: mask of CRTC using this DPLL, active or not
194 */
195 unsigned crtc_mask;
196
197 /**
198 * @hw_state: hardware configuration for the DPLL stored in
199 * struct &intel_dpll_hw_state.
200 */
201 struct intel_dpll_hw_state hw_state;
202};
203
204/**
205 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
206 */
207struct intel_shared_dpll_funcs {
208 /**
209 * @prepare:
210 *
211 * Optional hook to perform operations prior to enabling the PLL.
212 * Called from intel_prepare_shared_dpll() function unless the PLL
213 * is already enabled.
214 */
215 void (*prepare)(struct drm_i915_private *dev_priv,
216 struct intel_shared_dpll *pll);
217
218 /**
219 * @enable:
220 *
221 * Hook for enabling the pll, called from intel_enable_shared_dpll()
222 * if the pll is not already enabled.
223 */
224 void (*enable)(struct drm_i915_private *dev_priv,
225 struct intel_shared_dpll *pll);
226
227 /**
228 * @disable:
229 *
230 * Hook for disabling the pll, called from intel_disable_shared_dpll()
231 * only when it is safe to disable the pll, i.e., there are no more
232 * tracked users for it.
233 */
234 void (*disable)(struct drm_i915_private *dev_priv,
235 struct intel_shared_dpll *pll);
236
237 /**
238 * @get_hw_state:
239 *
240 * Hook for reading the values currently programmed to the DPLL
241 * registers. This is used for initial hw state readout and state
242 * verification after a mode set.
243 */
244 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
245 struct intel_shared_dpll *pll,
246 struct intel_dpll_hw_state *hw_state);
247};
248
249/**
250 * struct dpll_info - display PLL platform specific info
251 */
252struct dpll_info {
253 /**
254 * @name: DPLL name; used for logging
255 */
256 const char *name;
257
258 /**
259 * @funcs: platform specific hooks
260 */
261 const struct intel_shared_dpll_funcs *funcs;
262
263 /**
264 * @id: unique indentifier for this DPLL; should match the index in the
265 * dev_priv->shared_dplls array
266 */
267 enum intel_dpll_id id;
268
269#define INTEL_DPLL_ALWAYS_ON (1 << 0)
270 /**
271 * @flags:
272 *
273 * INTEL_DPLL_ALWAYS_ON
274 * Inform the state checker that the DPLL is kept enabled even if
275 * not in use by any CRTC.
276 */
277 uint32_t flags;
278};
279
280/**
281 * struct intel_shared_dpll - display PLL with tracked state and users
282 */
283struct intel_shared_dpll {
284 /**
285 * @state:
286 *
287 * Store the state for the pll, including the its hw state
288 * and CRTCs using it.
289 */
290 struct intel_shared_dpll_state state;
291
292 /**
293 * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
294 */
295 unsigned active_mask;
296
297 /**
298 * @on: is the PLL actually active? Disabled during modeset
299 */
300 bool on;
301
302 /**
303 * @info: platform specific info
304 */
305 const struct dpll_info *info;
306};
307
308#define SKL_DPLL0 0
309#define SKL_DPLL1 1
310#define SKL_DPLL2 2
311#define SKL_DPLL3 3
312
313/* shared dpll functions */
314struct intel_shared_dpll *
315intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
316 enum intel_dpll_id id);
317enum intel_dpll_id
318intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
319 struct intel_shared_dpll *pll);
320void assert_shared_dpll(struct drm_i915_private *dev_priv,
321 struct intel_shared_dpll *pll,
322 bool state);
323#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
324#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
325struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
326 struct intel_crtc_state *state,
327 struct intel_encoder *encoder);
328void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
329 struct intel_crtc *crtc,
330 struct drm_atomic_state *state);
331void intel_prepare_shared_dpll(struct intel_crtc *crtc);
332void intel_enable_shared_dpll(struct intel_crtc *crtc);
333void intel_disable_shared_dpll(struct intel_crtc *crtc);
334void intel_shared_dpll_swap_state(struct drm_atomic_state *state);
335void intel_shared_dpll_init(struct drm_device *dev);
336
337void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
338 struct intel_dpll_hw_state *hw_state);
339
340#endif /* _INTEL_DPLL_MGR_H_ */